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71. 发明申请

US20080173906A1 ENHANCED MOBILITY CMOS TRANSISTORS WITH A V-SHAPED CHANNEL WITH SELF-ALIGNMENT TO SHALLOW TRENCH ISOLATION 失效
标题翻译：具有自对准功能的V形通道的增强型移动CMOS晶体管，以便进行分离隔离
公开(公告)号：US20080173906A1
公开(公告)日：2008-07-24
申请号：US11624931
申请日：2007-01-19
申请人： Huilong Zhu , Thomas W. Dyer
发明人： Huilong Zhu , Thomas W. Dyer
IPC分类号： H01L29/04 , H01L21/306
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/823828 , H01L27/11 , H01L27/1104 , H01L29/1037 , H01L29/4236 , H01L29/66621 , H01L29/7853
摘要： The present invention provides structures and methods for a transistor formed on a V-shaped groove. The V-shaped groove contains two crystallographic facets joined by a ridge. The facets have different crystallographic orientations than what a semiconductor substrate normally provides such as the substrate orientation or orientations orthogonal to the substrate orientation. Unlike the prior art, the V-shaped groove is formed self-aligned to the shallow trench isolation, eliminating the need to precisely align the V-shaped grooves with lithographic means. The electrical properties of the new facets, specifically, the enhanced carrier mobility, are utilized to enhance the performance of transistors. In a transistor with a channel on the facets that are joined to form a V-shaped profile, the current flows in the direction of the ridge joining the facets avoiding any inflection in the direction of the current.
摘要翻译：本发明提供了形成在V形槽上的晶体管的结构和方法。 V形槽包含两个通过脊连接的结晶面。这些刻面具有与半导体衬底通常提供的不同的晶体取向，例如衬底取向或与衬底取向正交的取向。与现有技术不同，V形槽形成为与浅沟槽隔离自对准，从而不需要将V形槽与光刻装置精确对准。新面的电特性，特别是增强的载流子迁移率被用于增强晶体管的性能。在具有被连接以形成V形轮廓的小平面上的通道的晶体管中，电流沿连接小面的脊的方向流动，以避免在电流方向上的任何拐点。

72. 发明申请

US20080171420A1 STRUCTURE AND METHOD TO FORM IMPROVED ISOLATION IN A SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件中形成改进隔离的结构和方法
公开(公告)号：US20080171420A1
公开(公告)日：2008-07-17
申请号：US11622057
申请日：2007-01-11
申请人： Haining S. Yang , Thomas W. Dyer , William C. Wille
发明人： Haining S. Yang , Thomas W. Dyer , William C. Wille
IPC分类号： H01L21/76
CPC分类号： H01L21/823878 , H01L21/76227 , H01L21/76237
摘要： A method is disclosed for forming an STI (shallow trench isolation) in a substrate during CMOS (complementary metal-oxide semiconductor) semiconductor fabrication which includes providing at least two wells including dopants. A pad layer may be formed on a top surface of the substrate and a partial STI trench is etched in the upper portion of the substrate followed by etching to form a full STI trench. Boron is implanted in a lower area of the full STI trench forming an implant area which is anodized to form a porous silicon region, which is then oxidized to form a oxidized region. A dielectric layer is formed over the silicon nitride layer filling the full STI trench to provide, after etching, at least two electrical component areas on the top surface of the substrate having the full STI trench therebetween.
摘要翻译：公开了一种用于在CMOS（互补金属氧化物半导体）半导体制造期间在衬底中形成STI（浅沟槽隔离）的方法，其包括提供至少两个包括掺杂剂的阱。衬底层可以形成在衬底的顶表面上，并且在衬底的上部蚀刻部分STI沟槽，然后蚀刻以形成完整的STI沟槽。硼被植入整个STI沟槽的下部区域，形成一个阳极氧化以形成多孔硅区域的植入区域，然后被氧化形成氧化区域。在填充整个STI沟槽的氮化硅层上形成介电层，在蚀刻之后，在衬底的顶表面上提供至少两个具有全部STI沟槽的电气部件区域。

73. 发明申请

US20080169535A1 SUB-LITHOGRAPHIC FACETING FOR MOSFET PERFORMANCE ENHANCEMENT 审中-公开
标题翻译：用于MOSFET性能增强的次平面成像
公开(公告)号：US20080169535A1
公开(公告)日：2008-07-17
申请号：US11622588
申请日：2007-01-12
申请人： Shahid A. Butt , Thomas W. Dyer , Oh-Jung Kwon , Jack A. Mandelman , Haining S. Yang
发明人： Shahid A. Butt , Thomas W. Dyer , Oh-Jung Kwon , Jack A. Mandelman , Haining S. Yang
IPC分类号： H01L29/06 , H01L21/311
CPC分类号： H01L21/3086 , H01L21/28123 , H01L21/3088 , H01L21/823807 , H01L29/0673 , H01L29/1037 , H01L29/78
摘要： The present invention provides structures and methods for providing multiple parallel V-shaped faceted grooves with sub-lithographic widths on a semiconductor substrate for enhanced performance MOSFETs. A self-aligning self-assembling material is used to pattern multiple parallel sub-lithographic lines. By employing an anisotropic etch that produces crystallographic facets on a semiconductor surface, multiple adjoining parallel V-shaped grooves with sub-lithographic groove widths are formed. While providing enhanced mobility for the MOSFET, the width of the MOSFET is not limited by the depth of focus in subsequent lithographic steps or the thickness of semiconductor layer above a BOX layer due to the sub-lithographic widths of the V-shaped grooves and the consequent reduction in the variation of the vertical profile. Also, the MOSFET has a well defined threshold voltage due to the narrow widths of each facet.
摘要翻译：本发明提供了用于在半导体衬底上提供具有亚光刻宽度的多个平行V形刻面槽以提高性能MOSFET的结构和方法。使用自对准自组装材料来对多个平行的次平版印刷线进行图案化。通过采用在半导体表面上产生结晶小面的各向异性蚀刻，形成具有亚光刻槽宽度的多个相邻的平行V形槽。在为MOSFET提供增强的移动性的同时，MOSFET的宽度不受后续光刻步骤中的深度深度或BOX层上方的半导体层厚度的限制，这是由于V形沟槽的次平版印刷宽度和从而导致垂直剖面变化的减小。此外，由于每个刻面的窄宽度，MOSFET具有明确的阈值电压。

74. 发明申请

US20080111200A1 FORMING CONDUCTIVE STUD FOR SEMICONDUCTIVE DEVICES 失效
标题翻译：形成用于半导体器件的导电陶瓷
公开(公告)号：US20080111200A1
公开(公告)日：2008-05-15
申请号：US11559574
申请日：2006-11-14
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823871 , H01L21/76895 , H01L21/76897 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7843
摘要： Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer reaching a contact area of the semiconductor device, the opening being away from a protected area of the semiconductor device; and filling the opening with a conductive material to form the conductive stud. One embodiment may further include forming a dielectric liner directly on top of the semiconductor device, and forming the protective layer on top of the dielectric liner. Embodiments of the present invention also provide a semiconductor device made thereof.
摘要翻译：本发明的实施例提供一种形成与半导体器件接触的导电柱的方法。该方法包括形成覆盖半导体器件的保护层; 选择性地将开口向下蚀刻穿过保护层到达半导体器件的接触区域，该开口远离半导体器件的保护区域; 并用导电材料填充开口以形成导电柱。一个实施例还可以包括直接在半导体器件的顶部上形成电介质衬垫，以及在电介质衬垫的顶部上形成保护层。本发明的实施例还提供由其制成的半导体器件。

75. 发明申请

US20080054313A1 DEVICE STRUCTURES INCLUDING BACKSIDE CONTACTS, AND METHODS FOR FORMING SAME 有权
标题翻译：包括背面接触的装置结构及其形成方法
公开(公告)号：US20080054313A1
公开(公告)日：2008-03-06
申请号：US11468068
申请日：2006-08-29
申请人： Thomas W. Dyer , Haining Yang
发明人： Thomas W. Dyer , Haining Yang
IPC分类号： H01L29/80
CPC分类号： H01L21/76898 , G03F9/7084 , H01L23/544 , H01L24/02 , H01L2223/54453 , H01L2924/01074 , H01L2924/12044 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043
摘要： The present invention relates to device structures having backside contacts that extend from a back surface of a substrate through the substrate to electrically contact frontside semiconductor devices. The substrate preferably further includes one or more alignment structures located therein, each of which is sufficiently visible at the back surface of the substrate. In this manner, backside lithographic alignment can be carried out using such alignment structures to form at least one back contact opening in a patterned resist layer over the back surface of the substrate. The formed back contact opening is lithographically aligned with the front semiconductor device and can be etched to form a back contact via that extends from the back surface of the substrate onto the front semiconductor device. Filling of the back contact via with a conductive material results in a conductive back contact that electrically contacts the front semiconductor device.
摘要翻译：本发明涉及具有从衬底的背表面延伸穿过衬底到背面半导体器件的背面接触的器件结构。基板优选地还包括位于其中的一个或多个对准结构，其中每个在基板的背面处足够可见。以这种方式，可以使用这种对准结构来进行背面光刻对准，以在衬底的背面上形成图案化抗蚀剂层中的至少一个后接触开口。形成的后接触开口与前半导体器件光刻对准，并且可以被蚀刻以形成从衬底的背面延伸到前半导体器件上的后接触。用导电材料填充背面接触孔导致与前半导体器件电接触的导电背接触。

76. 发明授权

US06809368B2 TTO nitride liner for improved collar protection and TTO reliability 失效
公开(公告)号：US06809368B2
公开(公告)日：2004-10-26
申请号：US09832605
申请日：2001-04-11
申请人： Rama Divakaruni , Thomas W. Dyer , Rajeev Malik , Jack A. Mandelman , Venkatachalam C. Jaiprakash
发明人： Rama Divakaruni , Thomas W. Dyer , Rajeev Malik , Jack A. Mandelman , Venkatachalam C. Jaiprakash
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L21/31612 , H01L21/3185 , H01L27/10867
摘要： A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the formation of a vertical MOSFET DRAM cell device. This liner is subsequently removed after TTO sidewall etch. One function of this liner is to protect the collar oxide from being etched during the TTO oxide sidewall etch and generally provides lateral etch protection which is not realized in the current processing scheme. The process sequence does not rely on previously deposited films for collar protection, and decouples TTO sidewall etch protection from previous processing steps to provide additional process flexibility, such as allowing a thinner strap Cut Mask nitride and greater nitride etching during node nitride removal and buried strap nitrided interface removal. Advantageously, the presence of the nitride liner beneath the TTO reduces possibility of TTO dielectric breakdown between the gate and capacitor node electrode of the vertical MOSFET DRAM cell, while assuring strap diffusion to gate conductor overlap.

77. 发明授权

US06518616B2 Vertical gate top engineering for improved GC and CB process windows 有权
公开(公告)号：US06518616B2
公开(公告)日：2003-02-11
申请号：US09837799
申请日：2001-04-18
申请人： Thomas W. Dyer , Stephan P. Kudelka , Venkatachaiam C. Jaiprakash , Carl J. Radens
发明人： Thomas W. Dyer , Stephan P. Kudelka , Venkatachaiam C. Jaiprakash , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10888
摘要： A method for a memory cell has a trench capacitor and a vertical transistor adjacent to the capacitor. The vertical transistor has a gate conductor above the trench capacitor. The upper portion of the gate conductor is narrower than the lower portion of the gate conductor. The memory cell further includes spacers adjacent the upper portion of the gate conductor and a bitline contact adjacent to the gate conductor. The spacers reduce short circuits between the bitline contact and the gate conductor. The gate contact above the gate conductor has an insulator which separates the gate contact from the bitline. The difference between the width of the upper and lower portions of the gate conductor reduces short circuits between the bitline contact and the gate conductor.

78. 发明申请

US20140061914A1 DOPING OF COPPER WIRING STRUCTURES IN BACK END OF LINE PROCESSING 有权
公开(公告)号：US20140061914A1
公开(公告)日：2014-03-06
申请号：US13599256
申请日：2012-08-30
申请人： Thomas W. Dyer , Daniel C. Edelstein , Tze-man Ko , Andrew H. Simon , Wei-tsu Tseng
发明人： Thomas W. Dyer , Daniel C. Edelstein , Tze-man Ko , Andrew H. Simon , Wei-tsu Tseng
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76846 , H01L21/76849 , H01L21/76867 , H01L21/76873 , H01L21/76886 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.

79. 发明授权

US08362531B2 Method of patterning semiconductor structure and structure thereof 有权
标题翻译：图案化半导体结构及其结构的方法
公开(公告)号：US08362531B2
公开(公告)日：2013-01-29
申请号：US13102007
申请日：2011-05-05
申请人： Thomas W. Dyer , James J. Toomey
发明人： Thomas W. Dyer , James J. Toomey
IPC分类号： H01L29/80
CPC分类号： H01L21/8258 , H01L21/0337 , H01L21/28123 , H01L21/31144
摘要： Method of patterning a semiconductor structure is disclosed. The method involves crystallographic etching techniques to enhance a patterned monocrystalline layer as a hard mask. In one embodiment, the method includes bonding a monocrystalline silicon layer to a non-crystalline protective layer; patterning the monocrystalline layer to form a hard mask; enhancing the pattern of the hard mask; stripping the hard mask after conventional etching of protective layer; and forming a gate oxide thereon. The enhanced patterning of the hard mask is performed with crystallographic etching to replace optical effects of rounding and dimension narrowing at the ends of a defined region with straight edges and sharp corners. A resulting structure from the use of the enhanced patterned hard mask includes a layer of composite materials on the substrate of the semiconductor structure. The layer of composite materials includes different materials in discrete blocks defined by straight edges within the layer.
摘要翻译：公开了图案化半导体结构的方法。该方法涉及晶体蚀刻技术以增强作为硬掩模的图案化单晶层。在一个实施例中，该方法包括将单晶硅层结合到非结晶保护层; 图案化单晶层以形成硬掩模; 增强硬面膜的图案; 常规蚀刻保护层后剥去硬掩模; 并在其上形成栅极氧化物。通过结晶蚀刻来进行硬掩模的增强图案化，以取代在具有直边和锐角的限定区域的端部处的圆化和尺寸变窄的光学效应。使用增强型图案化硬掩模的结果包括在半导体结构的衬底上的复合材料层。复合材料层包括在层内由直边限定的离散块中的不同材料。

80. 发明授权

US08198194B2 Methods of forming p-channel field effect transistors having SiGe source/drain regions 有权
标题翻译：形成具有SiGe源极/漏极区域的p沟道场效应晶体管的方法
公开(公告)号：US08198194B2
公开(公告)日：2012-06-12
申请号：US12729486
申请日：2010-03-23
申请人： Jong Ho Yang , Hyung-rae Lee , Jin-Ping Han , Chung Woh Lai , Henry K. Utomo , Thomas W. Dyer
发明人： Jong Ho Yang , Hyung-rae Lee , Jin-Ping Han , Chung Woh Lai , Henry K. Utomo , Thomas W. Dyer
IPC分类号： H01L21/311
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.
摘要翻译：形成p沟道MOSFET的方法使用在制造过程中相对较早执行的光晕注入步骤。这些方法包括在半导体衬底上形成其上具有第一侧壁间隔物的栅电极，然后在栅电极上形成牺牲侧壁间隔层。然后在栅电极上图案化掩模层。选择性地蚀刻牺牲侧壁间隔层，以使用图案化掩模层作为蚀刻掩模在第一侧壁间隔物上限定牺牲侧壁间隔物。然后使用牺牲侧壁间隔件作为植入物掩模，将掺杂剂的PFET晕注入物执行到邻近栅电极延伸的部分半导体衬底。在该注入步骤之后，源极和漏极区沟槽在栅电极的相对侧被蚀刻到半导体衬底中。然后通过在其中外延生长SiGe源极和漏极区域来填充这些源极和漏极区沟槽。

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