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1. 发明授权

US06809368B2 TTO nitride liner for improved collar protection and TTO reliability 失效
公开(公告)号：US06809368B2
公开(公告)日：2004-10-26
申请号：US09832605
申请日：2001-04-11
申请人： Rama Divakaruni , Thomas W. Dyer , Rajeev Malik , Jack A. Mandelman , Venkatachalam C. Jaiprakash
发明人： Rama Divakaruni , Thomas W. Dyer , Rajeev Malik , Jack A. Mandelman , Venkatachalam C. Jaiprakash
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L21/31612 , H01L21/3185 , H01L27/10867
摘要： A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the formation of a vertical MOSFET DRAM cell device. This liner is subsequently removed after TTO sidewall etch. One function of this liner is to protect the collar oxide from being etched during the TTO oxide sidewall etch and generally provides lateral etch protection which is not realized in the current processing scheme. The process sequence does not rely on previously deposited films for collar protection, and decouples TTO sidewall etch protection from previous processing steps to provide additional process flexibility, such as allowing a thinner strap Cut Mask nitride and greater nitride etching during node nitride removal and buried strap nitrided interface removal. Advantageously, the presence of the nitride liner beneath the TTO reduces possibility of TTO dielectric breakdown between the gate and capacitor node electrode of the vertical MOSFET DRAM cell, while assuring strap diffusion to gate conductor overlap.

2. 发明授权

US06897107B2 Method for forming TTO nitride liner for improved collar protection and TTO reliability 失效
标题翻译：用于形成TTO氮化物衬垫以改善套环保护和TTO可靠性的方法
公开(公告)号：US06897107B2
公开(公告)日：2005-05-24
申请号：US10720490
申请日：2003-11-24
申请人： Rama Divakaruni , Thomas W. Dyer , Rajeev Malik , Jack A. Mandelman , Venkatachajam C. Jaiprakash
发明人： Rama Divakaruni , Thomas W. Dyer , Rajeev Malik , Jack A. Mandelman , Venkatachajam C. Jaiprakash
IPC分类号： H01L21/316 , H01L21/318 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/10864 , H01L21/31612 , H01L21/3185 , H01L27/10867
摘要： A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the formation of a vertical MOSFET DRAM cell device. This liner is subsequently removed after TTO sidewall etch. One function of this liner is to protect the collar oxide from being etched during the TTO oxide sidewall etch and generally provides lateral etch protection which is not realized in the current processing scheme. The process sequence does not rely on previously deposited films for collar protection, and decouples TTO sidewall etch protection from previous processing steps to provide additional process flexibility, such as allowing a thinner strap Cut Mask nitride and greater nitride etching during node nitride removal and buried strap nitrided interface removal. Advantageously, the presence of the nitride liner beneath the TTO reduces possibility of TTO dielectric breakdown between the gate and capacitor node electrode of the vertical MOSFET DRAM cell, while assuring strap diffusion to gate conductor overlap.
摘要翻译：在垂直MOSFET DRAM单元器件形成期间，能够在沟槽顶氧化物TTO（高密度等离子体）HDP沉积之前沉积薄氮化物衬垫的结构和方法。随后在TTO侧壁蚀刻之后移除该衬垫。该衬垫的一个功能是在TTO氧化物侧壁蚀刻期间保护套环氧化物不被蚀刻，并且通常提供在当前处理方案中未实现的横向蚀刻保护。工艺顺序不依赖于以前沉积的膜用于套环保护，并且将TTO侧壁蚀刻保护与先前的处理步骤解耦以提供附加的工艺灵活性，例如在节点氮化物去除期间允许更薄的带切割掩模氮化物和更大的氮化物蚀刻和掩埋带氮化界面去除。有利地，在TTO之下的氮化物衬垫的存在降低了垂直MOSFET DRAM单元的栅极和电容器节点电极之间的TTO介质击穿的可能性，同时确保带扩散到栅极导体重叠。

3. 发明授权

US06404000B1 Pedestal collar structure for higher charge retention time in trench-type DRAM cells 失效
标题翻译：基座领结构，在沟槽式DRAM单元中具有更高的电荷保留时间
公开(公告)号：US06404000B1
公开(公告)日：2002-06-11
申请号：US09599261
申请日：2000-06-22
申请人： Rama Divakaruni , Rajarao Jammy , Byeong Y. Kim , Jack A. Mandelman , Akira Sudo , Dirk Tobben
发明人： Rama Divakaruni , Rajarao Jammy , Byeong Y. Kim , Jack A. Mandelman , Akira Sudo , Dirk Tobben
IPC分类号： H01L2972
CPC分类号： H01L27/10861 , H01L27/10867 , H01L29/945
摘要： A memory structure having a trenched formed in a substrate. A collar oxide is located in an upper portion of the trench and includes a pedestal portion. A method of forming a memory device having a collar oxide with pedestal collar is also disclosed.
摘要翻译：一种在衬底中形成有沟槽的存储器结构。环状氧化物位于沟槽的上部，并且包括基座部分。还公开了一种形成具有带衬垫环的环形氧化物的存储器件的方法。

4. 发明授权

US06288422B1 Structure and process for fabricating a 6F2 DRAM cell having vertical MOSFET and large trench capacitance 失效
标题翻译：用于制造具有垂直MOSFET和大沟槽电容的6F2 DRAM单元的结构和工艺
公开(公告)号：US06288422B1
公开(公告)日：2001-09-11
申请号：US09540276
申请日：2000-03-31
申请人： Jack A. Mandelman , Rama Divakaruni , Carl Radens
发明人： Jack A. Mandelman , Rama Divakaruni , Carl Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10876 , H01L27/10891 , H01L29/945
摘要： A 6F2 memory cell structure comprising a plurality of capacitors each located in a separate trench in a substrate; a pluralaity of transfer transistors each having a vertical gate dielectric, a gate conductor, and a bitline diffusion, each transistor being located above and electrically connected to a respective trench capacitor; a plurality of troughs in a striped pattern about said transistor, said troughs being spaced apart by a substantially uniform spacing, said plurality of striped troughs comprising a first group of troughs consisting of every other one of said troughs being filled with a dielectric material, and a second group of troughs being the remaining troughs of said plurality, said second group of troughs containing dielectric material, damascened wordlines and damascene wordline contacts; a respective wordline electrical contact connected to each respective gate conductor; and a bitline contacted to each bitline diffusion, wherein said bitline diffusions have a width defined by said spacing of said striped troughs and each wordline electrical contact is self-aligned to an edge of a trough of said second group of troughs.
摘要翻译： 6F2存储器单元结构，包括多个电容器，每个电容器位于衬底中的单独的沟槽中; 每个具有垂直栅极电介质，栅极导体和位线扩散的转移晶体管的多个，每个晶体管位于相应的沟槽电容器的上方并电连接到相应的沟槽电容器; 围绕所述晶体管的条纹图案的多个槽，所述槽以基本上均匀的间隔间隔开，所述多个条纹槽包括由每一个所述槽中的每一个填充有电介质材料构成的第一组槽，以及第二组槽是所述多个的剩余槽，所述第二组槽包含电介质材料，大阴影字线和大马士革字线触点; 连接到每个相应的栅极导体的相应字线电触头; 并且与每个位线扩散接触的位线，其中所述位线扩散具有由所述条纹槽的所述间隔限定的宽度，并且每个字线电触点与所述第二组槽的槽的边缘自对准。

5. 发明授权

US06762447B1 Field-shield-trench isolation for gigabit DRAMs 有权
标题翻译：用于千兆位DRAM的场屏蔽沟槽隔离
公开(公告)号：US06762447B1
公开(公告)日：2004-07-13
申请号：US09245269
申请日：1999-02-05
申请人： Jack A. Mandelman , Rama Divakaruni , Giuseppe Larosa , Ulrike Gruening , Carl Radens
发明人： Jack A. Mandelman , Rama Divakaruni , Giuseppe Larosa , Ulrike Gruening , Carl Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L21/763 , H01L21/765 , H01L27/10829 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A dynamic random access memory (DRAM) formed in a semiconductor body has individual pairs of memory cells that are isolated from one another by a vertical electrical isolation trench and are isolated from support circuitry. The isolation trench has sidewalls and upper and lower portions, and encircles an area of the semiconductor body which contains the memory cells. This electrically isolates pairs of memory cells from each other and from the support circuitry contained within the semiconductor body but not located within the encircled area. The lower portion of the isolation trench is filled with an electrically conductive material that has sidewall portions thereof which are at least partly separated from the sidewalls of the lower portion of the trench by a first electrical insulator, and that has a lower portion that is in electrical contact with the semiconductor body. The upper portion of the isolation trench is filled with a second electrical insulator.
摘要翻译：形成在半导体主体中的动态随机存取存储器（DRAM）具有通过垂直电隔离沟槽彼此隔离并且与支持电路隔离的各对存储单元。隔离沟槽具有侧壁和上部和下部，并且包围包含存储单元的半导体主体的区域。这使得存储器单元对彼此和从包含在半导体本体内但不位于包围区域内的支撑电路电隔离。隔离沟槽的下部填充有导电材料，该导电材料具有其侧壁部分，其侧壁部分通过第一电绝缘体至少部分地与沟槽的下部的侧壁分离，并且其具有位于与半导体本体电接触。隔离沟槽的上部填充有第二电绝缘体。

6. 发明授权

US06501131B1 Transistors having independently adjustable parameters 有权
标题翻译：晶体管具有可独立调节的参数
公开(公告)号：US06501131B1
公开(公告)日：2002-12-31
申请号：US09359291
申请日：1999-07-22
申请人： Rama Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Rajesh Rengarajan
发明人： Rama Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Rajesh Rengarajan
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823807 , H01L29/66492 , H01L29/66537 , H01L29/66583
摘要： The process rules for manufacturing semiconductor devices such as MOSFET's are modified to provide dual work-function doping following the customary gate sidewall oxidation step, greatly reducing thermal budget and boron penetration concerns. The concern of thermal budget is further significantly reduced by a device structure which allows a reduced gap aspect ratio while maintaining low sheet resistance values. A reduced gap aspect ratio also relaxes the need for highly reflowable dielectric materials and also facilitates the use of angled source-drain (S-D) and halo implants. Also provided is a novel structure and process for producing a MOSFET channel, lateral doping profile which suppresses short channel effects while providing low S-D junction capacitance and leakage, as well as immunity to hot-carrier effects. This also affords the potential for reduction in the contact stud-to-gate conductor capacitance, because borderless contacts can be formed with an oxide gate sidewall spacer. As a result, the S-D junctions can be doped independently of the gate conductor doping, more easily allowing a variety of MOSFET structures.
摘要翻译：制造半导体器件如MOSFET的工艺规则被修改，以提供遵循常规栅极侧壁氧化步骤的双重功能掺杂，大大降低了热预算和硼渗透问题。通过允许减小的间隙宽高比同时保持低的薄层电阻值的装置结构，热预算的关注进一步显着降低。减小的间隙宽高比也放松了对高回流电介质材料的需要，并且还有助于使用倾斜的源漏（S-D）和晕轮植入物。还提供了用于产生MOSFET沟道，横向掺杂分布的新型结构和工艺，其抑制短沟道效应，同时提供低S-D结电容和泄漏，以及对热载流子效应的抗扰性。这也提供了减小接触柱对栅极导体电容的可能性，因为可以用氧化物栅极侧壁间隔物形成无边界接触。结果，S-D结可以独立于栅极导体掺杂掺杂，更容易地允许各种MOSFET结构。

7. 发明授权

US06441423B1 Trench capacitor with an intrinsically balanced field across the dielectric 失效
标题翻译：沟槽电容器，在电介质上具有本质平衡的场
公开(公告)号：US06441423B1
公开(公告)日：2002-08-27
申请号：US09584357
申请日：2000-05-31
申请人： Jack A. Mandelman , Rama Divakaruni
发明人： Jack A. Mandelman , Rama Divakaruni
IPC分类号： H01L27108
CPC分类号： H01L27/10861
摘要： The preferred embodiment of the present invention provides an improved capacitor design that overcomes many of the limitations of the prior art. The preferred embodiment of the present invention uses germanium to adjust the work function of the storage node. Specifically, the addition of germanium modifies the fermi level of the storage node, moving the fermi level towards the conduction band. This modification of the fermi level reduces the difference in conduction band-edge potentials between the storage node and the counter electrode, thus reducing the maximum electric potential seen across the capacitor. In the preferred embodiment, p-type doped silicon germanium is formed in the trench capacitor adjacent to the capacitor dielectric layer. A barrier layer is then formed over the doped silicon germanium, and the remaining storage node area is filled with n+-type polysilicon. The p-type doped silicon germanium adjusts the workfunction of the capacitor storage node, moving the fermi level toward the conduction band. This minimizes the maximum difference between conduction band-edge potentials of the storage node and the buried plate, which serves as the counter electrode. This has the effect of balancing the electric potential seen across the dielectric for stored high and stored low situations. This reduces the maximum electric potential seen across the capacitor dielectric. This solution improves the reliability of the capacitor, especially those capacitors with relatively thin dielectric layers, without requiring additional circuitry to bias the buried plate, and without increasing power consumption. The preferred embodiment also reduces leakage current through the capacitor dielectric, thus increasing signal retention time.
摘要翻译：本发明的优选实施例提供了一种改进的电容器设计，其克服了现有技术的许多限制。本发明的优选实施例使用锗来调节存储节点的功能。具体地说，锗的添加改变存储节点的费米能级，将费米能级移向导带。费米能级的这种修改降低了存储节点和对电极之间的导带边缘电位的差异，从而减少了跨越电容器的最大电位。在优选实施例中，在与电容器介电层相邻的沟槽电容器中形成p型掺杂硅锗。然后在掺杂的硅锗上形成阻挡层，并且剩余的存储节点区域填充有n +型多晶硅。 p型掺杂硅锗调节电容器存储节点的功函数，将费米电平移向导带。这使存储节点的导带边缘电位与用作对电极的掩埋板之间的最大差异最小化。这具有平衡在存储的高和存储的低情况下跨过电介质看到的电位的效果。这降低了在电容器电介质两端看到的最大电位。该解决方案提高了电容器的可靠性，特别是具有相对薄的介电层的电容器，而不需要额外的电路来偏置掩埋板，并且不增加功耗。优选实施例还减少了通过电容器电介质的泄漏电流，从而增加了信号保持时间。

8. 发明授权

US06373086B1 Notched collar isolation for suppression of vertical parasitic MOSFET and the method of preparing the same 失效
标题翻译：用于抑制垂直寄生MOSFET的缺口环隔离及其制备方法
公开(公告)号：US06373086B1
公开(公告)日：2002-04-16
申请号：US09607135
申请日：2000-06-29
申请人： Jack A. Mandelman , Rama Divakaruni , Byeong Y. Kim
发明人： Jack A. Mandelman , Rama Divakaruni , Byeong Y. Kim
IPC分类号： H01L27108
CPC分类号： H01L27/10867 , H01L27/1087 , H01L29/945
摘要： A deep trench capacitor having a modified sidewall geometry within the collar isolation region such that the threshold voltage of the vertical parasitic MOSFET between a buried-strap out-diffusion and a N+ capacitor plate is significantly increased as compared to a conventional arrangement. By forming a concave notch within the sidewalls of the capacitor, the electrical thickness of the gate dielectric is effectively thicker than its actual physical thickness. Thereby, a reduced amount of gate dielectric and dopant is needed for suppression of vertical parasitic MOSFET conduction.
摘要翻译：一种深沟槽电容器，其具有在套环隔离区域内的改进的侧壁几何形状，使得与常规布置相比，掩埋带外扩散与N +电容器板之间的垂直寄生MOSFET的阈值电压显着增加。通过在电容器的侧壁内形成凹陷痕，栅极电介质的电气厚度比其实际物理厚度有效厚。因此，需要减少量的栅极电介质和掺杂剂来抑制垂直寄生MOSFET导通。

9. 发明授权

US06348394B1 Method and device for array threshold voltage control by trapped charge in trench isolation 失效
标题翻译：用于沟槽隔离中捕获电荷的阵列阈值电压控制的方法和装置
公开(公告)号：US06348394B1
公开(公告)日：2002-02-19
申请号：US09573375
申请日：2000-05-18
申请人： Jack A. Mandelman , Rama Divakaruni , Herbert Ho , Giuseppe La Rosa , Yujun Li , Jochen Beintner , Radhika Srinivasan
发明人： Jack A. Mandelman , Rama Divakaruni , Herbert Ho , Giuseppe La Rosa , Yujun Li , Jochen Beintner , Radhika Srinivasan
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/76224
摘要： A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A nitride liner is formed in the trench. Charge is trapped in the nitride liner. In a preferred embodiment, the trench is filled with an oxide by an HDP process to increase the amount of charge trapped in the nitride liner. Preferably, the oxide fill is formed directly on the nitride liner.
摘要翻译：提供半导体器件及其制造方法。在半导体衬底中形成沟槽。优选在沟槽的表面上形成薄的氧化物衬垫。氮化物衬垫形成在沟槽中。电荷被困在氮化物衬垫中。在优选实施例中，沟槽通过HDP工艺填充氧化物以增加在氮化物衬垫中捕获的电荷量。优选地，氧化物填充物直接形成在氮化物衬垫上。

10. 发明授权

US06281539B1 Structure and process for 6F2 DT cell having vertical MOSFET and large storage capacitance 失效
标题翻译：具有垂直MOSFET和大容量电容的6F2 DT电池的结构和工艺
公开(公告)号：US06281539B1
公开(公告)日：2001-08-28
申请号：US09540854
申请日：2000-03-31
申请人： Jack A. Mandelman , Rama Divakaruni
发明人： Jack A. Mandelman , Rama Divakaruni
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891 , H01L29/945
摘要： A 6F2 memory cell comprising a plurality of capacitors each located in a separate trench that is formed in a semiconductor substrate; a plurality of transfer transistors each having a vertical gate dielectric, a gate conductor, and a bitline diffusion, each transistor is located above and electrically connected to a respective trench capacitor; a plurality of dielectric-filled isolation trenches in a striped pattern about said transistors, said isolation trenches are spaced apart by a substantially uniform spacing; a respective wordline electrically contacted to each respective gate conductor, said wordline is in the same direction as the isolation stripes; and a bitline in contact with said bitline diffusion, wherein said bitline diffusions have a width that is defined by said spacing of said isolation trenches.
摘要翻译：一种6F2存储单元，包括多个电容器，每个电容器均位于形成在半导体衬底中的单独的沟槽中; 每个具有垂直栅极电介质，栅极导体和位线扩散的多个转移晶体管，每个晶体管位于相应的沟槽电容器的上方并电连接到相应的沟槽电容器; 围绕所述晶体管的条纹图案的多个电介质填充的隔离沟槽，所述隔离沟槽间隔开大致均匀的间隔; 与每个相应的栅极导体电接触的相应字线，所述字线与隔离条相同; 以及与所述位线扩散接触的位线，其中所述位线扩散具有由所述隔离沟槽的所述间隔限定的宽度。

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