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1. 发明申请

US20140061914A1 DOPING OF COPPER WIRING STRUCTURES IN BACK END OF LINE PROCESSING 有权
公开(公告)号：US20140061914A1
公开(公告)日：2014-03-06
申请号：US13599256
申请日：2012-08-30
申请人： Thomas W. Dyer , Daniel C. Edelstein , Tze-man Ko , Andrew H. Simon , Wei-tsu Tseng
发明人： Thomas W. Dyer , Daniel C. Edelstein , Tze-man Ko , Andrew H. Simon , Wei-tsu Tseng
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76846 , H01L21/76849 , H01L21/76867 , H01L21/76873 , H01L21/76886 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.

2. 发明授权

US08765602B2 Doping of copper wiring structures in back end of line processing 有权
标题翻译：在线路处理后端掺杂铜线结构
公开(公告)号：US08765602B2
公开(公告)日：2014-07-01
申请号：US13599256
申请日：2012-08-30
申请人： Thomas W. Dyer , Daniel C. Edelstein , Tze-man Ko , Andrew H. Simon , Wei-tsu Tseng
发明人： Thomas W. Dyer , Daniel C. Edelstein , Tze-man Ko , Andrew H. Simon , Wei-tsu Tseng
IPC分类号： H01L23/52
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76846 , H01L21/76849 , H01L21/76867 , H01L21/76873 , H01L21/76886 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.
摘要翻译：形成金属互连结构的方法包括在层间电介质（ILD）层内形成铜线; 用铜合金材料直接掺杂铜线的顶面; 并在ILD层和铜合金材料上形成介电层; 其中所述铜合金材料用于所述铜线和所述电介质层之间的粘合界面层。

3. 发明授权

US07488679B2 Interconnect structure and process of making the same 有权
标题翻译：互连结构和制作过程相同
公开(公告)号：US07488679B2
公开(公告)日：2009-02-10
申请号：US11461137
申请日：2006-07-31
申请人： Theodorus Eduardus Standaert , Pegeen M. Davis , John Anthony Fitzsimmons , Stephen Edward Greco , Tze-Man Ko , Naftali Eliahu Lustig , Lee Matthew Nicholson , Sujatha Sankaran
发明人： Theodorus Eduardus Standaert , Pegeen M. Davis , John Anthony Fitzsimmons , Stephen Edward Greco , Tze-Man Ko , Naftali Eliahu Lustig , Lee Matthew Nicholson , Sujatha Sankaran
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L21/76808 , H01L21/76805 , H01L21/76814 , H01L21/76846 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings on top of at least one of the one or more via openings covered by the first liner; and forming a second liner covering the trenching openings and at least part of the first liner. An interconnect structure formed by the method is also provided.
摘要翻译：一种在层间电介质（ILD）材料中形成互连结构的方法，所述方法包括以下步骤：在ILD材料中形成一个或多个通路孔; 形成覆盖所述一个或多个通孔开口中的至少一个的第一衬垫; 在由所述第一衬垫覆盖的所述一个或多个通孔中的至少一个的顶部上形成一个或多个沟槽开口; 以及形成覆盖所述下料开口和所述第一衬里的至少一部分的第二衬里。还提供了通过该方法形成的互连结构。

4. 发明授权

US08623673B1 Structure and method for detecting defects in BEOL processing 失效
标题翻译：用于检测BEOL处理缺陷的结构和方法
公开(公告)号：US08623673B1
公开(公告)日：2014-01-07
申请号：US13572720
申请日：2012-08-13
申请人： Thomas W. Dyer , Tze-Man Ko , Yiheng Xu , Shaoning Yao
发明人： Thomas W. Dyer , Tze-Man Ko , Yiheng Xu , Shaoning Yao
IPC分类号： H01L21/66 , H01L21/306
CPC分类号： H01L22/34 , H01L22/30
摘要： A test structure and method for monitoring process uniformity. Embodiments of the invention include test structures having a first metallization layer, a second metallization layer formed above the first metallization layer, a defect-generating region in a first metallization layer, a defect-dispersing region in the second metallization layer above the defect-generating region; and a defect-detecting region in the second metallization layer adjacent to the defect-dispersing region. The defect-generating region of the exemplary embodiment may have zero pattern density, uniform non-zero pattern density, or non-uniform non-zero pattern density. The defect-detecting region may include a test pattern such as, a comb-serpentine structure. Embodiments may include more than one defect-generating region, more than one defect-dispersing region, or more than one defect-detecting region. Embodiments may further include methods of manufacturing said test structures and methods of utilizing said test structures to monitor back end processes and determine if such processes are within specification limits.
摘要翻译：一种用于监测过程均匀性的测试结构和方法。本发明的实施例包括具有第一金属化层的第一金属化层，在第一金属化层上形成的第二金属化层，第一金属化层中的缺陷产生区，在产生缺陷的第二金属化层中的缺陷分散区的测试结构地区; 以及与所述缺陷分散区域相邻的所述第二金属化层中的缺陷检测区域。示例性实施例的缺陷产生区域可以具有零图案密度，均匀的非零图案密度或非均匀非零图案密度。缺陷检测区域可以包括诸如梳状蛇形结构的测试图案。实施例可以包括多于一个缺陷产生区域，多于一个缺陷分散区域或多于一个缺陷检测区域。实施例还可以包括制造所述测试结构的方法以及利用所述测试结构来监测后端处理并确定这些过程是否在规定范围内的方法。

5. 发明申请

US20080026568A1 INTERCONNECT STRUCTURE AND PROCESS OF MAKING THE SAME 有权
标题翻译：互连结构及其制作方法
公开(公告)号：US20080026568A1
公开(公告)日：2008-01-31
申请号：US11461137
申请日：2006-07-31
申请人： Theodorus Eduardus Standaert , Pegeen M. Davis , John Anthony Fitzsimmons , Stephen Edward Greco , Tze-Man Ko , Naftali Eliahu Lustig , Lee Matthew Nicholson , Sujatha Sankaran
发明人： Theodorus Eduardus Standaert , Pegeen M. Davis , John Anthony Fitzsimmons , Stephen Edward Greco , Tze-Man Ko , Naftali Eliahu Lustig , Lee Matthew Nicholson , Sujatha Sankaran
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76805 , H01L21/76814 , H01L21/76846 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings on top of at least one of the one or more via openings covered by the first liner; and forming a second liner covering the trenching openings and at least part of the first liner. An interconnect structure formed by the method is also provided.
摘要翻译：一种在层间电介质（ILD）材料中形成互连结构的方法，所述方法包括以下步骤：在ILD材料中形成一个或多个通路孔; 形成覆盖所述一个或多个通孔开口中的至少一个的第一衬垫; 在由所述第一衬垫覆盖的所述一个或多个通孔中的至少一个的顶部上形成一个或多个沟槽开口; 以及形成覆盖所述下料开口和所述第一衬里的至少一部分的第二衬里。还提供了通过该方法形成的互连结构。

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