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1. 发明申请

US20080171420A1 STRUCTURE AND METHOD TO FORM IMPROVED ISOLATION IN A SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件中形成改进隔离的结构和方法
公开(公告)号：US20080171420A1
公开(公告)日：2008-07-17
申请号：US11622057
申请日：2007-01-11
申请人： Haining S. Yang , Thomas W. Dyer , William C. Wille
发明人： Haining S. Yang , Thomas W. Dyer , William C. Wille
IPC分类号： H01L21/76
CPC分类号： H01L21/823878 , H01L21/76227 , H01L21/76237
摘要： A method is disclosed for forming an STI (shallow trench isolation) in a substrate during CMOS (complementary metal-oxide semiconductor) semiconductor fabrication which includes providing at least two wells including dopants. A pad layer may be formed on a top surface of the substrate and a partial STI trench is etched in the upper portion of the substrate followed by etching to form a full STI trench. Boron is implanted in a lower area of the full STI trench forming an implant area which is anodized to form a porous silicon region, which is then oxidized to form a oxidized region. A dielectric layer is formed over the silicon nitride layer filling the full STI trench to provide, after etching, at least two electrical component areas on the top surface of the substrate having the full STI trench therebetween.
摘要翻译：公开了一种用于在CMOS（互补金属氧化物半导体）半导体制造期间在衬底中形成STI（浅沟槽隔离）的方法，其包括提供至少两个包括掺杂剂的阱。衬底层可以形成在衬底的顶表面上，并且在衬底的上部蚀刻部分STI沟槽，然后蚀刻以形成完整的STI沟槽。硼被植入整个STI沟槽的下部区域，形成一个阳极氧化以形成多孔硅区域的植入区域，然后被氧化形成氧化区域。在填充整个STI沟槽的氮化硅层上形成介电层，在蚀刻之后，在衬底的顶表面上提供至少两个具有全部STI沟槽的电气部件区域。

2. 发明授权

US07635899B2 Structure and method to form improved isolation in a semiconductor device 有权
标题翻译：在半导体器件中形成改进隔离的结构和方法
公开(公告)号：US07635899B2
公开(公告)日：2009-12-22
申请号：US11622057
申请日：2007-01-11
申请人： Haining S. Yang , Thomas W. Dyer , William C. Wille
发明人： Haining S. Yang , Thomas W. Dyer , William C. Wille
IPC分类号： H01L27/092
CPC分类号： H01L21/823878 , H01L21/76227 , H01L21/76237
摘要： A method is disclosed for forming an STI (shallow trench isolation) in a substrate during CMOS (complementary metal-oxide semiconductor) semiconductor fabrication which includes providing at least two wells including dopants. A pad layer may be formed on a top surface of the substrate and a partial STI trench is etched in the upper portion of the substrate followed by etching to form a full STI trench. Boron is implanted in a lower area of the full STI trench forming an implant area which is anodized to form a porous silicon region, which is then oxidized to form a oxidized region. A dielectric layer is formed over the silicon nitride layer filling the full STI trench to provide, after etching, at least two electrical component areas on the top surface of the substrate having the full STI trench therebetween.
摘要翻译：公开了一种用于在CMOS（互补金属氧化物半导体）半导体制造期间在衬底中形成STI（浅沟槽隔离）的方法，其包括提供至少两个包括掺杂剂的阱。衬底层可以形成在衬底的顶表面上，并且在衬底的上部蚀刻部分STI沟槽，然后蚀刻以形成完整的STI沟槽。硼被植入整个STI沟槽的下部区域，形成一个阳极氧化以形成多孔硅区域的植入区域，然后被氧化形成氧化区域。在填充整个STI沟槽的氮化硅层上形成介电层，在蚀刻之后，在衬底的顶表面上提供至少两个具有全部STI沟槽的电气部件区域。

3. 发明授权

US06621392B1 Micro electromechanical switch having self-aligned spacers 有权
公开(公告)号：US06621392B1
公开(公告)日：2003-09-16
申请号：US10132743
申请日：2002-04-25
申请人： Richard P. Volant , David Angell , Donald F. Canaperi , Joseph T. Kocis , Kevin S. Petrarca , Kenneth J. Stein , William C. Wille
发明人： Richard P. Volant , David Angell , Donald F. Canaperi , Joseph T. Kocis , Kevin S. Petrarca , Kenneth J. Stein , William C. Wille
IPC分类号： H01H5122
CPC分类号： B81B3/001 , B81B2201/014 , H01H59/0009 , H01H2059/0072
摘要： A method of fabricating and the structure of a micro-electromechanical switch (MEMS) device provided with self-aligned spacers or bumps is described. The spacers are designed to have an optimum size and to be positioned such that they act as a detent mechanism for the switch to minimize problems caused by stiction. The spacers are fabricated using standard semiconductor techniques typically used for the manufacture of CMOS devices. The present method of fabricating these spacers requires no added depositions, no extra lithography steps, and no additional etching.

4. 发明授权

US06461529B1 Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme 失效
标题翻译：各向异性氮化物蚀刻工艺，在镶嵌蚀刻方案中对氧化物和光致抗蚀剂层具有高选择性
公开(公告)号：US06461529B1
公开(公告)日：2002-10-08
申请号：US09299137
申请日：1999-04-26
申请人： Diane C. Boyd , Stuart M. Burns , Hussein I. Hanafi , Waldemar W. Kocon , William C. Wille , Richard Wise
发明人： Diane C. Boyd , Stuart M. Burns , Hussein I. Hanafi , Waldemar W. Kocon , William C. Wille , Richard Wise
IPC分类号： H01L213215
CPC分类号： H01L29/66583 , H01L21/31116 , H01L21/76224 , H01L21/823481
摘要： A process and etchant gas composition for anisotropically etching a trench in a silicon nitride layer of a multilayer structure. The etchant gas composition has an etchant gas including a polymerizing agent, a hydrogen source, an oxidant, and a noble gas diluent. The oxidant preferably includes a carbon-containing oxidant component and an oxidant-noble gas component. The fluorocarbon gas is selected from CF4, C2F6, and C3F8; the hydrogen source is selected from CHF3, CH2F2, CH3F, and H2; the oxidant is selected from CO, CO2, and O2; and the noble gas diluent is selected from He, Ar, and Ne. The constituents are added in amounts to achieve an etchant gas having a high nitride selectivity to silicon oxide and photoresist. A power source, such as an RF power source, is applied to the structure to control the directionality of the high density plasma formed by exciting the etchant gas. The power source that controls the directionality of the plasma is decoupled from the power source used to excite the etchant gas. The etchant gas can be used during a nitride etch step in a process for making a metal oxide semiconductor field effect transistor.
摘要翻译：一种用于各向异性蚀刻多层结构的氮化硅层中的沟槽的工艺和蚀刻剂气体组合物。蚀刻剂气体组合物具有包括聚合剂，氢源，氧化剂和惰性气体稀释剂的蚀刻剂气体。氧化剂优选包括含碳氧化剂组分和氧化剂 - 惰性气体组分。碳氟化合物气体选自CF4，C2F6和C3F8; 氢源选自CHF 3，CH 2 F 2，CH 3 F和H 2; 氧化剂选自CO，CO 2和O 2; 惰性气体稀释剂选自He，Ar和Ne。添加成分以达到对氧化硅和光致抗蚀剂具有高氮化物选择性的蚀刻剂气体。将诸如RF电源的电源施加到结构以控制通过激发蚀刻剂气体形成的高密度等离子体的方向性。控制等离子体方向性的电源与用于激发蚀刻剂气体的电源脱耦。在制造金属氧化物半导体场效应晶体管的工艺中的氮化物蚀刻步骤期间可以使用蚀刻剂气体。

5. 发明授权

US07030031B2 Method for forming damascene structure utilizing planarizing material coupled with diffusion barrier material 有权
标题翻译：使用与扩散阻挡材料耦合的平面化材料形成镶嵌结构的方法
公开(公告)号：US07030031B2
公开(公告)日：2006-04-18
申请号：US10604056
申请日：2003-06-24
申请人： William C. Wille , Daniel C. Edelstein , William J. Cote , Peter E. Biolsi , John Fritche , Allan W. Upham
发明人： William C. Wille , Daniel C. Edelstein , William J. Cote , Peter E. Biolsi , John Fritche , Allan W. Upham
IPC分类号： H01L21/302
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/76804
摘要： This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a diffusion barrier material. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized. With this method, the problem of photoresist poisoning by the interlevel dielectric material is alleviated.
摘要翻译：本发明涉及集成电路器件中的双镶嵌互连结构的制造。具体地，公开了一种利用平面化材料和扩散阻挡材料在低k电介质薄膜中形成单一或双镶嵌结构的方法。在该方法的优选双镶嵌实施例中，首先在电介质材料中形成通孔，然后将平坦化材料沉积在通孔和介电材料上，并且阻挡材料沉积在平坦化材料上。然后在成像材料中光刻地形成沟槽，通过阻挡材料蚀刻成平坦化材料，并将沟槽图案转移到电介质材料。在这些蚀刻步骤期间和之后，去除成像，阻挡层和平坦化材料。然后可以将所得的双镶嵌结构金属化。通过这种方法，可以减轻层间电介质材料的光致抗蚀剂中毒问题。

6. 发明授权

US06762667B2 Micro electromechanical switch having self-aligned spacers 失效
标题翻译：具有自对准间隔物的微机电开关
公开(公告)号：US06762667B2
公开(公告)日：2004-07-13
申请号：US10465451
申请日：2003-06-19
申请人： Richard P. Volant , David Angell , Donald F. Canaperi , Joseph T. Kocis , Kevin S. Petrarca , Kenneth J. Stein , William C. Wille
发明人： Richard P. Volant , David Angell , Donald F. Canaperi , Joseph T. Kocis , Kevin S. Petrarca , Kenneth J. Stein , William C. Wille
IPC分类号： H01H3752
CPC分类号： B81B3/001 , B81B2201/014 , H01H59/0009 , H01H2059/0072
摘要： A method of fabricating and the structure of a micro-electromechanical switch (MEMS) device provided with self-aligned spacers or bumps is described. The spacers are designed to have an optimum size and to be positioned such that they act as a detent mechanism for the switch to minimize problems caused by stiction. The spacers are fabricated using standard semiconductor techniques typically used for the manufacture of CMOS devices. The present method of fabricating these spacers requires no added depositions, no extra lithography steps, and no additional etching.
摘要翻译：描述了一种制造和具有自对准间隔物或凸块的微机电开关（MEMS）装置的结构的方法。间隔件被设计成具有最佳尺寸并且被定位成使得它们用作开关的制动机构以最小化由静摩擦引起的问题。使用通常用于制造CMOS器件的标准半导体技术制造间隔物。制造这些间隔物的本方法不需要附加的沉积，不需要额外的光刻步骤，也不需要额外的蚀刻。

7. 发明申请

US20090098706A1 Methods of Forming Integrated Circuit Devices Having Ion-Cured Electrically Insulating Layers Therein 有权
标题翻译：形成具有离子固化电绝缘层的集成电路器件的方法
公开(公告)号：US20090098706A1
公开(公告)日：2009-04-16
申请号：US11871602
申请日：2007-10-12
申请人： Jun-jung Kim , Joo-chan Kim , Jae-eon Park , Richard Anthony Conti , Zhao Lun , Johnny Widodo , William C. Wille , Biao Zuo
发明人： Jun-jung Kim , Joo-chan Kim , Jae-eon Park , Richard Anthony Conti , Zhao Lun , Johnny Widodo , William C. Wille , Biao Zuo
IPC分类号： H01L21/762
CPC分类号： H01L21/3105 , H01L21/76229 , H01L21/76232
摘要： Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.
摘要翻译：形成集成电路器件的方法包括在半导体衬底的表面中形成沟槽，并用其中具有接缝的电绝缘区填充沟槽。可以通过在沟槽的侧壁和底部上沉积足够厚的电绝缘层来填充沟槽。然后将固化离子以足够的能量和剂量注入电绝缘区域以减少其中原子序列的程度。固化离子可以是选自氮（N），磷（P），硼（B），砷（As），碳（C），氩（Ar），锗（Ge），氦），氖（Ne）和氙（Xe）。这些固化离子可以以至少约80KeV的能量和至少约5×1014个离子/ cm 2的剂量注入。然后将电绝缘区域在足够的温度下退火并持续足够的时间以增加电绝缘区域内的原子级数。

8. 发明申请

US20090047791A1 SEMICONDUCTOR ETCHING METHODS 审中-公开
标题翻译：半导体蚀刻方法
公开(公告)号：US20090047791A1
公开(公告)日：2009-02-19
申请号：US11839681
申请日：2007-08-16
申请人： David M. Dobuzinsky , Johnathan E. Faltermeier , Munir D. Naeem , William C. Wille , Richard S. Wise
发明人： David M. Dobuzinsky , Johnathan E. Faltermeier , Munir D. Naeem , William C. Wille , Richard S. Wise
IPC分类号： H01L21/302
CPC分类号： H01L21/3081 , H01L27/10844 , H01L27/11
摘要： A method of etching semiconductor structures is disclosed. The method may include etching an SRAM portion of a semiconductor device, the method comprising: providing a silicon substrate layer, a nitride layer thereover, an optical dispersive layer over the nitride layer, and a silicon anti-reflective coating layer thereover; etching the silicon anti-reflective coating layer using an image layer; removing the image layer; etching the optical dispersive layer while removing the silicon anti-reflective coating layer; etching the optical dispersive layer and the nitride layer simultaneously; and etching the optical dispersive layer, the nitride layer, and the silicon substrate simultaneously.
摘要翻译：公开了蚀刻半导体结构的方法。该方法可以包括蚀刻半导体器件的SRAM部分，该方法包括：提供硅衬底层，其上的氮化物层，氮化物层上的光学色散层和其上的硅抗反射涂层; 使用图像层蚀刻硅抗反射涂层; 去除图像层; 在去除硅抗反射涂层的同时蚀刻光学色散层; 同时蚀刻光学色散层和氮化物层; 并同时蚀刻光学色散层，氮化物层和硅衬底。

9. 发明授权

US5976982A Methods for protecting device components from chemical mechanical polish induced defects 失效
标题翻译：保护器件部件免受化学机械抛光引起的缺陷的方法
公开(公告)号：US5976982A
公开(公告)日：1999-11-02
申请号：US884120
申请日：1997-06-27
申请人： Max G. Levy , Wolfgang Bergner , Bernhard Fiegl , George R. Goth , Paul Parries , Matthew J. Sendelbach , Tinghao T. Wang , William C. Wille , Juergen Wittmann
发明人： Max G. Levy , Wolfgang Bergner , Bernhard Fiegl , George R. Goth , Paul Parries , Matthew J. Sendelbach , Tinghao T. Wang , William C. Wille , Juergen Wittmann
IPC分类号： H01L21/302 , H01L21/304 , H01L21/306 , H01L21/3105 , H01L21/76
CPC分类号： H01L21/31053
摘要： A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.
摘要翻译：一种用于防止对设置在台面的衬垫氮化物层下方的衬底的CMP诱导（化学机械抛光）损伤的方法。衬垫氮化物层设置在共形沉积的电介质层的下方。电介质层设置在共形沉积的多晶硅层下方。该方法包括使用CMP平坦化多晶硅层至至少介电层的表面以暴露电介质层的第一区域。该方法还包括使用第一蚀刻参数部分地蚀刻介质层的第一区域。第一蚀刻参数包括蚀刻剂源气体，其对衬垫氮化物层基本上是选择性的，以防止衬垫氮化物层即使在存在CMP缺陷的情况下被蚀刻。此外，还包括在蚀刻之后部分地通过电介质层的第一区域去除多晶硅层。

10. 发明授权

US5811357A Process of etching an oxide layer 失效
标题翻译：蚀刻氧化层的工艺
公开(公告)号：US5811357A
公开(公告)日：1998-09-22
申请号：US824744
申请日：1997-03-26
申请人： Michael D. Armacost , Tina J. Wagner , Michael L. Passow , Dominic J. Schepis , Matthew J. Sendelbach , William C. Wille
发明人： Michael D. Armacost , Tina J. Wagner , Michael L. Passow , Dominic J. Schepis , Matthew J. Sendelbach , William C. Wille
IPC分类号： H01L21/311 , H01L21/302
CPC分类号： H01L21/02063 , H01L21/31116
摘要： A dry etching process for etching an oxide layer on a substrate in which a plasma is created in a gaseous mixture containing C.sub.4 F.sub.8 and C.sub.2 F.sub.6. The dry etch process is useful for etching an oxide layer stopping on a silicon nitride layer on a semiconductor wafer of an integrated circuit structure as it eliminates resist blistering without sacrificing high selectivity to nitride, via wall angle, and/or etch uniformity.
摘要翻译：用于蚀刻在其中在含有C 4 F 8和C 2 F 6的气体混合物中产生等离子体的衬底上的氧化物层的干蚀刻工艺。干蚀刻工艺对于蚀刻在集成电路结构的半导体晶片上的氮化硅层上停止的氧化物层是有用的，因为它消除了抗蚀剂起泡，而不牺牲对氮化物，经由壁角度和/或蚀刻均匀性的高选择性。

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