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1. 发明申请

US20080171420A1 STRUCTURE AND METHOD TO FORM IMPROVED ISOLATION IN A SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件中形成改进隔离的结构和方法
公开(公告)号：US20080171420A1
公开(公告)日：2008-07-17
申请号：US11622057
申请日：2007-01-11
申请人： Haining S. Yang , Thomas W. Dyer , William C. Wille
发明人： Haining S. Yang , Thomas W. Dyer , William C. Wille
IPC分类号： H01L21/76
CPC分类号： H01L21/823878 , H01L21/76227 , H01L21/76237
摘要： A method is disclosed for forming an STI (shallow trench isolation) in a substrate during CMOS (complementary metal-oxide semiconductor) semiconductor fabrication which includes providing at least two wells including dopants. A pad layer may be formed on a top surface of the substrate and a partial STI trench is etched in the upper portion of the substrate followed by etching to form a full STI trench. Boron is implanted in a lower area of the full STI trench forming an implant area which is anodized to form a porous silicon region, which is then oxidized to form a oxidized region. A dielectric layer is formed over the silicon nitride layer filling the full STI trench to provide, after etching, at least two electrical component areas on the top surface of the substrate having the full STI trench therebetween.
摘要翻译：公开了一种用于在CMOS（互补金属氧化物半导体）半导体制造期间在衬底中形成STI（浅沟槽隔离）的方法，其包括提供至少两个包括掺杂剂的阱。衬底层可以形成在衬底的顶表面上，并且在衬底的上部蚀刻部分STI沟槽，然后蚀刻以形成完整的STI沟槽。硼被植入整个STI沟槽的下部区域，形成一个阳极氧化以形成多孔硅区域的植入区域，然后被氧化形成氧化区域。在填充整个STI沟槽的氮化硅层上形成介电层，在蚀刻之后，在衬底的顶表面上提供至少两个具有全部STI沟槽的电气部件区域。

2. 发明授权

US07635899B2 Structure and method to form improved isolation in a semiconductor device 有权
标题翻译：在半导体器件中形成改进隔离的结构和方法
公开(公告)号：US07635899B2
公开(公告)日：2009-12-22
申请号：US11622057
申请日：2007-01-11
申请人： Haining S. Yang , Thomas W. Dyer , William C. Wille
发明人： Haining S. Yang , Thomas W. Dyer , William C. Wille
IPC分类号： H01L27/092
CPC分类号： H01L21/823878 , H01L21/76227 , H01L21/76237
摘要： A method is disclosed for forming an STI (shallow trench isolation) in a substrate during CMOS (complementary metal-oxide semiconductor) semiconductor fabrication which includes providing at least two wells including dopants. A pad layer may be formed on a top surface of the substrate and a partial STI trench is etched in the upper portion of the substrate followed by etching to form a full STI trench. Boron is implanted in a lower area of the full STI trench forming an implant area which is anodized to form a porous silicon region, which is then oxidized to form a oxidized region. A dielectric layer is formed over the silicon nitride layer filling the full STI trench to provide, after etching, at least two electrical component areas on the top surface of the substrate having the full STI trench therebetween.
摘要翻译：公开了一种用于在CMOS（互补金属氧化物半导体）半导体制造期间在衬底中形成STI（浅沟槽隔离）的方法，其包括提供至少两个包括掺杂剂的阱。衬底层可以形成在衬底的顶表面上，并且在衬底的上部蚀刻部分STI沟槽，然后蚀刻以形成完整的STI沟槽。硼被植入整个STI沟槽的下部区域，形成一个阳极氧化以形成多孔硅区域的植入区域，然后被氧化形成氧化区域。在填充整个STI沟槽的氮化硅层上形成介电层，在蚀刻之后，在衬底的顶表面上提供至少两个具有全部STI沟槽的电气部件区域。

3. 发明授权

US08159031B2 SOI substrates and SOI devices, and methods for forming the same 有权
标题翻译： SOI衬底和SOI器件及其形成方法
公开(公告)号：US08159031B2
公开(公告)日：2012-04-17
申请号：US12709873
申请日：2010-02-22
申请人： Thomas W. Dyer , Zhijiong Luo , Haining S. Yang
发明人： Thomas W. Dyer , Zhijiong Luo , Haining S. Yang
IPC分类号： H01L27/12
CPC分类号： H01L29/0653 , H01L21/76243 , H01L21/76267 , H01L21/76283 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried insulator layer at a first depth (i.e., measured from the planar upper surface of the SOI substrate), and (3) third regions that contain second portions of the patterned buried insulator layer at a second depth, where the first depth is larger than the second depth. One or more field effect transistors (FETs) can be formed in the SOI substrate. For example, the FETs may comprise: channel regions in the first regions of the SOI substrate, source and drain regions in the second regions of the SOI substrate, and source/drain extension regions in the third regions of the SOI substrate.
摘要翻译：提供了一种改进的绝缘体上半导体（SOI）衬底，其包含在不同深度处的图案化掩埋绝缘体层。具体而言，SOI衬底具有基本平坦的上表面，并且包括：（1）不包含任何埋入绝缘体的第一区域，（2）第一区域，其包含第一深度处的图案化掩埋绝缘体层的第一部分从SOI衬底的平坦的上表面），和（3）第二深度大于第二深度的第二深度上包含图案化的掩埋绝缘体层的第二部分的第三区域。可以在SOI衬底中形成一个或多个场效应晶体管（FET）。例如，FET可以包括：SOI衬底的第一区域中的沟道区域，SOI衬底的第二区域中的源极和漏极区域以及SOI衬底的第三区域中的源极/漏极延伸区域。

4. 发明授权

US07884448B2 High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching 有权
标题翻译：高性能3D FET结构，以及使用优先晶体蚀刻形成相同方法
公开(公告)号：US07884448B2
公开(公告)日：2011-02-08
申请号：US12500396
申请日：2009-07-09
申请人： Thomas W. Dyer , Haining S. Yang
发明人： Thomas W. Dyer , Haining S. Yang
IPC分类号： H01L29/04
CPC分类号： H01L21/823807 , H01L21/823821 , H01L27/0922 , H01L27/1211 , H01L29/04 , H01L29/66795 , H01L29/7853
摘要： The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.
摘要翻译：本发明涉及高性能三维（3D）场效应晶体管（FET）。具体而言，可以使用具有沿着第一组等效晶面中的一个取向的底表面和沿着第二不同组的等效晶面取向的多个附加表面的3D半导体结构，以形成具有载体通道定向的高性能3D FET 沿着第二个不同组的等效晶面。更重要的是，这种3D半导体结构可以容易地在具有底表面和多个附加表面的附加3D半导体结构的同一衬底上形成，所述另外的三维半导体结构全部沿着第一组等效晶面取向。附加的3D半导体结构可以用于形成附加的3D FET，其与上述3D FET互补，并且具有沿着第一组等效晶面取向的载流子通道。

5. 发明申请

US20090283829A1 FINFET WITH A V-SHAPED CHANNEL 审中-公开
标题翻译： FINFET与V形通道
公开(公告)号：US20090283829A1
公开(公告)日：2009-11-19
申请号：US12119515
申请日：2008-05-13
申请人： Thomas W. Dyer , Haining S. Yang
发明人： Thomas W. Dyer , Haining S. Yang
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L29/785 , H01L29/045 , H01L29/66818
摘要： A fin-type field effect transistor (finFET) structure comprises a substrate having a planar upper surface, an elongated fin on the planar upper surface of the substrate (wherein the length and the height of the fin are greater that the width of the fin) and an elongated gate conductor on the planar upper surface of the substrate. The length and the height of the gate conductor are greater than the width of the gate conductor. The fin comprises a center section comprising a semiconducting channel region and end sections distal to the channel region. The end sections of the fin comprise conductive source and drain regions. The gate conductor covers the channel region of the fin. The sidewalls of the channel region comprise a different crystal orientation than the sidewalls of the source and drain regions.
摘要翻译：鳍式场效应晶体管（finFET）结构包括具有平坦上表面的基板，在基板的平面上表面上的细长翅片（其中鳍的长度和高度大于翅片的宽度）以及在基板的平面上表面上的细长栅极导体。栅极导体的长度和高度大于栅极导体的宽度。翅片包括中心部分，其包括半导体沟道区域和远离沟道区域的端部区段。翅片的端部部分包括导电源极和漏极区域。栅极导体覆盖鳍片的沟道区域。沟道区的侧壁包括与源区和漏区的侧壁不同的晶体取向。

6. 发明申请

US20090256173A1 COMPLEMENTARY FIELD EFFECT TRANSISTORS HAVING EMBEDDED SILICON SOURCE AND DRAIN REGIONS 有权
标题翻译：具有嵌入式硅源和漏区的补充场效应晶体管
公开(公告)号：US20090256173A1
公开(公告)日：2009-10-15
申请号：US12103301
申请日：2008-04-15
申请人： Xiangdong Chen , Thomas W. Dyer , Haining S. Yang
发明人： Xiangdong Chen , Thomas W. Dyer , Haining S. Yang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/8258 , H01L29/1054 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than silicon can be epitaxially grown on an underlying semiconductor region of a substrate. The first semiconductor region can be grown laterally adjacent to a second semiconductor region which has a lattice constant smaller than that of silicon. Layers consisting essentially of silicon can be grown epitaxially onto exposed major surfaces of the first and second semiconductor regions after which gates can be formed which overlie the epitaxially grown silicon layers. Portions of the first and second semiconductor regions adjacent to the gates can be removed to form recesses. Regions consisting essentially of silicon can be grown within the recesses to form embedded silicon regions. Source and drain regions then can be formed in the embedded silicon regions. The difference between the lattice constant of silicon and that of the underlying first and second regions results in tensile stressed silicon over the first semiconductor region and compressive stressed silicon over the second semiconductor region.
摘要翻译：提供了制造互补应力半导体器件的方法，例如具有拉伸应力通道的NFET和具有压应力通道的PFET。在这种方法中，可以在衬底的下面的半导体区域外延生长具有大于硅的晶格常数的第一半导体区域。第一半导体区域可以与具有比硅的晶格常数小的晶格常数的第二半导体区域横向生长。基本上由硅组成的层可以外延生长到第一和第二半导体区域的暴露的主表面上，之后可以形成覆盖外延生长的硅层的栅极。可以去除与栅极相邻的第一和第二半导体区域的部分以形成凹部。基本上由硅组成的区域可以在凹槽内生长以形成嵌入的硅区域。然后可以在嵌入的硅区域中形成源区和漏区。硅的晶格常数和下面的第一和第二区域的晶格常数之间的差异导致第一半导体区域上的拉伸应力硅和第二半导体区域上的压应力硅。

7. 发明申请

US20080001182A1 IMPROVED CMOS DEVICES WITH STRESSED CHANNEL REGIONS, AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：改进的具有应力通道区域的CMOS器件及其制造方法
公开(公告)号：US20080001182A1
公开(公告)日：2008-01-03
申请号：US11427495
申请日：2006-06-29
申请人： Xiangdong Chen , Thomas W. Dyer , Kenneth Settlemyer , Haining S. Yang
发明人： Xiangdong Chen , Thomas W. Dyer , Kenneth Settlemyer , Haining S. Yang
IPC分类号： H01L29/76 , H01L27/148
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/30604 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/045 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/78 , H01L29/78684 , H01L29/78696
摘要： The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.
摘要翻译：本发明涉及具有应力通道区域的改进的互补金属氧化物半导体（CMOS）器件。具体地，每个改进的CMOS器件包括具有位于半导体器件结构中的沟道区的场效应晶体管（FET），其具有沿着第一组等效晶面中的一个取向的顶表面和沿着第二，不同组的等效晶面。这种附加表面可以通过晶体蚀刻容易地形成。此外，具有固有压缩或拉伸应力的一个或多个应力层位于半导体器件结构的附加表面上，并且被布置和构造成将拉应力或压应力施加到FET的沟道区。这样的应力层可以通过具有与半导体器件结构不同的晶格常数的半导体材料的假晶生长来形成。

8. 发明授权

US08853746B2 CMOS devices with stressed channel regions, and methods for fabricating the same 有权
标题翻译：具有应力沟道区的CMOS器件及其制造方法
公开(公告)号：US08853746B2
公开(公告)日：2014-10-07
申请号：US11427495
申请日：2006-06-29
申请人： Xiangdong Chen , Thomas W. Dyer , Kenneth Settlemyer , Haining S. Yang
发明人： Xiangdong Chen , Thomas W. Dyer , Kenneth Settlemyer , Haining S. Yang
IPC分类号： H01L29/76 , H01L27/148 , H01L29/66 , H01L29/165 , H01L29/786 , H01L29/78 , H01L27/12 , H01L21/84 , H01L29/04 , H01L29/10 , H01L21/762 , H01L21/8238
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/30604 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/045 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/78 , H01L29/78684 , H01L29/78696
摘要： The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.
摘要翻译：本发明涉及具有应力通道区域的改进的互补金属氧化物半导体（CMOS）器件。具体地，每个改进的CMOS器件包括具有位于半导体器件结构中的沟道区的场效应晶体管（FET），其具有沿着第一组等效晶面中的一个取向的顶表面和沿着第二，不同组的等效晶面。这种附加表面可以通过晶体蚀刻容易地形成。此外，具有固有压缩或拉伸应力的一个或多个应力层位于半导体器件结构的附加表面上，并且被布置和构造成将拉应力或压应力施加到FET的沟道区。这种应力层可以通过具有与半导体器件结构不同的晶格常数的半导体材料的假晶生长来形成。

9. 发明授权

US07968910B2 Complementary field effect transistors having embedded silicon source and drain regions 有权
标题翻译：具有嵌入式硅源极和漏极区域的互补场效应晶体管
公开(公告)号：US07968910B2
公开(公告)日：2011-06-28
申请号：US12103301
申请日：2008-04-15
申请人： Xiangdong Chen , Thomas W. Dyer , Haining S. Yang
发明人： Xiangdong Chen , Thomas W. Dyer , Haining S. Yang
IPC分类号： H01L21/02 , H01L27/12
CPC分类号： H01L21/823807 , H01L21/8258 , H01L29/1054 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than silicon can be epitaxially grown on an underlying semiconductor region of a substrate. The first semiconductor region can be grown laterally adjacent to a second semiconductor region which has a lattice constant smaller than that of silicon. Layers consisting essentially of silicon can be grown epitaxially onto exposed major surfaces of the first and second semiconductor regions after which gates can be formed which overlie the epitaxially grown silicon layers. Portions of the first and second semiconductor regions adjacent to the gates can be removed to form recesses. Regions consisting essentially of silicon can be grown within the recesses to form embedded silicon regions. Source and drain regions then can be formed in the embedded silicon regions. The difference between the lattice constant of silicon and that of the underlying first and second regions results in tensile stressed silicon over the first semiconductor region and compressive stressed silicon over the second semiconductor region.
摘要翻译：提供了制造互补应力半导体器件的方法，例如具有拉伸应力通道的NFET和具有压应力通道的PFET。在这种方法中，可以在衬底的下面的半导体区域外延生长具有大于硅的晶格常数的第一半导体区域。第一半导体区域可以与具有比硅的晶格常数小的晶格常数的第二半导体区域横向生长。基本上由硅组成的层可以外延生长到第一和第二半导体区域的暴露的主表面上，之后可以形成覆盖外延生长的硅层的栅极。可以去除与栅极相邻的第一和第二半导体区域的部分以形成凹部。基本上由硅组成的区域可以在凹槽内生长以形成嵌入的硅区域。然后可以在嵌入的硅区域中形成源区和漏区。硅的晶格常数和下面的第一和第二区域的晶格常数之间的差异导致第一半导体区域上的拉伸应力硅和第二半导体区域上的压应力硅。

10. 发明授权

US07750429B2 Self-aligned and extended inter-well isolation structure 失效
标题翻译：自对准和扩展的井间隔离结构
公开(公告)号：US07750429B2
公开(公告)日：2010-07-06
申请号：US11748521
申请日：2007-05-15
申请人： Thomas W. Dyer , Zhijiong Luo , Haining S. Yang
发明人： Thomas W. Dyer , Zhijiong Luo , Haining S. Yang
IPC分类号： H01L29/78
CPC分类号： H01L21/76229 , H01L21/3086 , H01L21/823878
摘要： A pedestal is formed out of the pad layer such that two edges of the pedestal coincide with a border of the wells as implanted. An extended pedestal is formed over the pedestal by depositing a conformal dielectric layer. The area of the extended pedestal is exposed the semiconductor surface below is recessed to a recess depth. Other trenches including at least one intra-well isolation trench are lithographically patterned. After a reactive ion etch, both an inter-well isolation trench and at least one intra-well isolation trench are formed. The width of the inter-well isolation trench may be reduced due to the deeper bottom surface compared to the prior art structures. The boundary between the p-well and the n-well below the inter-well isolation structure is self-aligned to the middle of the inter-well isolation structure.
摘要翻译：从衬垫层形成基座，使得底座的两个边缘与植入的孔的边界重合。通过沉积保形介电层在基座上形成延伸基座。扩展基座的面积暴露在下方的半导体表面凹陷到凹陷深度。包括至少一个井内隔离沟槽的其它沟槽被光刻图案化。在反应离子蚀刻之后，形成阱间隔离沟槽和至少一个阱间隔离沟槽。与现有技术的结构相比，由于较深的底面，间隙隔离沟槽的宽度可能会降低。在井间隔离结构下面的p阱和n阱之间的边界与井间隔离结构的中间自对准。

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