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71. 发明申请

US20110172429A1 STAT3 INHIBITOR CONTAINING QUINOLINECARBOXAMIDE DERIVATIVE AS ACTIVE INGREDIENT 有权
标题翻译：含有喹啉甲酰胺衍生物的STAT3抑制剂作为活性成分
公开(公告)号：US20110172429A1
公开(公告)日：2011-07-14
申请号：US13003441
申请日：2009-07-10
申请人： Akira Asai , Kenji Matsuno , Naohisa Ogo , Takane Yokotagawa , Osamu Takahashi , Yasuto Akiyama , Tadashi Ashizawa , Tadashi Okawara
发明人： Akira Asai , Kenji Matsuno , Naohisa Ogo , Takane Yokotagawa , Osamu Takahashi , Yasuto Akiyama , Tadashi Ashizawa , Tadashi Okawara
IPC分类号： C07D215/14
CPC分类号： C07D401/12 , A61K31/4709 , C07D413/12 , C07D413/14 , C07D417/12 , C07D417/14
摘要： The present invention provides a STATS inhibitor containing as an active ingredient, a quinolinecarboxamide derivative represented by the formula (I) (in the formula, W represents a bond or an alkylene chain; X represents O, S, or NR34; and R1 to R8 and R34 each represent H, halogen, alkyl, phenyl, furyl, thienyl, or the like.), or a pharmacologically acceptable salt thereof.
摘要翻译：本发明提供含有作为活性成分的式（I）所示的喹啉甲酰胺衍生物的STATS抑制剂（式中，W表示键或亚烷基链; X表示O，S或NR34; R1〜R8 和R 34各自表示H，卤素，烷基，苯基，呋喃基，噻吩基等）或其药理学上可接受的盐。

72. 发明授权

US07781033B2 Optical film, method of producing the same, optical compensatory film, polarizing film, and liquid crystal display device 有权
标题翻译：光学膜，其制造方法，光学补偿膜，偏振膜和液晶显示装置
公开(公告)号：US07781033B2
公开(公告)日：2010-08-24
申请号：US11480467
申请日：2006-07-05
申请人： Hiromoto Haruta , Osamu Takahashi
发明人： Hiromoto Haruta , Osamu Takahashi
IPC分类号： G02F1/1335
CPC分类号： G02B5/3083 , C08J5/18 , Y10T428/1036 , Y10T428/1041 , Y10T428/105
摘要： An optical film comprising a layer consisting mainly of an organic compound and a layer containing inorganic fine particles wherein a content of the organic compound having a molecular weight of 1000 or less is 30% by mass or less based on a content of the inorganic fine particles. The optical film exhibits a low haze and a high contrast when being assembled into a liquid crystal display device.
摘要翻译：一种光学膜，其包含主要由有机化合物组成的层和含有无机细颗粒的层，其中基于无机细颗粒的含量，分子量为1000以下的有机化合物的含量为30质量％以下。当组装成液晶显示装置时，该光学薄膜呈现低雾度和高对比度。

73. 发明授权

US07780342B2 Spring device and timepiece 有权
标题翻译：弹簧装置和钟表
公开(公告)号：US07780342B2
公开(公告)日：2010-08-24
申请号：US12207164
申请日：2008-09-09
申请人： Osamu Takahashi , Nobuyuki Hirose , Masaaki Maejima , Masatoshi Moteki
发明人： Osamu Takahashi , Nobuyuki Hirose , Masaaki Maejima , Masatoshi Moteki
IPC分类号： G04B1/10
CPC分类号： G04B1/10 , G04B9/02
摘要： A spring device having an inside-end wheel that moves in conjunction with the inside end of a mainspring; an outside-end wheel that moves in conjunction with the outside end of the mainspring; a torque return unit that transfers part of the output torque of the mainspring from one to the other of the inside-end wheel and outside-end wheel; a duration time indicating unit that operates in conjunction with both the inside-end wheel and outside-end wheel and indicates the number of winds in the mainspring; and a torque transfer clutch unit that disengages torque transfer between the inside-end wheel and outside-end wheel by means of the torque return unit when the mainspring unwinds and the duration time indicating unit indicates a predetermined reference number of winds.
摘要翻译：弹簧装置，其具有与主发条的内端一起移动的内端轮; 与主发条的外端一起移动的外端轮; 转矩返回单元，其将主发条的输出转矩的一部分从内端轮和外端轮中的一个转移到另一个; 持续时间指示单元，其与内端轮和外端轮一起操作并且指示主发条中的风数; 以及扭矩传递离合器单元，当发条退绕和持续时间指示单元指示预定的参考数量时，借助于转矩返回单元使内端轮和外端轮之间的转矩传递脱离。

74. 发明授权

US07746140B2 Scannable latch 有权
标题翻译：可扫描闩锁
公开(公告)号：US07746140B2
公开(公告)日：2010-06-29
申请号：US11550997
申请日：2006-10-19
申请人： Sang Hoo Dhong , Joel A. Silberman , Osamu Takahashi
发明人： Sang Hoo Dhong , Joel A. Silberman , Osamu Takahashi
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/356113 , G01R31/318541
摘要： A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.
摘要翻译：公开了可扫描的闩锁。可扫描锁存器包括动态电路，耦合到动态电路的两个交叉耦合NAND门和耦合到动态电路的一对堆叠晶体管。堆叠晶体管中的一个用于接收数据信号，而另一个堆叠晶体管用于接收扫描信号。

75. 发明授权

US07710796B2 Level shifter for boosting wordline voltage and memory cell performance 有权
标题翻译：电平移位器用于提高字线电压和存储单元性能
公开(公告)号：US07710796B2
公开(公告)日：2010-05-04
申请号：US11935741
申请日：2007-11-06
申请人： Scott R. Cottier , Sang Hoo Dhong , Rajiv V. Joshi , Juergen Pille , Osamu Takahashi
发明人： Scott R. Cottier , Sang Hoo Dhong , Rajiv V. Joshi , Juergen Pille , Osamu Takahashi
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C11/418
摘要： A circuit and method includes first circuits powered by a first supply voltage and second circuits powered by a second supply voltage. A level shifter is coupled between the first circuits and the second circuits. The level shifter is configured to select a supply voltage output for a circuit including one of the first supply voltage and the second supply voltage in accordance an input signal, where the input signal depends on at least one of an operation to be performed and component performing the operation.
摘要翻译：电路和方法包括由第一电源电压供电的第一电路和由第二电源电压供电的第二电路。电平移位器耦合在第一电路和第二电路之间。电平移位器被配置为根据输入信号选择包括第一电源电压和第二电源电压中的一个的电路的电源电压输出，其中输入信号取决于要执行的操作和组件执行中的至少一个的操作。

76. 发明申请

US20080298553A1 Particle-Beam Treatment System 有权
标题翻译：粒子束处理系统
公开(公告)号：US20080298553A1
公开(公告)日：2008-12-04
申请号：US11870512
申请日：2007-10-11
申请人： Osamu Takahashi , Yuehu Pu , Hisashi Harada , Masahiro Ikeda , Yasuyuki Takatani , Hiroshi Otani
发明人： Osamu Takahashi , Yuehu Pu , Hisashi Harada , Masahiro Ikeda , Yasuyuki Takatani , Hiroshi Otani
IPC分类号： G21K5/04
CPC分类号： A61N5/1042 , A61B5/1127 , A61N5/1064 , A61N2005/1059 , A61N2005/1087 , G21K1/046
摘要： Provision is made for a particle-beam treatment system in which, even during particle-beam irradiation, the shape of a multileaf collimator is monitored. The particle-beam treatment system, in which multi-layer conformal irradiation is performed while the setting of the shape of the multileaf collimator in an irradiation head is changed during particle-beam irradiation, is provided with an optical shape-monitoring unit mounted attachably and detachably in the snout portion at the downstream side of the multileaf collimator, the optical shape-monitoring unit having a shape-monitoring mirror, opposing the multileaf collimator, for monitoring the shape of the multileaf collimator; a video camera for shooting the multileaf-collimator shape reflected by the shape-monitoring mirror; and an image monitor for displaying an image of the video camera that shoots the shape of the multileaf collimator.
摘要翻译：规定了一种粒子束处理系统，其中即使在粒子束照射期间，监视多叶准直器的形状。在粒子束照射期间，在照射头中的多叶准直器的形状的设定被改变的同时进行多层共形照射的粒子束处理系统设置有可安装地安装的光学形状监视单元，所述光学形状监视单元具有与所述多叶准直器相对的形状监视镜，用于监视所述多叶准直器的形状; 用于拍摄由形状监视镜反射的多叶准直器形状的摄像机; 以及用于显示拍摄多叶准直器的形状的摄像机的图像的图像监视器。

77. 发明申请

US20080254237A1 Polymer Film, and Optically-Compensatory Film, Polarizer and Liquid-Crystal Display Device Comprising the Same 有权
标题翻译：聚合物膜和光学补偿膜，偏振器和包括其的液晶显示装置
公开(公告)号：US20080254237A1
公开(公告)日：2008-10-16
申请号：US11659705
申请日：2005-08-05
申请人： Tadashi Omatsu , Hajime Nakayama , Akihiro Matsufuji , Osamu Takahashi , Shigeaki Nimura , Yousuke Nishiura , Takako Nishiura
发明人： Tadashi Omatsu , Hajime Nakayama , Akihiro Matsufuji , Osamu Takahashi , Shigeaki Nimura , Yousuke Nishiura , Takako Nishiura
IPC分类号： G02B1/08 , G02B5/30 , G02F1/1335
CPC分类号： G02B1/08 , C08J7/12 , C08J2301/10 , G02B5/3016 , Y10T428/1041 , Y10T428/31
摘要： A polymer film that has an in-plane retardation Re(λ) and a thickness-direction retardation Rth(λ) satisfying formula (i) and (ii), and that further has a surface energy of at least one surface is from 50 mN/m to 80 mN/m: (i) 0≦Re(630)≦10, and |Rth(630)|≦25; and (ii) |Re(400)−Re(700)≦10, and |Rth(400)−Rth(700)|≦35. in the formulae, Re(λ) and Rth(λ) are measurement values at the wavelength of λ nm, and an optically-compensatory film, an optical material such as a polarizer and a liquid-crystal display device using the polymer film.
摘要翻译：具有面内相位差Re（λ）＆lt;＆gt;和满足式（i）和（ii）的厚度方向延迟Rth（λ）的聚合物膜，并且进一步具有至少一个表面的表面能为50mN / m至80mN / m：（i）0 <= RE（630）<= 10，和| RTH | <= 25; AND（II）| RE（400）（700）<= 10，AND | RTH（400）（700） <= 35。在公式中，Re（λ）和Rth（λ）是波长为λnm的测量值，光学补偿膜，光学材料如偏振片和使用聚合物膜的液晶显示装置。

78. 发明申请

US20080189670A1 METHOD OF LOGIC CIRCUIT SYNTHESIS AND DESIGN USING A DYNAMIC CIRCUIT LIBRARY 有权
标题翻译：使用动态电路图的逻辑电路合成和设计方法
公开(公告)号：US20080189670A1
公开(公告)日：2008-08-07
申请号：US12060768
申请日：2008-04-01
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块，然后执行用于要实现的预定逻辑运算的逻辑合成。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计，其必然包括一系列动态电路块，每个动态电路块与单个复位信号相关联。一旦生成了中间电路，电路设计方法包括从中间电路中消除不必要的设备，产生最终的逻辑电路，然后对最终电路中的器件进行尺寸调整以完成设计。

79. 发明授权

US07363609B2 Method of logic circuit synthesis and design using a dynamic circuit library 有权
标题翻译：使用动态电路库的逻辑电路合成与设计方法
公开(公告)号：US07363609B2
公开(公告)日：2008-04-22
申请号：US09915437
申请日：2001-07-26
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block (16) and then performing logic synthesis (17) for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design (29) which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit (29) is produced, the circuit design method includes eliminating unnecessary devices (46) from the intermediate circuit (29) to produce a final logic circuit, and then sizing the devices (48) in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块（16），然后执行用于要实现的预定逻辑运算的逻辑合成（17）。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计（29），其必须包括一系列与单个复位信号相关联的动态电路块。一旦产生中间电路（29），电路设计方法包括从中间电路（29）消除不必要的装置（46）以产生最终的逻辑电路，然后对最终电路中的装置（48）进行尺寸调整以完成设计。

80. 发明申请

US20080013388A1 Method and Apparatus for Wordline Redundancy Control of Memory in an Information Handling System 失效
标题翻译：信息处理系统中字节冗余控制的方法与装置
公开(公告)号：US20080013388A1
公开(公告)日：2008-01-17
申请号：US11457507
申请日：2006-07-14
申请人： Toru Asano , Sang H. Dhong , Takaaki Nakazato , Osamu Takahashi
发明人： Toru Asano , Sang H. Dhong , Takaaki Nakazato , Osamu Takahashi
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/848
摘要： A memory system including a memory array with redundant wordlines is disclosed. The memory system includes a memory wordline tester that determines if any of the wordlines exhibits a defect. The memory system also includes decoder redundancy logic that efficiently couples to wordline shift logic using a reduced number of control signal lines therebetween. The shift logic shifts defective wordlines to upstream wordlines in the array to bypass the defective wordlines.
摘要翻译：公开了一种包括具有冗余字线的存储器阵列的存储器系统。存储器系统包括存储器字线测试器，其确定任何字线是否存在缺陷。存储器系统还包括使用其间数量减少的控制信号线有效地耦合到字线移位逻辑的解码器冗余逻辑。移位逻辑将有缺陷的字线转移到阵列中的上游字线以绕过有缺陷的字线。

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