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1. 发明授权

US07710796B2 Level shifter for boosting wordline voltage and memory cell performance 有权
标题翻译：电平移位器用于提高字线电压和存储单元性能
公开(公告)号：US07710796B2
公开(公告)日：2010-05-04
申请号：US11935741
申请日：2007-11-06
申请人： Scott R. Cottier , Sang Hoo Dhong , Rajiv V. Joshi , Juergen Pille , Osamu Takahashi
发明人： Scott R. Cottier , Sang Hoo Dhong , Rajiv V. Joshi , Juergen Pille , Osamu Takahashi
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C11/418
摘要： A circuit and method includes first circuits powered by a first supply voltage and second circuits powered by a second supply voltage. A level shifter is coupled between the first circuits and the second circuits. The level shifter is configured to select a supply voltage output for a circuit including one of the first supply voltage and the second supply voltage in accordance an input signal, where the input signal depends on at least one of an operation to be performed and component performing the operation.
摘要翻译：电路和方法包括由第一电源电压供电的第一电路和由第二电源电压供电的第二电路。电平移位器耦合在第一电路和第二电路之间。电平移位器被配置为根据输入信号选择包括第一电源电压和第二电源电压中的一个的电路的电源电压输出，其中输入信号取决于要执行的操作和组件执行中的至少一个的操作。

2. 发明申请

US20090116307A1 LEVEL SHIFTER FOR BOOSTING WORDLINE VOLTAGE AND MEMORY CELL PERFORMANCE 有权
标题翻译：提高字线电压和存储单元性能的级别更换
公开(公告)号：US20090116307A1
公开(公告)日：2009-05-07
申请号：US11935741
申请日：2007-11-06
申请人： Scott R. Cottier , Sang Hoo Dhong , Rajiv V. Joshi , Juergen Pille , Osamu Takahashi
发明人： Scott R. Cottier , Sang Hoo Dhong , Rajiv V. Joshi , Juergen Pille , Osamu Takahashi
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C11/418
摘要： A circuit and method includes first circuits powered by a first supply voltage and second circuits powered by a second supply voltage. A level shifter is coupled between the first circuits and the second circuits. The level shifter is configured to select a supply voltage output for a circuit including one of the first supply voltage and the second supply voltage in accordance an input signal, where the input signal depends on at least one of an operation to be performed and component performing the operation.
摘要翻译：电路和方法包括由第一电源电压供电的第一电路和由第二电源电压供电的第二电路。电平移位器耦合在第一电路和第二电路之间。电平移位器被配置为根据输入信号选择包括第一电源电压和第二电源电压中的一个的电路的电源电压输出，其中输入信号取决于要执行的操作和组件执行中的至少一个的操作。

3. 发明授权

US07225422B2 Wire trimmed programmable logic array 有权
标题翻译：电线修剪可编程逻辑阵列
公开(公告)号：US07225422B2
公开(公告)日：2007-05-29
申请号：US10464879
申请日：2003-06-19
申请人： Robert John Bucki , Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi
发明人： Robert John Bucki , Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of designing a logic circuit includes providing a leaf cell having at least one transistor. The leaf is suitable for use as a 1-cell or a 0-cell in the logic circuit. A first array of abutting leaf cells is tiled using at least one 1-cell and at least one 0-cell to define at least one logical expression by the relative positions of the array cells. Length optimized interconnects are added to the array. Each length optimized interconnect terminates at a last leaf cell in the array to which the interconnect makes contact. The leaf cell may be a floating leaf cell in which any pair of abutting cells are electrically isolated from one another until the length optimized interconnects are added to the design. The leaf cell array likely includes a set of rows and a set of columns in which the leaf cells in each row and the set of columns each correspond to an input of the logical expression.
摘要翻译：设计逻辑电路的方法包括提供具有至少一个晶体管的叶单元。叶片适用于逻辑电路中的1单元或0单元。使用至少一个1-单元和至少一个O单元来平铺第一对接叶单元阵列以通过阵列单元的相对位置限定至少一个逻辑表达式。长度优化的互连将添加到阵列中。每个长度优化的互连终止于互连接触到的阵列中的最后一个叶单元格。叶细胞可以是浮叶细胞，其中任何一对邻接细胞彼此电隔离，直到长度优化的互连被添加到设计中。叶单元阵列可能包括一组行和一组列，其中每行中的叶单元和列组各自对应于逻辑表达式的输入。

4. 发明授权

US07139215B2 Apparatus and method of word line decoding for deep pipelined memory 失效
公开(公告)号：US07139215B2
公开(公告)日：2006-11-21
申请号：US10982109
申请日：2004-11-05
申请人： Toru Asano , Sang Hoo Dhong , Takaaki Nakazato , Osamu Takahashi
发明人： Toru Asano , Sang Hoo Dhong , Takaaki Nakazato , Osamu Takahashi
IPC分类号： G11C8/00
CPC分类号： G11C7/1039 , G11C8/08 , G11C8/10
摘要： A method, an apparatus, and a computer program are provided to reduce the number of required latches in a deep pipeline wordline (WL) decoder. Traditionally, a signal local clock buffer (LCB) has been responsible for providing a driving signal to a WL driver. However, with this configuration, a large number of latches are utilized. To reduce this latch usage, a number of LCBs are employed, such that one latch can enable an increased number of WLs. Hence, the overall area occupied by latches is reduced and power consumption is reduced.

5. 发明授权

US06850456B2 Subarray control and subarray cell access in a memory module 失效
标题翻译：存储器模块中的子阵列控制和子阵列单元访问
公开(公告)号：US06850456B2
公开(公告)日：2005-02-01
申请号：US10606585
申请日：2003-06-26
申请人： Toru Asano , Sang Hoo Dhong , Takaaki Nakazato , Osamu Takahashi
发明人： Toru Asano , Sang Hoo Dhong , Takaaki Nakazato , Osamu Takahashi
IPC分类号： G11C7/22 , G11C8/08 , G11C8/18 , G11C8/00
CPC分类号： G11C7/22 , G11C8/08 , G11C8/18
摘要： The present invention provides a subarray control apparatus and method. The subarray control includes a wordline driver configured to generate a wordline activation signal, and a write/read control signal generator configured to generate a write/read enable signal. In addition, the subarray control includes a timing generator configured to generate a wordline timing signal input to the wordline driver and a write/read timing signal input to the write/read control signal generator. The wordline activation signal is based on enable data captured by a first transparent latching circuit and the wordline timing signal generated within the subarray. The write/read enable signal is based on enable data captured by a second transparent latching circuit and the write/read timing signal generated within the subarray. Accessing subarray cells in a memory module and a memory module incorporating the subarray control are also disclosed.
摘要翻译：本发明提供了一种子阵列控制装置和方法。子阵列控制包括被配置为产生字线激活信号的字线驱动器，以及被配置为产生写/读使能信号的写/读控制信号发生器。此外，子阵列控制包括定时发生器，其被配置为产生输入到字线驱动器的字线定时信号和输入到写/读控制信号发生器的写/读定时信号。字线激活信号基于由第一透明锁存电路捕获的使能数据和在子阵列内生成的字线定时信号。写/读使能信号基于由第二透明锁存电路捕获的使能数据和在子阵列内生成的写/读定时信号。还公开了存储器模块中的子阵列单元和并入子阵列控制的存储器模块。

6. 发明授权

US06825695B1 Unified local clock buffer structures 失效
标题翻译：统一本地时钟缓冲结构
公开(公告)号：US06825695B1
公开(公告)日：2004-11-30
申请号：US10455170
申请日：2003-06-05
申请人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
发明人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
IPC分类号： H03K19096
CPC分类号： G06F1/10
摘要： Several local clock buffers are disclosed, each including an input section and an output section. The input sections are substantially identical, and include control logic and gating logic. The control logic produces a gating signal dependent upon multiple control signals and a time-delayed global clock signal. The gating logic produces an intermediate clock signal dependent upon the global clock signal and the gating signal. The output section produces at least one local clock signal dependent upon the intermediate clock signal. In one embodiment, the output section produces a first local clock signal dependent upon the intermediate clock signal and a second local clock signal dependent upon the first local clock signal. In another embodiment, the gating logic produces the intermediate clock signal dependent upon the global clock and gating signals and a feedback signal. The output section produces the feedback signal and one or more local clock signals.
摘要翻译：公开了几个本地时钟缓冲器，每个本地时钟缓冲器包括输入部分和输出部分。输入部分基本相同，包括控制逻辑和门控逻辑。控制逻辑产生取决于多个控制信号和时间延迟的全局时钟信号的选通信号。门控逻辑产生取决于全局时钟信号和门控信号的中间时钟信号。输出部分根据中间时钟信号产生至少一个本地时钟信号。在一个实施例中，输出部分产生取决于中间时钟信号的第一本地时钟信号和取决于第一本地时钟信号的第二本地时钟信号。在另一个实施例中，选通逻辑根据全局时钟和门控信号以及反馈信号产生中间时钟信号。输出部分产生反馈信号和一个或多个本地时钟信号。

7. 发明授权

US6104213A Domino logic circuit having a clocked precharge 失效
标题翻译：多米诺逻辑电路具有时钟预充电
公开(公告)号：US6104213A
公开(公告)日：2000-08-15
申请号：US32820
申请日：1998-03-02
申请人： Sang Hoo Dhong , Uttam Shyamalindu Ghoshal , Joel Abraham Silberman , Osamu Takahashi
发明人： Sang Hoo Dhong , Uttam Shyamalindu Ghoshal , Joel Abraham Silberman , Osamu Takahashi
IPC分类号： H03K19/096 , H03K3/01 , H03K19/0175
CPC分类号： H03K19/0963
摘要： A domino logic circuit having a clocked precharge is disclosed. The domino logic circuit includes a precharge transistor, a discharger transistor, several input transistors, and an invertor. Connected to a power supply, the precharge transistor receives a first clock input. The discharge transistor, connected to the ground, receives a second clock input. The input transistors is coupled between the precharge transistor and the discharge transistor. Each of the input transistors receives a signal input. The inverter has an input coupled to the precharge transistor, and an output to yield a signal output. The inverter includes a first transistor and a second transistor connected in series, and the output of the inverter is connected to a body of the first transistor.
摘要翻译：公开了具有时钟预充电的多米诺骨牌逻辑电路。多米诺逻辑电路包括预充电晶体管，放电晶体管，多个输入晶体管和反相器。连接到电源，预充电晶体管接收第一时钟输入。连接到地的放电晶体管接收第二个时钟输入。输入晶体管耦合在预充电晶体管和放电晶体管之间。每个输入晶体管接收信号输入。反相器具有耦合到预充电晶体管的输入端和产生信号输出的输出端。逆变器包括串联连接的第一晶体管和第二晶体管，反相器的输出端连接到第一晶体管的主体。

8. 发明授权

US07746140B2 Scannable latch 有权
标题翻译：可扫描闩锁
公开(公告)号：US07746140B2
公开(公告)日：2010-06-29
申请号：US11550997
申请日：2006-10-19
申请人： Sang Hoo Dhong , Joel A. Silberman , Osamu Takahashi
发明人： Sang Hoo Dhong , Joel A. Silberman , Osamu Takahashi
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/356113 , G01R31/318541
摘要： A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.
摘要翻译：公开了可扫描的闩锁。可扫描锁存器包括动态电路，耦合到动态电路的两个交叉耦合NAND门和耦合到动态电路的一对堆叠晶体管。堆叠晶体管中的一个用于接收数据信号，而另一个堆叠晶体管用于接收扫描信号。

9. 发明申请

US20080189670A1 METHOD OF LOGIC CIRCUIT SYNTHESIS AND DESIGN USING A DYNAMIC CIRCUIT LIBRARY 有权
标题翻译：使用动态电路图的逻辑电路合成和设计方法
公开(公告)号：US20080189670A1
公开(公告)日：2008-08-07
申请号：US12060768
申请日：2008-04-01
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块，然后执行用于要实现的预定逻辑运算的逻辑合成。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计，其必然包括一系列动态电路块，每个动态电路块与单个复位信号相关联。一旦生成了中间电路，电路设计方法包括从中间电路中消除不必要的设备，产生最终的逻辑电路，然后对最终电路中的器件进行尺寸调整以完成设计。

10. 发明授权

US07363609B2 Method of logic circuit synthesis and design using a dynamic circuit library 有权
标题翻译：使用动态电路库的逻辑电路合成与设计方法
公开(公告)号：US07363609B2
公开(公告)日：2008-04-22
申请号：US09915437
申请日：2001-07-26
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block (16) and then performing logic synthesis (17) for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design (29) which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit (29) is produced, the circuit design method includes eliminating unnecessary devices (46) from the intermediate circuit (29) to produce a final logic circuit, and then sizing the devices (48) in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块（16），然后执行用于要实现的预定逻辑运算的逻辑合成（17）。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计（29），其必须包括一系列与单个复位信号相关联的动态电路块。一旦产生中间电路（29），电路设计方法包括从中间电路（29）消除不必要的装置（46）以产生最终的逻辑电路，然后对最终电路中的装置（48）进行尺寸调整以完成设计。

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