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1. 发明申请

US20080013388A1 Method and Apparatus for Wordline Redundancy Control of Memory in an Information Handling System 失效
标题翻译：信息处理系统中字节冗余控制的方法与装置
公开(公告)号：US20080013388A1
公开(公告)日：2008-01-17
申请号：US11457507
申请日：2006-07-14
申请人： Toru Asano , Sang H. Dhong , Takaaki Nakazato , Osamu Takahashi
发明人： Toru Asano , Sang H. Dhong , Takaaki Nakazato , Osamu Takahashi
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/848
摘要： A memory system including a memory array with redundant wordlines is disclosed. The memory system includes a memory wordline tester that determines if any of the wordlines exhibits a defect. The memory system also includes decoder redundancy logic that efficiently couples to wordline shift logic using a reduced number of control signal lines therebetween. The shift logic shifts defective wordlines to upstream wordlines in the array to bypass the defective wordlines.
摘要翻译：公开了一种包括具有冗余字线的存储器阵列的存储器系统。存储器系统包括存储器字线测试器，其确定任何字线是否存在缺陷。存储器系统还包括使用其间数量减少的控制信号线有效地耦合到字线移位逻辑的解码器冗余逻辑。移位逻辑将有缺陷的字线转移到阵列中的上游字线以绕过有缺陷的字线。

2. 发明授权

US07423921B2 Method and apparatus for wordline redundancy control of memory in an information handling system 失效
标题翻译：用于信息处理系统中存储器的字线冗余控制的方法和装置
公开(公告)号：US07423921B2
公开(公告)日：2008-09-09
申请号：US11457507
申请日：2006-07-14
申请人： Toru Asano , Sang H. Dhong , Takaaki Nakazato , Osamu Takahashi
发明人： Toru Asano , Sang H. Dhong , Takaaki Nakazato , Osamu Takahashi
IPC分类号： G11C7/00
CPC分类号： G11C29/848
摘要： A memory system including a memory array with redundant wordlines. The memory system includes a memory wordline tester that determines if any of the wordlines exhibits a defect. The memory system also includes decoder redundancy logic that efficiently couples to wordline shift logic using a reduced number of control signal lines therebetween. The shift logic shifts defective wordlines to upstream wordlines in the array to bypass the defective wordlines.
摘要翻译：包括具有冗余字线的存储器阵列的存储器系统。存储器系统包括存储器字线测试器，其确定任何字线是否存在缺陷。存储器系统还包括使用其间数量减少的控制信号线有效地耦合到字线移位逻辑的解码器冗余逻辑。移位逻辑将有缺陷的字线转移到阵列中的上游字线以绕过有缺陷的字线。

3. 发明申请

US20070043895A1 Method and apparatus for row based power control of a microprocessor memory array 审中-公开
标题翻译：微处理器存储器阵列的基于行的功率控制的方法和装置
公开(公告)号：US20070043895A1
公开(公告)日：2007-02-22
申请号：US11204417
申请日：2005-08-16
申请人： Chad Adams , Toru Asano , Sang Dhong , Takaaki Nakazato , Joel Silberman , Osamu Takahashi
发明人： Chad Adams , Toru Asano , Sang Dhong , Takaaki Nakazato , Joel Silberman , Osamu Takahashi
IPC分类号： G06F12/06 , G06F1/00
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3275 , G11C8/08 , Y02D10/128 , Y02D10/14 , Y02D10/152
摘要： An apparatus, a method, and a computer program are provided to efficiently use a microprocessor array. Typically, microprocessor arrays can be divided into multiple subarrays. Also, in the conventional arrays, each of the subarrays were engaged when the microprocessor array is used. To alleviate the power consumed by the microprocessor arrays, row selection logic is employed to engage only specific rows of subarrays. Therefore, power consumed by unused subarrys is saved.
摘要翻译：提供了一种装置，方法和计算机程序以有效地使用微处理器阵列。通常，微处理器阵列可以分为多个子阵列。此外，在常规阵列中，当使用微处理器阵列时，每个子阵列被接合。为了减轻微处理器阵列消耗的功率，采用行选择逻辑仅与特定的子阵列相啮合。因此，省去了未使用的亚军消耗的电力。

4. 发明授权

US07053668B2 SOI sense amplifier with cross-coupled body terminal 有权
标题翻译：具有交叉耦合体端子的SOI读出放大器
公开(公告)号：US07053668B2
公开(公告)日：2006-05-30
申请号：US10852863
申请日：2004-05-25
申请人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong
发明人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong
IPC分类号： G01R19/00 , G11C7/00 , H03F3/45
CPC分类号： H03K3/012 , G11C7/065 , H03K3/356139
摘要： Systems and methods for increasing the amount of current that can flow through the data line pull-down transistors in a sense amplifier by tying the bodies of these transistors to a voltage other than ground. In one embodiment, the bodies of the data line pull-down transistors in a sense amplifier are tied to the intermediate nodes on the opposing side of the sense amplifier to increase the current flow through the data line pull-down transistors, and also to reduce the voltage at the intermediate node that will be pulled low by the action of the bit line transistors. In one embodiment, the sense amplifier also includes pre-charge circuits which pre-charge the intermediate nodes to a predetermined voltage that is not reduced by the threshold voltage of the pull-down transistors.
摘要翻译：用于通过将这些晶体管的主体连接到除地之外的电压来增加可以流过读出放大器中的数据线下拉晶体管的电流量的系统和方法。在一个实施例中，读出放大器中的数据线下拉晶体管的主体被连接到读出放大器的相对侧上的中间节点，以增加通过数据线下拉晶体管的电流，并且还减少通过位线晶体管的动作将中间节点处的电压拉低。在一个实施例中，读出放大器还包括将中间节点预充电到未被下拉晶体管的阈值电压降低的预定电压的预充电电路。

5. 发明申请

US20050264322A1 SOI sense amplifier with pre-charge 审中-公开
标题翻译：具有预充电的SOI读出放大器
公开(公告)号：US20050264322A1
公开(公告)日：2005-12-01
申请号：US10852868
申请日：2004-05-25
申请人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong
发明人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong
IPC分类号： G11C11/419 , G11C7/06 , G11C7/12 , H03F3/45 , H03K3/356 , H03K19/0948
CPC分类号： G11C7/065 , G11C7/12 , H03F3/45183 , H03F2203/45318
摘要： Systems and methods for pre-charging opposing nodes in a sense amplifier to substantially the same voltage in order to reduce or eliminate malfunctions arising from differences in threshold voltages of transistors coupled to the opposing nodes. One embodiment is a method including providing a silicon-on-insulator (SOI) sense amplifier having intermediate nodes between the transistors coupling each output data line to the corresponding input bit line and pre-charging each intermediate node to a predetermined voltage while the sense amplifier is not enabled. In one embodiment, the intermediate nodes are pre-charged by coupling them to a voltage source through pre-charge paths that do not include the data line pull-down transistors. In one embodiment, the method also includes decoupling the pre-charge paths after pre-charging the intermediate nodes and then enabling the sense amplifier.
摘要翻译：用于将读出放大器中的相对节点预充电到基本相同的电压的系统和方法，以便减少或消除由耦合到相对节点的晶体管的阈值电压的差异引起的故障。一个实施例是一种方法，包括提供绝缘体上硅（SOI）读出放大器，该晶体管在晶体管之间具有中间节点，每个晶体管将每个输出数据线耦合到相应的输入位线，并将每个中间节点预充电到预定电压，而读出放大器未启用在一个实施例中，中间节点通过不包括数据线下拉晶体管的预充电路径将其耦合到电压源进行预充电。在一个实施例中，该方法还包括在对中间节点预充电然后启用读出放大器之后去耦合预充电路径。

6. 发明授权

US06898135B2 Latch type sense amplifier method and apparatus 失效
标题翻译：锁存型读出放大器的方法和装置
公开(公告)号：US06898135B2
公开(公告)日：2005-05-24
申请号：US10606587
申请日：2003-06-26
申请人： Toru Asano , Sang Hoo Dhong , Takaaki Nakazato , Osamu Takahashi
发明人： Toru Asano , Sang Hoo Dhong , Takaaki Nakazato , Osamu Takahashi
IPC分类号： G11C7/06 , G11C7/10 , G11C7/00
CPC分类号： G11C7/1069 , G11C7/065 , G11C7/1051
摘要： Disclosed is an apparatus for and a method of overcoming signal delay problems in a read-out path occurring in connection with pipelined memory circuits. A latch type sense amplifier (SA) is used to receive the memory cell logic levels during a pre-charge state in a cycle prior to read-out. Thus, the SA may quickly provide an output signal during a read latch clock cycle. The SA output is passed through a dynamically enabled logic circuit to a latch circuit for holding the receiving logic value for use in the next clock cycle.
摘要翻译：公开了一种克服与流水线存储器电路相关的读出路径中的信号延迟问题的装置和方法。闩锁型读出放大器（SA）用于在读出之前的一个周期中的预充电状态期间接收存储单元逻辑电平。因此，SA可以在读取锁存时钟周期期间快速提供输出信号。 SA输出通过一个动态使能的逻辑电路被传送到一个锁存电路，用于保持接收逻辑值用于下一个时钟周期。

7. 发明申请

US20050264324A1 SOI sense amplifier with cross-coupled body terminal 有权
标题翻译：具有交叉耦合体端子的SOI读出放大器
公开(公告)号：US20050264324A1
公开(公告)日：2005-12-01
申请号：US10852863
申请日：2004-05-25
申请人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong
发明人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong
IPC分类号： G11C11/419 , G11C7/06 , H03F3/45 , H03K3/012 , H03K3/356
CPC分类号： H03K3/012 , G11C7/065 , H03K3/356139
摘要： Systems and methods for increasing the amount of current that can flow through the data line pull-down transistors in a sense amplifier by tying the bodies of these transistors to a voltage other than ground. In one embodiment, the bodies of the data line pull-down transistors in a sense amplifier are tied to the intermediate nodes on the opposing side of the sense amplifier to increase the current flow through the data line pull-down transistors, and also to reduce the voltage at the intermediate node that will be pulled low by the action of the bit line transistors. In one embodiment, the sense amplifier also includes pre-charge circuits which pre-charge the intermediate nodes to a predetermined voltage that is not reduced by the threshold voltage of the pull-down transistors.
摘要翻译：用于通过将这些晶体管的主体连接到除地之外的电压来增加可以流过读出放大器中的数据线下拉晶体管的电流量的系统和方法。在一个实施例中，读出放大器中的数据线下拉晶体管的主体被连接到读出放大器的相对侧上的中间节点，以增加通过数据线下拉晶体管的电流，并且还减少通过位线晶体管的动作将中间节点处的电压拉低。在一个实施例中，读出放大器还包括将中间节点预充电到未被下拉晶体管的阈值电压降低的预定电压的预充电电路。

8. 发明授权

US06885596B2 Apparatus and method of wordline/bitline redundancy control using shift registers in an SRAM 失效
标题翻译：使用SRAM中的移位寄存器进行字线/位线冗余控制的装置和方法
公开(公告)号：US06885596B2
公开(公告)日：2005-04-26
申请号：US10606584
申请日：2003-06-26
申请人： Toru Asano , Sang Hoo Dhong , Takaaki Nakazato , Osamu Takahashi
发明人： Toru Asano , Sang Hoo Dhong , Takaaki Nakazato , Osamu Takahashi
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/806
摘要： A decoder for use in wordline/bitline redundancy control is disclosed. In one aspect, the decoder includes first and second wordlines respectively coupled to redundant first and second wordlines, where the first and second wordlines are configured to be activated based on decoded first and second addresses. In addition, the decoder includes first and second shift registers respectively coupled to the redundant first and second wordlines, where each is configured to respectively activate the redundant first and second wordlines when the first or second wordlines contain a defect. In addition, a method of selecting wordlines for use in wordline/bitline redundancy control and a wordline decoder having redundancy control capabilities are also disclosed.
摘要翻译：公开了一种用于字线/位线冗余控制的解码器。在一个方面，解码器包括分别耦合到冗余第一和第二字线的第一和第二字线，其中第一和第二字线被配置为基于经解码的第一和第二地址被激活。此外，解码器包括分别耦合到冗余第一和第二字线的第一和第二移位寄存器，其中每个被配置为当第一或第二字线包含缺陷时分别激活冗余第一和第二字线。此外，还公开了一种用于字线/位线冗余控制中使用的字线的方法和具有冗余控制能力的字线解码器。

9. 发明授权

US06833736B2 Pulse generating circuit 有权
公开(公告)号：US06833736B2
公开(公告)日：2004-12-21
申请号：US10359805
申请日：2003-02-07
申请人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong , Atsushi Kawasumi
发明人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong , Atsushi Kawasumi
IPC分类号： H03K908
CPC分类号： H03K5/1565 , H03K5/05 , H03K5/06
摘要： A pulse generator circuit includes a first logic means, a second logic means, a first delay means, and a second delay means. The first logic means is for receiving an input clock signal. The first delay means is for delaying the input clock signal by a first delay time. The second logic means is for receiving a signal output from the first logic means. The second delay means is for delaying the signal output from the first logic means by a second delay time.

10. 发明授权

US07139215B2 Apparatus and method of word line decoding for deep pipelined memory 失效
公开(公告)号：US07139215B2
公开(公告)日：2006-11-21
申请号：US10982109
申请日：2004-11-05
申请人： Toru Asano , Sang Hoo Dhong , Takaaki Nakazato , Osamu Takahashi
发明人： Toru Asano , Sang Hoo Dhong , Takaaki Nakazato , Osamu Takahashi
IPC分类号： G11C8/00
CPC分类号： G11C7/1039 , G11C8/08 , G11C8/10
摘要： A method, an apparatus, and a computer program are provided to reduce the number of required latches in a deep pipeline wordline (WL) decoder. Traditionally, a signal local clock buffer (LCB) has been responsible for providing a driving signal to a WL driver. However, with this configuration, a large number of latches are utilized. To reduce this latch usage, a number of LCBs are employed, such that one latch can enable an increased number of WLs. Hence, the overall area occupied by latches is reduced and power consumption is reduced.

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