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71. 发明申请

US20060237725A1 Semiconductor devices having thin film transistors and methods of fabricating the same 有权
标题翻译：具有薄膜晶体管的半导体器件及其制造方法
公开(公告)号：US20060237725A1
公开(公告)日：2006-10-26
申请号：US11364773
申请日：2006-02-28
申请人： Jae-Hun Jeong , Soon-Moon Jung , Hoon Lim , Won-Seok Cho , Jin-Ho Kim , Chang-Min Hong , Jong-Hyuk Kim , Kun-Ho Kwak
发明人： Jae-Hun Jeong , Soon-Moon Jung , Hoon Lim , Won-Seok Cho , Jin-Ho Kim , Chang-Min Hong , Jong-Hyuk Kim , Kun-Ho Kwak
IPC分类号： H01L29/76 , H01L29/00
CPC分类号： H01L27/0688 , H01L23/485 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having thin film transistors (TFTs) and methods of fabricating the same are provided. The semiconductor devices include a semiconductor substrate and a lower interlayer insulating layer disposed on the semiconductor substrate. A lower semiconductor body disposed on or in the lower interlayer insulating layer. A lower TFT includes a lower source region and a lower drain region, which are disposed in the lower semiconductor body, and a lower gate electrode, which covers and crosses at least portions of at least two surfaces of the lower semiconductor body disposed between the lower source and drain regions.
摘要翻译：提供具有薄膜晶体管（TFT）的半导体器件及其制造方法。半导体器件包括设置在半导体衬底上的半导体衬底和下层间绝缘层。下部半导体本体设置在下部层间绝缘层上或下部层间绝缘层中。下部TFT包括设置在下部半导体本体中的下部源极区域和下部漏极区域以及下部栅极电极，该下部栅极电极覆盖并交叉配置在下部半导体器件的下部半导体本体的至少两个表面的至少一部分源极和漏极区域。

72. 发明申请

US20060157848A1 Structure and method for joining a semiconductor package to a substrate using solder column 有权
标题翻译：使用焊料柱将半导体封装与基板接合的结构和方法
公开(公告)号：US20060157848A1
公开(公告)日：2006-07-20
申请号：US11330773
申请日：2006-01-11
申请人： Cheol-Joon Yoo , Jin-Ho Kim , Hee-Jin Park , Tae-Sung Yoon , Chan-Suk Lee
发明人： Cheol-Joon Yoo , Jin-Ho Kim , Hee-Jin Park , Tae-Sung Yoon , Chan-Suk Lee
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H05K3/3436 , H01L23/3128 , H01L24/10 , H01L24/13 , H01L24/48 , H01L2224/13 , H01L2224/13099 , H01L2224/48091 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H05K3/3452 , H05K3/3484 , H05K2201/10977 , H05K2203/0568 , Y02P70/613 , H01L2924/00 , H01L2224/0401 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In one embodiment, a semiconductor package and a package mounting substrate are joined using a conductive material column such as a solder column. Each of the semiconductor package and the package mounting substrate include an insulating protective opening exposing a wiring layer therein. The solder column resides within the insulating protective openings to electrically couple the wiring layers. By forming the insulating protective openings with sufficient depth, each protects the solder column against stress faults and thereby forms more reliable electrical connections and supports high-density electrical connections between the semiconductor package and the package mounting substrate.
摘要翻译：在一个实施例中，使用诸如焊料柱的导电材料柱将半导体封装和封装安装基板接合。半导体封装和封装安装衬底中的每一个包括暴露其中的布线层的绝缘保护开口。焊料柱位于绝缘保护开口内，以电连接布线层。通过形成具有足够深度的绝缘保护开口，每个保护焊料柱免受应力故障，从而形成更可靠的电连接并且支持半导体封装和封装安装基板之间的高密度电连接。

73. 发明申请

US20050205975A1 Semiconductor package having step type die and method for manufacturing the same 有权
标题翻译：具有步进式模具的半导体封装及其制造方法
公开(公告)号：US20050205975A1
公开(公告)日：2005-09-22
申请号：US11077235
申请日：2005-03-11
申请人： In-Ku Kang , Seok Goh , Jin-Ho Kim , Tae-Gyeong Chung , Yong-Jae Lee
发明人： In-Ku Kang , Seok Goh , Jin-Ho Kim , Tae-Gyeong Chung , Yong-Jae Lee
IPC分类号： H01L25/18 , H01L21/301 , H01L21/50 , H01L21/60 , H01L21/78 , H01L21/98 , H01L23/02 , H01L23/12 , H01L23/31 , H01L25/065 , H01L25/07 , H01L29/06
CPC分类号： H01L24/32 , H01L21/78 , H01L23/3128 , H01L24/05 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L29/0657 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/49175 , H01L2224/4945 , H01L2224/73204 , H01L2224/73265 , H01L2224/85051 , H01L2224/85191 , H01L2224/85399 , H01L2224/85986 , H01L2224/92247 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06582 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01033 , H01L2924/01051 , H01L2924/01057 , H01L2924/01068 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/10158 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2224/85186 , H01L2224/45099 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/4554
摘要： A variety of non-rectangular IC chips having a stepped or modified periphery or edge profile including one or more recessed or indented peripheral regions are provided for incorporation in modified package configurations, single chip packages and multi-chip assemblies, both stacked and/or planar. In the planar configurations, the recessed regions may be utilized, in cooperation with another appropriately sized IC chip, to increase the packing density of the resulting device. Similarly, in the stacked configuration, the recessed regions may be utilized to provide access to bond pads of lower chips and thereby reduce the need for spacers or peripheral thinning techniques and thereby improve the strength of the resulting assembly and/or reduce the overall height of the stacked structure.
摘要翻译：提供了具有包括一个或多个凹陷或凹入周边区域的阶梯状或改进的周边或边缘轮廓的各种非矩形IC芯片，用于结合到改进的封装结构，单个芯片封装和多芯片组件中，堆叠和/或平面。在平面构造中，可以与另一适当尺寸的IC芯片配合使用凹陷区域，以增加所得器件的封装密度。类似地，在堆叠构造中，凹陷区域可以用于提供对下部芯片的接合焊盘的访问，从而减少对间隔件或外围变薄技术的需要，从而提高所得组件的强度和/或降低总体高度堆叠结构。

74. 发明申请

US20050170646A1 Use of multiple etching steps to reduce lateral etch undercut 有权
标题翻译：使用多个蚀刻步骤来减少横向蚀刻底切
公开(公告)号：US20050170646A1
公开(公告)日：2005-08-04
申请号：US10772932
申请日：2004-02-04
申请人： Chunchieh Huang , Chia-Shun Hsiao , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel Wang
发明人： Chunchieh Huang , Chia-Shun Hsiao , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel Wang
IPC分类号： H01L21/44 , H01L21/8247 , H01L27/105 , H01L27/115
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11539
摘要： In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.
摘要翻译：在集成电路制造中，使用具有侧向分量的蚀刻。例如，蚀刻可以是各向同性的。在层（160）的各向同性蚀刻之前，执行相同层的另一蚀刻。这种其他蚀刻可以是各向异性的。该蚀刻攻击通过各向同性蚀刻形成的与特征相邻的层的部分（160×2）。该部分被各向异性蚀刻完全或部分地去除。然后，各向同性蚀刻掩模（420）被形成为延伸超过经过各向异性蚀刻的部分的位置的特征。如果完全去除该部分，则各向同性蚀刻掩模可以完全密封要在该部分侧面上形成的特征，因此不会发生横向蚀刻。如果该部分仅部分被去除，则横向底切将被阻碍，因为在各向同性蚀刻掩模下的特征的通过将变窄。

75. 发明授权

US09420591B2 Method and apparatus for reconfiguring control channel in wireless communication system 有权
标题翻译：无线通信系统中重新配置控制信道的方法和装置
公开(公告)号：US09420591B2
公开(公告)日：2016-08-16
申请号：US13098670
申请日：2011-05-02
申请人： Jung-Su Han , Hi-Chan Moon , Jun-Sung Lim , Jin-Ho Kim
发明人： Jung-Su Han , Hi-Chan Moon , Jun-Sung Lim , Jin-Ho Kim
IPC分类号： H04J4/00 , H04L5/00 , H04W72/08 , H04W16/14
CPC分类号： H04W72/082 , H04L5/001 , H04L5/0053 , H04L5/0096 , H04W16/14
摘要： A method for receiving control information by a User Equipment (UE) in a wireless communication system is provided. The method includes monitoring channel quality of a control channel, determining whether reconfiguration of the control channel is needed, based on the channel quality of the control channel, if the reconfiguration of the control channel is needed, requesting an evolved Node B (eNB) to reconfigure the control channel, and receiving the control information through the reconfigured control channel.
摘要翻译：提供了一种用于在无线通信系统中由用户设备（UE）接收控制信息的方法。该方法包括监视控制信道的信道质量，基于控制信道的信道质量来确定是否需要重配置控制信道，如果需要重新配置控制信道，则请求演进节点B（eNB）重新配置控制信道，并通过重新配置的控制信道接收控制信息。

76. 发明授权

US09159958B2 Organic light emitting display device 有权
标题翻译：有机发光显示装置
公开(公告)号：US09159958B2
公开(公告)日：2015-10-13
申请号：US13339075
申请日：2011-12-28
申请人： Il Jeon , Jin-Ho Kim
发明人： Il Jeon , Jin-Ho Kim
IPC分类号： G02F1/1335 , H01L51/52 , G02B5/30 , H01L27/32
CPC分类号： H01L51/5281 , G02B5/3016 , H01L27/3211
摘要： Disclosed is an organic light emitting display device to prevent deterioration of visibility caused by reflection of incident light and color transition at high viewing angle, and improve transmittance, the organic light emitting display device includes an organic light emitting display panel, and an antireflective member adhered to an outer surface of the organic light emitting display panel, the antireflective member including a reactive liquid crystal layer and a polarizer film which are laminated in this order, wherein the reactive liquid crystal layer has a λ/4 retardation with respect to a transmitted light of the polarizer film.
摘要翻译：公开了一种有机发光显示装置，用于防止由于入射光的反射和高视角的颜色变化引起的可见度的劣化，并且提高透射率，有机发光显示装置包括有机发光显示面板和附着的防反射构件涉及有机发光显示面板的外表面，该防反射构件包括依次层叠的反应性液晶层和偏振膜，其中反应性液晶层相对于透射光具有λ/ 4延迟的偏光膜。

77. 发明授权

US08929118B2 Stacked memory device having inter-chip connection unit, memory system including the same, and method of compensating for delay time of transmission line 有权
标题翻译：具有芯片间连接单元的堆叠存储器件，包括其的存储器系统以及补偿传输线路的延迟时间的方法
公开(公告)号：US08929118B2
公开(公告)日：2015-01-06
申请号：US13080061
申请日：2011-04-05
申请人： Chi-Sung Oh , Jin-Ho Kim , Ho-Cheol Lee , Uk-Song Kang , Hoon Lee
发明人： Chi-Sung Oh , Jin-Ho Kim , Ho-Cheol Lee , Uk-Song Kang , Hoon Lee
IPC分类号： G11C5/06 , G11C5/02 , G11C7/10
CPC分类号： G11C7/10 , G11C5/02 , G11C7/1048
摘要： A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a second signal of the second transmission line. The stacked semiconductor memory device further includes a second memory chip stacked over the first memory chip, an inter-chip connection unit electrically coupled between the second memory chip and the first transmission line of the first memory chip, and a dummy inter-chip connection unit electrically coupled to the second transmission line of the first memory chip and electrically isolated from the second memory chip.
摘要翻译：提供一种叠层半导体存储器件，其包括第一存储器芯片，该第一存储器芯片包括第一传输线，第二传输线和被配置为对第一传输线的第一信号执行逻辑运算的逻辑电路和第二传输线的第二信号传输线。层叠半导体存储器件还包括堆叠在第一存储器芯片上的第二存储器芯片，电连接在第二存储器芯片和第一存储器芯片的第一传输线之间的芯片间连接单元，以及虚拟芯片间连接单元电耦合到第一存储器芯片的第二传输线并且与第二存储器芯片电隔离。

78. 发明授权

US08362624B2 Multi-chip package and method of manufacturing thereof 失效
标题翻译：多芯片封装及其制造方法
公开(公告)号：US08362624B2
公开(公告)日：2013-01-29
申请号：US13230052
申请日：2011-09-12
申请人： Tae-Ho Kang , Jin-Ho Kim , Bo-Seong Kim
发明人： Tae-Ho Kang , Jin-Ho Kim , Bo-Seong Kim
IPC分类号： H01L23/48 , H01L23/02 , H01L21/00
CPC分类号： H01L24/85 , H01L23/3135 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L25/03 , H01L25/0657 , H01L25/50 , H01L2224/05554 , H01L2224/16225 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/49175 , H01L2224/73204 , H01L2224/73265 , H01L2224/8314 , H01L2224/838 , H01L2224/85138 , H01L2224/92247 , H01L2225/0651 , H01L2225/06517 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/0665 , H01L2924/07802 , H01L2924/10161 , H01L2924/10253 , H01L2924/15787 , H01L2924/181 , H01L2924/18161 , H01L2224/78 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： Provided are a multi-chip package and a method of manufacturing the same, which can facilitate wire bonding even when an upper chip is larger than a lower chip or overhangs a lower chip. A multi-chip package includes a substrate having first and second bonding pads on a top surface thereof, a first chip connected to the first bonding pads on the substrate, an insulating layer formed on the substrate so as to surround lateral surfaces of the first chip, a set of openings formed in the insulating layer so as to expose the second bonding pads, and a second chip formed on the insulating layer and the first chip, the second chip having a larger area than the first chip and connected to the second bonding pads using wires that pass through the second openings.
摘要翻译：提供一种多芯片封装及其制造方法，即使当上芯片大于下芯片或悬垂下芯片时，也可以促进引线键合。一种多芯片封装，包括在其顶表面上具有第一和第二焊盘的基板，与基板上的第一焊盘连接的第一芯片，形成在基板上以围绕第一芯片的侧表面的绝缘层，形成在所述绝缘层中以露出所述第二接合焊盘的一组开口，以及形成在所述绝缘层和所述第一芯片上的第二芯片，所述第二芯片具有比所述第一芯片更大的面积并且连接到所述第二接合垫使用穿过第二开口的线。

79. 发明授权

US08315218B2 Method for supporting route optimization in 6LoWPAN based MANEMO environment 有权
标题翻译：支持基于6LoWPAN的MANEMO环境中路由优化的方法
公开(公告)号：US08315218B2
公开(公告)日：2012-11-20
申请号：US12702751
申请日：2010-02-09
申请人： Jin-Hyoung Kim , Sun-Gi Kim , Dae-Hyung Kwon , Choong-Seon Hong , Jin-Ho Kim , Byung-Goo Choi
发明人： Jin-Hyoung Kim , Sun-Gi Kim , Dae-Hyung Kwon , Choong-Seon Hong , Jin-Ho Kim , Byung-Goo Choi
IPC分类号： H04W4/00
CPC分类号： H04W36/385 , Y02D70/144 , Y02D70/22
摘要： A method is provided for registering a mobile router in an Internet Protocol version 6 over Low power Wireless Personal Area Network (6LoWPAN) network. The mobile router detects movement into a wireless network through the reception of a beacon message, and sends a Router Solicitation (RS) message requesting registration in the wireless network to a gateway. The gateway acquires an address of the mobile router from the RS message, stores the acquired address, assigns a new address to be used in the wireless network to the mobile router, and sends a Router Advertisement (RA) message with assigned address information and gateway address information, to the mobile router. The mobile router acquires the assigned address information and the gateway address information from the RA message.
摘要翻译：提供了一种用于通过低功率无线个人区域网（6LoWPAN）网络在互联网协议版本6中注册移动路由器的方法。移动路由器通过接收信标消息来检测到无线网络的移动，并且向无线网络发送请求在无线网络中注册的路由器请求（RS）消息。网关从RS消息中获取移动路由器的地址，存储获取的地址，将无线网络中要使用的新地址分配给移动路由器，并发送具有分配的地址信息和网关的路由器通告（RA）消息地址信息，到移动路由器。移动路由器从RA消息获取分配的地址信息和网关地址信息。

80. 发明授权

US08054420B2 Liquid crystal display device and method of fabricating the same 有权
标题翻译：液晶显示装置及其制造方法
公开(公告)号：US08054420B2
公开(公告)日：2011-11-08
申请号：US12683756
申请日：2010-01-07
申请人： Sung-Soo Chang , Woo-Hyun Kim , Jin-Ho Kim
发明人： Sung-Soo Chang , Woo-Hyun Kim , Jin-Ho Kim
IPC分类号： G02F1/1335 , G02F1/13
CPC分类号： G02F1/133555 , G02F1/133504 , G02F1/133514
摘要： A liquid crystal display device includes an array substrate having reflective and transmissive regions in a pixel region, wherein the array substrate includes a reflective electrode corresponding to the reflective region and a pixel electrode on a first substrate. A color filter substrate defines the reflective region and the transmissive region in the pixel region. The color filter substrate includes a color filter with first and second portions that correspond to the respective transmissive and reflective regions on a second substrate. The thickness of the second portion is less than a thickness of the first portion. The combined thickness of the scatter and the thickness of the second portion is greater than the thickness of the first portion; and a liquid crystal layer between the array and color filter substrates.
摘要翻译：一种液晶显示装置，具备在像素区域具有反射和透射区域的阵列基板，其中阵列基板包括对应于反射区域的反射电极和在第一基板上的像素电极。滤色器基板限定像素区域中的反射区域和透射区域。滤色器基板包括滤色器，滤色器具有对应于第二基板上的相应透射和反射区域的第一和第二部分。第二部分的厚度小于第一部分的厚度。第二部分的散射和厚度的组合厚度大于第一部分的厚度; 以及阵列和滤色器基板之间的液晶层。

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