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1. 发明授权

US09053813B2 Method and apparatus for refreshing and data scrubbing memory device 有权
标题翻译：用于刷新和数据擦除存储器件的方法和装置
公开(公告)号：US09053813B2
公开(公告)日：2015-06-09
申请号：US13241205
申请日：2011-09-23
申请人： Uk-Song Kang , Hak-Soo Yu , Chul-Woo Park
发明人： Uk-Song Kang , Hak-Soo Yu , Chul-Woo Park
IPC分类号： G06F13/00 , G06F13/28 , G11C11/406 , G06F11/10 , G11C29/52 , G11C11/40 , G11C29/04
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/0644 , G06F3/0652 , G06F3/0679 , G06F11/106 , G11C11/40 , G11C11/406 , G11C11/40611 , G11C11/40618 , G11C11/40622 , G11C29/52 , G11C2029/0409 , G11C2029/0411
摘要： At least one refresh without scrubbing is performed on a corresponding portion of the memory device with a first frequency. In addition, at least one refresh with scrubbing is performed on a corresponding portion of the memory device with a second frequency less than the first frequency. Accordingly, refresh operations with data scrubbing are performed to prevent data error accumulation. Furthermore, refresh operations without data scrubbing are also performed to reduce undue power consumption from the data scrubbing.
摘要翻译：在具有第一频率的存储器件的相应部分上执行至少一次不进行擦洗的刷新。此外，具有小于第一频率的第二频率对存储器件的相应部分执行至少一次刷洗刷新。因此，执行具有数据擦除的刷新操作以防止数据错误累积。此外，还执行没有数据擦除的刷新操作，以减少数据擦除的不必要的功耗。

2. 发明申请

US20140189215A1 MEMORY MODULES AND MEMORY SYSTEMS 有权
标题翻译：存储器模块和存储器系统
公开(公告)号：US20140189215A1
公开(公告)日：2014-07-03
申请号：US14083033
申请日：2013-11-18
申请人： UK-SONG KANG , Chul-Woo Park , Hak-Soo Yu , Jong-Pil Son
发明人： UK-SONG KANG , Chul-Woo Park , Hak-Soo Yu , Jong-Pil Son
IPC分类号： G11C11/406 , G06F12/02
CPC分类号： G11C11/40607 , G11C11/40603 , G11C11/40622 , G11C11/4087
摘要： A memory module includes a plurality of memory devices and a buffer chip. The buffer chip manages the memory devices. The buffer chip includes a refresh control circuit that groups a plurality of memory cell rows of the memory devices into a plurality of groups according to a data retention time of tire memory cell rows. The buffer chip selectively refreshes each of the plurality of groups in each of a plurality of refresh time regions that are periodically repeated and applies respective refresh periods to the plurality of groups, respectively.
摘要翻译：存储器模块包括多个存储器件和缓冲器芯片。缓冲芯片管理存储器件。缓冲芯片包括根据轮胎存储单元行的数据保持时间将存储器件的多个存储单元行分组成多个组的刷新控制电路。缓冲器芯片有选择地刷新周期性地重复的多个刷新时间区域中的每一个中的多个组中的每一个，并将各个刷新周期分别应用于多个组。

3. 发明授权

US08693269B2 Memory device for managing timing parameters 有权
标题翻译：用于管理时序参数的存储器
公开(公告)号：US08693269B2
公开(公告)日：2014-04-08
申请号：US13569636
申请日：2012-08-08
申请人： Uk-song Kang , Chul-woo Park , Hak-soo Yu , Hong-sun Hwang
发明人： Uk-song Kang , Chul-woo Park , Hak-soo Yu , Hong-sun Hwang
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C7/1009 , G11C11/40611 , G11C11/4093
摘要： A method of performing write operations in a memory device including a plurality of bank is performed. Each bank includes two or more sub-banks including at least a first sub-bank and a second sub-bank. The method comprises: performing a first row cycle for writing to a first word line of the first sub-bank, the first row cycle including a plurality of first sub-periods, each sub-period for performing a particular action; and performing a second row cycle for writing to a first word line of the second sub-bank, the second row cycle including a plurality of second sub-periods of the same type as the plurality of first sub-periods. The first row cycle overlaps with the second row cycle, and a first type sub-period of the first sub-periods overlaps with a second type sub-period of the second sub-periods, the first type and second type being different types.
摘要翻译：执行在包括多个存储体的存储器件中执行写入操作的方法。每个银行包括至少包括第一子银行和第二子银行的两个或多个子行。该方法包括：执行第一行周期以写入第一子行的第一字线，第一行周期包括多个第一子周期，用于执行特定动作的每个子周期; 以及执行第二行周期以写入所述第二子行的第一字线，所述第二行周期包括与所述多个第一子周期相同类型的多个第二子周期。第一行周期与第二行周期重叠，第一子周期的第一类型子周期与第二子周期的第二类型子周期重叠，第一类型和第二类型是不同类型。

4. 发明授权

US08369123B2 Stacked memory module and system 有权
标题翻译：堆叠内存模块和系统
公开(公告)号：US08369123B2
公开(公告)日：2013-02-05
申请号：US13535363
申请日：2012-06-28
申请人： Uk-Song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
发明人： Uk-Song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G11C5/025 , G11C5/04 , G11C8/12 , G11C8/18 , G11C29/14 , H01L23/481 , H01L25/0657 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.
摘要翻译：三维存储器模块和系统形成有在主芯片上堆叠的至少一个从芯片。通过半导体通孔（TSV）通过主芯片和从芯片中的至少一个形成。主芯片包括用于增加存储器模块/系统容量的存储器核心。此外，公开了形成有效布线的三维存储器模块/系统的容量组织，用于形成三维存储器模块/系统的多个存储器组，多个存储体组和/或多个等级。

5. 发明申请

US20120059984A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120059984A1
公开(公告)日：2012-03-08
申请号：US13209026
申请日：2011-08-12
申请人： Uk-song Kang , Young-hyun Jun , Joo-sun Choi
发明人： Uk-song Kang , Young-hyun Jun , Joo-sun Choi
IPC分类号： G06F12/10 , G11C7/00 , H01L23/48
CPC分类号： H01L25/18 , G11C5/02 , G11C7/10 , H01L2224/48091 , H01L2225/06544 , H01L2924/00014
摘要： A semiconductor package is disclosed. The semiconductor package includes a package interface, a stack of semiconductor chips, a plurality of stacks of through substrate vias, and an interface circuit. The package interface includes at least a first pair of terminals. Each stack of through substrate vias includes plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip. The interface circuit includes an input connected to the first pair of terminals to receive a differential signal providing first information, and includes an output to provide an output signal including the first information in a single-ended signal format to at least one of the plurality of stacks of through substrate vias.
摘要翻译：公开了半导体封装。半导体封装包括封装接口，半导体芯片堆叠，多个通过衬底通孔的堆叠以及接口电路。封装接口包括至少第一对端子。每个通过衬底通孔的堆叠包括相应的半导体芯片的多个通过衬底通孔，每个穿过衬底经由电连接到直接相邻的半导体芯片的贯穿衬底通孔。接口电路包括连接到第一对终端的输入端，以接收提供第一信息的差分信号，并且包括输出，以将包括单端信号格式的第一信息的输出信号提供给多个通过衬底通孔的堆叠。

6. 发明申请

US20110292708A1 3D SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20110292708A1
公开(公告)日：2011-12-01
申请号：US13115501
申请日：2011-05-25
申请人： Uk-song Kang , Dong-hyeon Jang , Seong-jin Jang , Hoon Lee , Jin-ho Kim , Nam-seog Kim , Byung-sik Moon , Woo-dong Lee
发明人： Uk-song Kang , Dong-hyeon Jang , Seong-jin Jang , Hoon Lee , Jin-ho Kim , Nam-seog Kim , Byung-sik Moon , Woo-dong Lee
IPC分类号： G11C5/06 , H01L21/66 , H01L21/50 , G11C8/18 , H01L23/48
CPC分类号： H01L23/481 , G11C5/06 , G11C8/18 , H01L22/32 , H01L24/05 , H01L24/16 , H01L24/17 , H01L24/73 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/05572 , H01L2224/16145 , H01L2224/16146 , H01L2224/17051 , H01L2224/17515 , H01L2224/73204 , H01L2224/94 , H01L2225/06513 , H01L2225/06544 , H01L2225/06596 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01047 , H01L2924/01055 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2224/05552 , H01L2924/00
摘要： A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.
摘要翻译：三维（3D）半导体器件可以包括一堆芯片，包括主芯片和一个或多个从芯片。从芯片的I / O连接不需要连接到主板上的通道，只有主芯片的电极焊盘可以连接到通道。只有主芯片可以为通道提供负载。可以在堆叠相同类型的半导体芯片的半导体器件的数据输入路径，数据输出路径，地址/命令路径和/或时钟路径上设置贯穿衬底通孔（TSV）边界。

7. 发明申请

US20110057310A1 SEMICONDUCTOR PACKAGE HAVING MEMORY DEVICES STACKED ON LOGIC DEVICE 有权
标题翻译：具有堆叠在逻辑设备上的存储器件的半导体封装
公开(公告)号：US20110057310A1
公开(公告)日：2011-03-10
申请号：US12946141
申请日：2010-11-15
申请人： Uk-Song KANG
发明人： Uk-Song KANG
IPC分类号： H01L23/498
CPC分类号： G11C5/025 , G11C5/02 , G11C5/063 , H01L25/0657 , H01L25/18 , H01L2224/05573 , H01L2224/05655 , H01L2224/05666 , H01L2224/05681 , H01L2224/05684 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06572 , H01L2924/15311 , H01L2924/15321 , H01L2924/00014
摘要： A semiconductor package includes a base substrate, a logic device with a serializer/deserializer (SerDes), a plurality of odd memory devices disposed on a lower surface of the logic device and operatively stack-connected with the SerDes, and a plurality of even memory devices disposed on an upper surface of the logic device and operatively stack-connected with the SerDes, such that the plurality of odd memory devices and the plurality of even memory devices are connected in parallel by the SerDes.
摘要翻译：半导体封装包括基底基板，具有串行器/解串器（SerDes）的逻辑器件，设置在逻辑器件的下表面上并与SerDes可操作地堆叠连接的多个奇数存储器件，以及多个偶数存储器设置在逻辑设备的上表面上并与SerDes可操作地堆叠连接的设备，使得多个奇数存储器件和多个偶数存储器件由SerDes并联连接。

8. 发明授权

US07894282B2 Dynamic random access memory device and method of determining refresh cycle thereof 失效
标题翻译：动态随机存取存储器件及其刷新周期的确定方法
公开(公告)号：US07894282B2
公开(公告)日：2011-02-22
申请号：US12329880
申请日：2008-12-08
申请人： Suk-Soo Pyo , Uk-Song Kang
发明人： Suk-Soo Pyo , Uk-Song Kang
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C11/408 , G11C2207/104 , G11C2211/4061
摘要： Provided are a dynamic random access memory device having reduced power consumption and a method of determining a refresh cycle of the dynamic random access memory device. The method includes: selecting one or more monitoring bits during first through n-th self refresh cycles, where “n” is a natural number equal to or greater than one; detecting whether the monitoring bits have errors during (n+1)-th through m-th self refresh cycles, where “m” is a natural number equal to or greater than n+1; and adjusting an (m+1)-th self refresh cycle according to whether the monitoring bits have errors.
摘要翻译：提供了具有降低的功耗的动态随机存取存储器件以及确定动态随机存取存储器件的刷新周期的方法。该方法包括：在第一至第n自刷新周期期间选择一个或多个监视位，其中“n”是等于或大于1的自然数; 检测在第（n + 1）至第m自刷新周期期间监视比特是否具有错误，其中“m”是等于或大于n + 1的自然数; 以及根据监视位是否具有错误来调整第（m + 1）个自刷新周期。

9. 发明申请

US20100020583A1 Stacked memory module and system 有权
标题翻译：堆叠内存模块和系统
公开(公告)号：US20100020583A1
公开(公告)日：2010-01-28
申请号：US12454064
申请日：2009-05-12
申请人： Uk-Song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
发明人： Uk-Song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： G11C5/02 , G11C5/025 , G11C5/04 , G11C8/12 , G11C8/18 , G11C29/14 , H01L23/481 , H01L25/0657 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.
摘要翻译：三维存储器模块和系统形成有在主芯片上堆叠的至少一个从芯片。通过半导体通孔（TSV）通过主芯片和从芯片中的至少一个形成。主芯片包括用于增加存储器模块/系统容量的存储器核心。此外，公开了形成有效布线的三维存储器模块/系统的容量组织，用于形成三维存储器模块/系统的多个存储器组，多个存储体组和/或多个等级。

10. 发明申请

US20090168571A1 DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF DETERMINING REFRESH CYCLE THEREOF 失效
标题翻译：动态随机访问存储器件及其确定周期的方法
公开(公告)号：US20090168571A1
公开(公告)日：2009-07-02
申请号：US12329880
申请日：2008-12-08
申请人： Suk-Soo Pyo , Uk-Song Kang
发明人： Suk-Soo Pyo , Uk-Song Kang
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C11/408 , G11C2207/104 , G11C2211/4061
摘要： Provided are a dynamic random access memory device having reduced power consumption and a method of determining a refresh cycle of the dynamic random access memory device. The method includes: selecting one or more monitoring bits during first through n-th self refresh cycles, where “n” is a natural number equal to or greater than one; detecting whether the monitoring bits have errors during (n+1)-th through m-th self refresh cycles, where “m” is a natural number equal to or greater than n+1; and adjusting an (m+1)-th self refresh cycle according to whether the monitoring bits have errors.
摘要翻译：提供了具有降低的功耗的动态随机存取存储器件以及确定动态随机存取存储器件的刷新周期的方法。该方法包括：在第一至第n自刷新周期期间选择一个或多个监视位，其中“n”是等于或大于1的自然数; 检测在第（n + 1）至第m自刷新周期期间监视比特是否具有错误，其中“m”是等于或大于n + 1的自然数; 以及根据监视位是否具有错误来调整第（m + 1）个自刷新周期。

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