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    • 3. 发明授权
    • Display device and method
    • 显示设备和方法
    • US09147376B2
    • 2015-09-29
    • US13149388
    • 2011-05-31
    • Yong Jae Lee
    • Yong Jae Lee
    • G09G5/00G09G3/36G09G3/20
    • G09G5/008G09G3/20G09G3/3688G09G2310/027G09G2310/08G09G2320/0223G09G2370/08
    • A display device and method are provided. The display device includes a timing controller configured to insert a clock between data and transmit the data in which the clock has been inserted, transmission lines configured to transfer the data in which the clock has been inserted, and data driver integrated circuits (ICs) configured to receive the data in which the clock has been inserted, separate the clock from the data, and drive data lines of a liquid crystal panel on the basis of the clock and the data. The timing controller includes a phase-locked loop (PLL) including an oscillator and an inductor-capacitor (LC) resonant circuit, and a reset signal generator configured to generate a reset signal causing the PLL to start coarse frequency tuning when initial power is applied or a frequency of an applied input clock changes.
    • 提供了一种显示装置和方法。 显示装置包括定时控制器,其被配置为在数据之间插入时钟并发送其中已经插入时钟的数据,配置成传送其中插入时钟的数据的传输线以及配置的数据驱动器集成电路(IC) 为了接收插入时钟的数据,将时钟与数据分开,并根据时钟和数据驱动液晶面板的数据线。 定时控制器包括一个包括一个振荡器和一个电感 - 电容(LC)谐振电路的锁相环(PLL),以及一个复位信号发生器,被配置为产生复位信号,使复位信号在初始电源被施加时使PLL开始粗调频率调谐 或施加的输入时钟的频率变化。
    • 4. 发明申请
    • METHOD FOR STORING MOTION PREDICTION-RELATED INFORMATION IN INTER PREDICTION METHOD, AND METHOD FOR OBTAINING MOTION PREDICTION-RELATED INFORMATION IN INTER PREDICTION METHOD
    • 用于存储互动预测方法中的运动预测相关信息的方法,以及用于在相互预测方法中获取运动预测相关信息的方法
    • US20140185948A1
    • 2014-07-03
    • US14115568
    • 2012-05-31
    • Chung Ku YieYong Jae LeeHui Kim
    • Chung Ku YieYong Jae LeeHui Kim
    • H04N19/51
    • H04N19/172H04N19/109H04N19/122H04N19/139H04N19/146H04N19/176H04N19/51H04N19/513H04N19/517
    • Provided are methods for storing and obtaining motion prediction-related information in inter motion prediction method. The method for storing the motion prediction-related information may include obtaining size information of prediction unit of a picture, and adaptively storing motion prediction-related information of the picture on the basis of the obtained size information of prediction unit of the picture. The method for obtaining the motion prediction-related information may include searching a first temporal motion prediction candidate block to obtain first temporal motion prediction-related information in the first temporal motion prediction candidate block, and searching a second temporal motion prediction candidate block to obtain second temporal motion prediction-related information in the second temporal motion prediction candidate block. Thus, a memory space for storing the motion prediction-related information may be efficiently utilized. Also, an error between the prediction block and an original block may be reduced to improve coding efficiency.
    • 提供了用于在帧间运动预测方法中存储和获得运动预测相关信息的方法。 用于存储运动预测相关信息的方法可以包括获得图像的预测单元的大小信息,并且基于获得的图像的预测单元的尺寸信息自适应地存储图像的运动预测相关信息。 用于获得运动预测相关信息的方法可以包括搜索第一时间运动预测候选块以获得第一时间运动预测候选块中的第一时间运动预测相关信息,并且搜索第二时间运动预测候选块以获得第二时间运动预测候选块 第二时间运动预测候选块中的时间运动预测相关信息。 因此,可以有效地利用用于存储运动预测相关信息的存储空间。 此外,可以减少预测块和原始块之间的误差,以提高编码效率。
    • 5. 发明授权
    • PLL, display using the same, and method for timing controller to generate clock using the same
    • PLL,使用相同的显示器,以及定时控制器生成使用该时钟的时钟的方法
    • US08547317B2
    • 2013-10-01
    • US13110523
    • 2011-05-18
    • Yong Jae Lee
    • Yong Jae Lee
    • G09G3/36
    • G09G3/3611G09G2370/08H03J2200/10H03L7/095H03L7/185
    • Provided are a phase-locked loop (PLL) receiving an input clock and generating a clock, a display using the PLL, and a method for a timing controller to generate a clock using the PLL. The display includes a timing controller configured to generate a first clock using a PLL, insert the first clock into data, and transmit the data into which the first clock is inserted, transmission lines configured to transfer the data into which the first clock is inserted, and data-driver integrated circuits (ICs) configured to receive the data into which the first clock is inserted, separate the first clock from the data, and drive data lines of a liquid crystal panel on the basis of the first clock and the data. The PLL includes a phase detector configured to generate a DC error corresponding to a phase difference between an input clock and the first clock, a plurality of voltage-controlled oscillators (VCOs), a VCO selector configured to select a VCO having a frequency operating range, which is a range from the highest oscillation frequency of the VCO to the lowest oscillation frequency, including a frequency of the first clock from among the plurality of VCOs with reference to the DC error, and an inductor/capacitor (LC) resonant circuit connected with the selected VCO, including a plurality of fixed capacitors, and configured to perform coarse frequency tuning of the selected VCO.
    • 提供了接收输入时钟并产生时钟的锁相环(PLL),使用PLL的显示器以及使用PLL来产生时钟的定时控制器的方法。 显示器包括定时控制器,其被配置为使用PLL生成第一时钟,将第一时钟插入到数据中,并且发送插入有第一时钟的数据,被配置为传送插入有第一时钟的数据的传输线, 以及被配置为接收插入有第一时钟的数据的数据驱动器集成电路(IC),将第一时钟与数据分开,并且基于第一时钟和数据驱动液晶面板的数据线。 PLL包括相位检测器,被配置为产生对应于输入时钟和第一时钟之间的相位差的DC误差,多个压控振荡器(VCO),VCO选择器,被配置为选择具有频率工作范围的VCO ,其是从VCO的最高振荡频率到最低振荡频率的范围,包括参考DC误差从多个VCO中的第一时钟的频率,以及连接的电感器/电容器(LC)谐振电路 所选择的VCO包括多个固定电容器,并被配置为对所选择的VCO进行粗略的频率调谐。
    • 6. 发明申请
    • COMPATIBLE OPTICAL PICKUP AND OPTICAL INFORMATION STORAGE MEDIUM APPARATUS USING THE SAME
    • 相容的光学拾取和光信息存储介质
    • US20120106311A1
    • 2012-05-03
    • US13282635
    • 2011-10-27
    • Ui-yol KimYong-Jae Lee
    • Ui-yol KimYong-Jae Lee
    • G11B7/1353
    • G11B7/1353G11B7/0903G11B7/131G11B7/1395G11B2007/0006
    • An optical pickup and an information storage medium system using the same. The optical pickup includes a light source that emits light having a plurality of different wavelengths. The optical pickup includes a diffraction device having a plurality of diffraction patterns corresponding to the plurality of different wavelengths to divide the light incident from the light source unit into main light and sub light. The optical pickup further includes a photo-detector having a first main light reception unit that receives the main light and a first sub light reception unit that receives the sub light so as to detect an information signal and/or an error signal by receiving reflected light. The first sub light reception unit of the photo-detector is shaped so as to reduce reception of noise sub light due to diffraction based on an undesired diffraction pattern of sub light generated the diffraction device.
    • 一种光学拾取器和使用该拾取器的信息存储介质系统。 光学拾取器包括发射具有多个不同波长的光的光源。 光拾取器包括衍射装置,其具有对应于多个不同波长的多个衍射图案,以将从光源单元入射的光分成主光和副光。 光拾取器还包括具有接收主光的第一主光接收单元和接收子光的第一子光接收单元的光检测器,以便通过接收反射光来检测信息信号和/或误差信号 。 光检测器的第一子光接收单元被成形为基于由衍射装置产生的副光的不想要的衍射图来减少由衍射引起的噪声子光的接收。
    • 8. 发明申请
    • PLL, DISPLAY USING THE SAME, AND METHOD FOR TIMING CONTROLLER TO GENERATE CLOCK USING THE SAME
    • PLL,使用该显示器的显示器,以及用于使控制器生成使用该时钟的时钟的方法
    • US20110292011A1
    • 2011-12-01
    • US13110523
    • 2011-05-18
    • Yong Jae LEE
    • Yong Jae LEE
    • G09G3/36G09G5/00H03L7/08
    • G09G3/3611G09G2370/08H03J2200/10H03L7/095H03L7/185
    • Provided are a phase-locked loop (PLL) receiving an input clock and generating a clock, a display using the PLL, and a method for a timing controller to generate a clock using the PLL. The display includes a timing controller configured to generate a first clock using a PLL, insert the first clock into data, and transmit the data into which the first clock is inserted, transmission lines configured to transfer the data into which the first clock is inserted, and data-driver integrated circuits (ICs) configured to receive the data into which the first clock is inserted, separate the first clock from the data, and drive data lines of a liquid crystal panel on the basis of the first clock and the data. The PLL includes a phase detector configured to generate a DC error corresponding to a phase difference between an input clock and the first clock, a plurality of voltage-controlled oscillators (VCOs), a VCO selector configured to select a VCO having a frequency operating range, which is a range from the highest oscillation frequency of the VCO to the lowest oscillation frequency, including a frequency of the first clock from among the plurality of VCOs with reference to the DC error, and an inductor/capacitor (LC) resonant circuit connected with the selected VCO, including a plurality of fixed capacitors, and configured to perform coarse frequency tuning of the selected VCO.
    • 提供了接收输入时钟并产生时钟的锁相环(PLL),使用PLL的显示器以及使用PLL来产生时钟的定时控制器的方法。 显示器包括定时控制器,其被配置为使用PLL生成第一时钟,将第一时钟插入到数据中,并且发送插入有第一时钟的数据,被配置为传送插入有第一时钟的数据的传输线, 以及被配置为接收插入有第一时钟的数据的数据驱动器集成电路(IC),将第一时钟与数据分开,并且基于第一时钟和数据驱动液晶面板的数据线。 PLL包括相位检测器,被配置为产生对应于输入时钟和第一时钟之间的相位差的DC误差,多个压控振荡器(VCO),VCO选择器,被配置为选择具有频率工作范围的VCO ,其是从VCO的最高振荡频率到最低振荡频率的范围,包括参考DC误差从多个VCO中的第一时钟的频率,以及连接的电感器/电容器(LC)谐振电路 所选择的VCO包括多个固定电容器,并被配置为对所选择的VCO进行粗略的频率调谐。
    • 10. 发明申请
    • Data driving circuit, display apparatus, and data driving method
    • 数据驱动电路,显示装置和数据驱动方法
    • US20100156882A1
    • 2010-06-24
    • US12654354
    • 2009-12-17
    • Yong Jae Lee
    • Yong Jae Lee
    • G09G5/00H03K3/00
    • G09G3/20G09G3/2092G09G3/3614G09G3/3674G09G3/3685G09G2310/0267G09G2310/027G09G2310/0275G09G2330/06
    • Provided are a data driving circuit, a display device, and a data driving method. The data driving circuit includes a clock generator configured to generate a clock signal from clock information included in a reception signal including the clock information, mode information and a body, a sampler configured to sample the reception signal according to the clock signal to obtain the mode information and the body that includes at least one of control information and data, a signal controller configured to determine whether or not the body corresponds to the control information with reference to the mode information, and generate a control signal corresponding to the control information according to a result of the determination, and a data driver configured to generate a data signal corresponding to the data according to the control signal.
    • 提供了数据驱动电路,显示装置和数据驱动方法。 数据驱动电路包括时钟发生器,被配置为从包括时钟信息,模式信息和主体的接收信号中的时钟信息产生时钟信号,采样器被配置为根据时钟信号对接收信号进行采样以获得模式 信息和主体,其包括控制信息和数据中的至少一个;信号控制器,被配置为参照所述模式信息来确定所述主体对应于所述控制信息,并且根据所述控制信息生成与所述控制信息相对应的控制信号 所述确定的结果以及被配置为根据所述控制信号产生与所述数据相对应的数据信号的数据驱动器。