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71. 发明授权

US07488412B2 Honeycomb structural body, honeycomb filter, and method of manufacturing the structural body and the filter 有权
标题翻译：蜂窝结构体，蜂窝过滤器，以及结构体和过滤器的制造方法
公开(公告)号：US07488412B2
公开(公告)日：2009-02-10
申请号：US10482299
申请日：2002-06-18
申请人： Fumio Abe , Toshio Yamada
发明人： Fumio Abe , Toshio Yamada
IPC分类号： B01D53/34 , F01N3/28
CPC分类号： F01N3/2828 , B01D46/0024 , B01D46/0039 , B01D46/2422 , B01D46/2425 , B01D46/2429 , B01D46/2451 , B01D46/2455 , B01D46/2459 , B01D46/2466 , B01D46/247 , B01D46/2474 , B01D2046/2433 , B01D2046/2437 , B01D2046/2492 , B01D2046/2496 , B01J23/42 , B01J35/0006 , B01J35/04 , B01J37/0246 , B28B3/2636 , B28B3/269 , B29C47/0028 , B29C47/12 , B29L2031/60 , F01N3/0222 , F01N2330/30 , F01N2330/48 , H01M8/2435 , Y02P70/56 , Y02T10/20 , Y10T29/49345
摘要： There is disclosed a honeycomb structural body (1) comprising: a plurality of through channels (3) formed by a plurality of partition walls (2) in an axial direction. The honeycomb structural body (1) is constituted of a plurality of honeycomb sections (10, 11) formed of materials having different characteristics, and the plurality of honeycomb sections (10, 11) are directly bonded to and integrated with one another. According to the structure of this honeycomb structural body, different high performances can be fulfilled in accordance with requests for each honeycomb section. Additionally, there is not any local stress concentration by shape mismatch of each honeycomb section or presence of a bond material, and reliability at the time of use, and the like can be enhanced.
摘要翻译：公开了一种蜂窝结构体（1），包括：沿轴向由多个分隔壁（2）形成的多个通道（3）。蜂窝结构体（1）由具有不同特性的材料形成的多个蜂窝部（10,11）构成，多个蜂窝部（10,11）直接接合并一体化。根据该蜂窝结构体的结构，可以根据对每个蜂窝部的要求来实现不同的高性能。此外，不存在每个蜂窝部的形状不匹配或粘合材料的存在的局部应力集中，并且可以提高使用时的可靠性等。

72. 发明申请

US20080311340A1 HONEYCOMB STRUCTURE AND PRODUCTION METHOD THEREOF 审中-公开
标题翻译：蜂窝结构及其生产方法
公开(公告)号：US20080311340A1
公开(公告)日：2008-12-18
申请号：US12145210
申请日：2008-06-24
申请人： Yoshiyuki Kasai , Toshio Yamada , Shinichi Miwa , Mikio Makino
发明人： Yoshiyuki Kasai , Toshio Yamada , Shinichi Miwa , Mikio Makino
IPC分类号： B32B3/12
CPC分类号： B01D46/2474 , B01D46/2425 , B01D46/2429 , B01D46/244 , B01D46/2444 , B01D46/2459 , B01D46/2466 , B01D46/247 , B01D2046/2481 , B01D2046/2485 , B01D2046/2492 , B01D2046/2496 , B01J23/42 , B01J35/04 , C04B35/195 , C04B38/0006 , F01N3/0222 , F01N3/2828 , F01N2330/06 , F01N2330/30 , Y02T10/20 , Y10T428/24149
摘要： A honeycomb structure excellent in thermal dispersibility upon heating and being protected from damage due to thermal stress, and an efficient method for manufacturing the honeycomb structure. The structure is provided with porous partition walls, functioning as a filtration layer, through which exhaust gas flowing into the cells can flow out, and plugging portions. Additional plugging portions are further disposed in the open end portions to which the plugging portions are not disposed (unplugged open end portions) not so as to plug unplugged open end portions. Each cross-sectional shape of additional plugging portions in a direction perpendicular to the axial direction forms a predetermined pattern shape as a whole, and a barycenter of the pattern shape is located in almost the center of a cross section of a flow of the exhaust gas in a direction perpendicular to the axial direction.
摘要翻译：一种加热时的热分散性优异且不受热应力损伤的蜂窝结构体，以及蜂窝结构体的制造方法。该结构设置有作为过滤层的多孔分隔壁，通过该过滤层流入细胞的排气可以流出，并且堵塞部分。另外，在插入部未未设置的开放端部（未插入开口端部）中还设置有插塞部，插拔未插入开口端部。附加堵塞部分在垂直于轴向的方向上的每个横截面形状整体形成预定的图案形状，并且图案形状的重心位于废气流的横截面的几乎中心在垂直于轴向的方向上。

73. 发明授权

US07245521B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07245521B2
公开(公告)日：2007-07-17
申请号：US11169800
申请日：2005-06-30
申请人： Ryo Mori , Toshio Yamada , Tetsuya Muraya
发明人： Ryo Mori , Toshio Yamada , Tetsuya Muraya
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C11/412
摘要： The present invention provides a semiconductor integrated circuit device having an SRAM in which leak current is reduced. In an SRAM comprising a plurality of memory cells each constructed by a storage in which input and output terminals of two inverter circuits are cross-connected and a selection MOSFET provided between the storage and complementary bit lines and whose gate is connected to a word line, a substrate bias switching circuit is provided. In normal operation, the substrate bias switching circuit supplies a power source voltage to an N-type well in which a P-channel MOSFET of a memory cell is formed and supplies a ground potential of the circuit to a P-type well in which an N-channel MOSFET is formed. In the standby state, the substrate bias switching circuit supplies a predetermined voltage which is lower than the power source voltage and by which a PN junction between the N-type well and the source of the P-channel MOSFET is not forward biased to the N-type well, and supplies a predetermined voltage which is higher than the ground potential and by which a PN junction between the P-type well and the source of the N-channel MOSFET is not forward biased to the P-type well.
摘要翻译：本发明提供一种半导体集成电路器件，其具有泄漏电流降低的SRAM。在包括多个存储单元的SRAM中，每个存储单元由两个反相器电路的输入和输出端子交叉存储的存储器构成，以及设置在存储和互补位线之间并且其栅极连接到字线的选择MOSFET，提供了衬底偏置开关电路。在正常操作中，衬底偏置开关电路将电源电压提供给形成存储单元的P沟道MOSFET的N型阱，并将电路的接地电位提供给P型阱，其中，形成N沟道MOSFET。在待机状态下，衬底偏置开关电路提供低于电源电压的预定电压，并且N型阱和P沟道MOSFET的源极之间的PN结不被正向偏置到N 并且提供比地电位高的预定电压，并且P型阱和N沟道MOSFET的源极之间的PN结未被正向偏置到P型阱。

74. 发明授权

US06458946B1 Crystals of diuridine tetraphosphate or salt thereof, process for producing the crystals, and process for producing the compounds 有权
标题翻译：二氢吖啶四磷酸的晶体或其盐，晶体的制造方法，以及该化合物的制造方法
公开(公告)号：US06458946B1
公开(公告)日：2002-10-01
申请号：US09582642
申请日：2000-07-28
申请人： Hideaki Maeda , Toshio Yamada , Hiroshi Sato , Yutaka Noda
发明人： Hideaki Maeda , Toshio Yamada , Hiroshi Sato , Yutaka Noda
IPC分类号： C07H1904
CPC分类号： C07H19/10 , C07H21/02
摘要： The invention provides crystals of p1,P4-di(uridine 5′-) tetraphosphate or a salt thereof; a process for producing the crystals; and a process for producing P1,P4-di(uridine 5′-) tetraphosphate (U2P4) or a salt thereof from UMP serving as a starting material and by use of DPC and PPi, which process comprises at least one of the following treatment steps: (a) adding UMP diphenylphosphate (UMP-DPP) in divided portions during a step of reaction of UMP-DPP with a PPi-organic alkali salt; (b) carrying out reaction of UMP-DPP with a PPi-organic alkali salt in the presence of a base; and (c) further treating the synthesized U2P4 with an alkali. The crystals of U2P4 or a salt thereof obtained through the process according to the invention have high purity and stability and a less hygroscopicity as compared with a lyophilized product, to thereby serve as a useful raw material for preparing a pharmaceutical. The process for producing U2P4 or a salt thereof according to the invention realizes high yield and enables large-scale synthesis.
摘要翻译：本发明提供了p1，P4-二（尿苷5'-）四磷酸盐或其盐的晶体; 制造晶体的方法; 以及由作为起始原料的UMP生产P1，P4-二（尿苷5'-）四磷酸（U2P4）或其盐的方法，并且使用DPC和PPi，该方法包括以下处理步骤中的至少一个：（a）在UMP-DPP与PPi-有机碱盐反应的步骤期间，分份加入UMP二苯基磷酸酯（UMP-DPP）; （b）在碱的存在下进行UMP-DPP与PPi-有机碱盐的反应; 和（c）用碱进一步处理合成的U2P4。通过本发明的方法获得的U2P4或其盐的结晶与冻干产品相比具有高纯度和稳定性以及较少的吸湿性，从而用作制备药物的有用原料。根据本发明的制备U2P4或其盐的方法实现高产率并且能够进行大规模合成。

75. 发明授权

US06392953B2 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US06392953B2
公开(公告)日：2002-05-21
申请号：US09875960
申请日：2001-06-08
申请人： Toshio Yamada , Akinori Shibayama
发明人： Toshio Yamada , Akinori Shibayama
IPC分类号： G11C800
CPC分类号： G11C29/785 , G11C7/062 , G11C7/14 , G11C11/406 , G11C11/4091 , G11C11/4099 , H01L27/10808
摘要： A plurality of information memory cells and a single reference memory cell are coupled to a single word line. The reference memory cell stores reference information equivalent to a reference potential to information readout. Pieces of information, stored in the information memory cells, are fed, over respective bit lines, to first input terminals of sense amplifiers. The reference information, stored in the reference memory cell, is fed, over a bit line, to second input terminals of the sense amplifiers. When the potential of signal charges stored in the information memory cells falls due to leakage current, the potential of a signal charge stored in the reference memory cell correspondingly falls due to leakage current. This prolongs a length of time taken for a difference between these potentials to reach a sense limit, thereby achieving a longer data retention time. As a result of such arrangement, even when there occurs a small current leakage from memory cells, it is possible to secure a long data retention time thereby making it possible to obtain a long refresh cycle period.
摘要翻译：多个信息存储单元和单个参考存储单元耦合到单个字线。参考存储单元存储与参考电位等同于信息读出的参考信息。存储在信息存储单元中的信息块通过各自的位线被馈送到读出放大器的第一输入端。存储在参考存储单元中的参考信息通过位线被馈送到读出放大器的第二输入端。当存储在信息存储单元中的信号电荷的电位由于泄漏电流而下降时，存储在参考存储单元中的信号电荷的电位由于泄漏电流而相应地下降。这延长了这些电位之间的差异达到感测极限所需的时间长度，从而实现更长的数据保留时间。作为这种安排的结果，即使当从存储器单元发生小的电流泄漏时，也可以确保长的数据保持时间，从而可以获得长的刷新周期。

76. 发明授权

US06338826B2 Gas duct having honeycomb structure 有权
标题翻译：具有蜂窝结构的气体管道
公开(公告)号：US06338826B2
公开(公告)日：2002-01-15
申请号：US09337334
申请日：1999-06-21
申请人： Toshio Yamada , Toshihiko Hijikata , Yukiharu Morita
发明人： Toshio Yamada , Toshihiko Hijikata , Yukiharu Morita
IPC分类号： F01N328
CPC分类号： F01N3/2853 , B01D53/94 , F23J15/025 , F23J2217/104 , F23J2219/10
摘要： A gas duct having a honeycomb structure includes: a metal case, a honeycomb structure accommodated in the metal case, a holding member placed between the outer surface of the honeycomb structure and the inner surface of the metal case, and a cone fitted to the inner surface of the metal case at one or both openings of the metal case, wherein the circumference of one or both end faces of the honeycomb structure is allowed to abut on the cone. The gas duct having a honeycomb structure can effectively utilize the whole volume of the honeycomb structure, is low in pressure loss, and inexpensive.
摘要翻译：具有蜂窝结构的气体管道包括：金属壳体，容纳在所述金属壳体中的蜂窝结构体，设置在所述蜂窝结构体的外表面与所述金属壳体的内表面之间的保持构件，在金属壳体的一个或两个开口处的金属壳体的表面，其中蜂窝结构体的一个或两个端面的圆周被允许邻接在锥体上。具有蜂窝结构的气体管道能够有效地利用蜂窝结构体的总体积，压力损失低，成本低廉。

77. 发明授权

US06181620B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US06181620B2
公开(公告)日：2001-01-30
申请号：US09484023
申请日：2000-01-18
申请人： Masashi Agata , Kazunari Takahashi , Tsutomu Fujita , Naoki Kuroda , Toshio Yamada
发明人： Masashi Agata , Kazunari Takahashi , Tsutomu Fujita , Naoki Kuroda , Toshio Yamada
IPC分类号： G11C1124
CPC分类号： G11C11/405 , G11C7/1042 , G11C7/12 , G11C7/22 , G11C11/4091 , G11C11/4094
摘要： The semiconductor storage device of this invention includes memory cells each having two transistors and one storage capacitor. Each memory cell is connected with a first word line and a first bit line for a first port and a second word line and a second bit line for a second port. The first and second bit lines are alternately disposed in an open bit line configuration. In the operation of the semiconductor storage device, in a period when a first precharge signal for precharging each first bit line or a first sense amplifier activating signal for activating a first sense amplifier is kept in an active state, a second precharge signal for precharging each second bit line and a second sense amplifier activating signal for activating a second sense amplifier are both placed in an inactive state.
摘要翻译：本发明的半导体存储装置包括具有两个晶体管和一个存储电容器的存储单元。每个存储单元与第一字线和用于第一端口的第一位线和用于第二端口的第二字线和第二位线连接。第一位线和第二位线以开放位线配置交替布置。在半导体存储装置的动作中，在对第一读出放大器的第一预定电荷进行预充电的第一预充电信号或激活第一读出放大器的第一读出放大器的激活信号保持为有效状态的期间内，第二位线和用于激活第二读出放大器的第二读出放大器激活信号都处于非活动状态。

78. 发明授权

US6091655A Semiconductor memory 失效
公开(公告)号：US6091655A
公开(公告)日：2000-07-18
申请号：US972444
申请日：1997-11-18
申请人： Toshio Yamada , Akinori Shibayama
发明人： Toshio Yamada , Akinori Shibayama
IPC分类号： G11C11/409 , G11C7/06 , G11C7/14 , G11C11/401 , G11C11/406 , G11C11/4091 , G11C11/4099 , G11C29/00 , G11C29/04 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , G11C7/02
CPC分类号： G11C29/785 , G11C11/406 , G11C11/4091 , G11C11/4099 , G11C7/062 , G11C7/14 , H01L27/10808
摘要： A plurality of information memory cells and a single reference memory cell are coupled to a single word line. The reference memory cell stores reference information equivalent to a reference potential to information readout. Pieces of information, stored in the information memory cells, are fed, over respective bit lines, to first input terminals of sense amplifiers. The reference information, stored in the reference memory cell, is fed, over a bit line, to second input terminals of the sense amplifiers. When the potential of signal charges stored in the information memory cells falls due to leakage current, the potential of a signal charge stored in the reference memory cell correspondingly falls due to leakage current. This prolongs a length of time taken for a difference between these potentials to reach a sense limit, thereby achieving a longer data retention time. As a result of such arrangement, even when there occurs a small current leakage from memory cells, it is possible to secure a long data retention time thereby making it possible to obtain a long refresh cycle period.

79. 发明授权

US6005436A Internal reduced-voltage generator for semiconductor integrated circuit 失效
标题翻译：用于半导体集成电路的内部降压发生器
公开(公告)号：US6005436A
公开(公告)日：1999-12-21
申请号：US857648
申请日：1997-05-16
申请人： Akinori Shibayama , Toshio Yamada
发明人： Akinori Shibayama , Toshio Yamada
IPC分类号： G05F1/46 , G11C7/00
CPC分类号： G05F1/465
摘要： A reference voltage generator is composed of a first constant-voltage generator consisting of three p-type MOS transistors for generating a first reference voltage Vref for use in the normal operation, which is independent of an external power-supply voltage VCC and of a second constant-voltage generator consisting of two p-type MOS transistors and one n-type MOS transistor for generating a second reference voltage Vrefbi for use in a burn-in acceleration test, which is dependent on VCC. The output of each of the constant-voltage generators is feedbacked to the other constant-voltage generator as its input. Two differential amplifiers and two output drivers output, as an internal reduced voltage Vint, the higher one of Vref and Vrefbi which are outputted from the reference voltage generator. Since Vint is generated based on the two outputs Vref and Vrefbi which are outputted from the single reference voltage generator and which are related to each other, the power consumption and layout area of an internal reduced-voltage generator, which is suitable for the burn-in, can be reduced.
摘要翻译：一个参考电压发生器由一个由三个p型MOS晶体管组成的第一恒压发生器组成，这三个p型MOS晶体管用于产生用于正常工作的第一参考电压Vref，其独立于外部电源电压VCC和第二恒定电压发生器由两个p型MOS晶体管和一个n型MOS晶体管组成的恒压发生器，用于产生依赖于VCC的老化加速度测试中使用的第二参考电压Vrefbi。每个恒压发生器的输出作为其输入被反馈到另一恒压发生器。两个差分放大器和两个输出驱动器作为内部降低电压Vint输出从参考电压发生器输出的Vref和Vrefbi中较高的一个。由于Vint基于从单个参考电压发生器输出并且彼此相关的两个输出Vref和Vrefbi产生，所以内部降压发生器的功耗和布局面积适合于燃烧 - 在，可以减少。

80. 发明授权

US5983331A Semiconductor integrated circuit having a plurality of chips 失效
标题翻译：具有多个芯片的半导体集成电路
公开(公告)号：US5983331A
公开(公告)日：1999-11-09
申请号：US943411
申请日：1997-09-30
申请人： Hironori Akamatsu , Toshio Yamada , Hisakazu Kotani , Yoshiro Nakata
发明人： Hironori Akamatsu , Toshio Yamada , Hisakazu Kotani , Yoshiro Nakata
IPC分类号： G06F15/78 , G11C11/401 , G06F12/00
CPC分类号： G06F15/7832
摘要： A CPU acting as a mother chip, in combination with a DRAM acting as a subsidiary chip, is mounted. A mode output circuit is able to set the storage capacity of the DRAM as well as the refresh cycle of the DRAM for forwarding to a mode input circuit of the CPU through a mode output terminal of the DRAM and a mode input terminal of the CPU. The CPU controls an address generator according to the data from the mode input circuit, to set the number of bits of address data for access to the DRAM according to the DRAM storage capacity and the DRAM refresh cycle.
摘要翻译：作为母芯片的CPU与作为辅助芯片的DRAM组合安装。模式输出电路能够设置DRAM的存储容量以及用于通过DRAM的模式输出端和CPU的模式输入端转发到CPU的模式输入电路的DRAM的刷新周期。 CPU根据来自模式输入电路的数据控制地址生成器，根据DRAM存储容量和DRAM刷新周期设定用于存取DRAM的地址数据的位数。

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