专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06181620B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US06181620B2
公开(公告)日：2001-01-30
申请号：US09484023
申请日：2000-01-18
申请人： Masashi Agata , Kazunari Takahashi , Tsutomu Fujita , Naoki Kuroda , Toshio Yamada
发明人： Masashi Agata , Kazunari Takahashi , Tsutomu Fujita , Naoki Kuroda , Toshio Yamada
IPC分类号： G11C1124
CPC分类号： G11C11/405 , G11C7/1042 , G11C7/12 , G11C7/22 , G11C11/4091 , G11C11/4094
摘要： The semiconductor storage device of this invention includes memory cells each having two transistors and one storage capacitor. Each memory cell is connected with a first word line and a first bit line for a first port and a second word line and a second bit line for a second port. The first and second bit lines are alternately disposed in an open bit line configuration. In the operation of the semiconductor storage device, in a period when a first precharge signal for precharging each first bit line or a first sense amplifier activating signal for activating a first sense amplifier is kept in an active state, a second precharge signal for precharging each second bit line and a second sense amplifier activating signal for activating a second sense amplifier are both placed in an inactive state.
摘要翻译：本发明的半导体存储装置包括具有两个晶体管和一个存储电容器的存储单元。每个存储单元与第一字线和用于第一端口的第一位线和用于第二端口的第二字线和第二位线连接。第一位线和第二位线以开放位线配置交替布置。在半导体存储装置的动作中，在对第一读出放大器的第一预定电荷进行预充电的第一预充电信号或激活第一读出放大器的第一读出放大器的激活信号保持为有效状态的期间内，第二位线和用于激活第二读出放大器的第二读出放大器激活信号都处于非活动状态。

2. 发明授权

US06285723B1 Timing signal generation circuit 失效
标题翻译：定时信号发生电路
公开(公告)号：US06285723B1
公开(公告)日：2001-09-04
申请号：US09513714
申请日：2000-02-25
申请人： Toshio Yamada , Masashi Agata
发明人： Toshio Yamada , Masashi Agata
IPC分类号： H04L700
CPC分类号： G06F1/04 , G06F1/10 , H03K5/131 , H03K5/133 , H03K5/135 , H03K2005/00052 , H03K2005/00286
摘要： A timing signal generation circuit according to the present invention includes: a delay circuit for transmitting an input clock signal while delaying the clock signal, the delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the delay circuit; a detection delay circuit for transmitting the clock signal while delaying the clock signal, the detection delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the detection delay circuit; a plurality of sample/hold circuits each having a sampling signal terminal, the sampling signal terminals being connected to corresponding ones of the plurality of intermediate taps of the detection delay circuit; a plurality of boundary delay circuits for detecting an edge of the clock signal, the boundary detection circuits being connected to respective output terminals of the sample/hold circuits; and an output selection circuit for extracting the clock signal via at least one of the plurality of intermediate taps selected in accordance with an edge position of the clock signal detected by the boundary detection circuits, the output selection circuit outputting the extracted clock signal as a timing signal.
摘要翻译：根据本发明的定时信号产生电路包括：延迟电路，用于在延迟时钟信号的同时传输输入时钟信号，延迟电路具有多个中间抽头，能够在延迟电路的相应位置输出时钟信号 ; 用于在延迟时钟信号的同时发送时钟信号的检测延迟电路，所述检测延迟电路具有能够在其检测延迟电路中的相应位置处输出时钟信号的多个中间抽头; 多个采样/保持电路，每个采样/保持电路均具有采样信号端子，采样信号端子连接到检测延迟电路的多个中间抽头中的相应的一个; 用于检测时钟信号的边沿的多个边界延迟电路，边界检测电路连接到取样/保持电路的各个输出端; 以及输出选择电路，用于经由根据由边界检测电路检测的时钟信号的边缘位置选择的多个中间抽头中的至少一个提取时钟信号，输出选择电路将提取的时钟信号作为定时输出信号。

3. 发明授权

US5892384A Timing signal generation circuit 失效
公开(公告)号：US5892384A
公开(公告)日：1999-04-06
申请号：US658931
申请日：1996-05-31
申请人： Toshio Yamada , Masashi Agata
发明人： Toshio Yamada , Masashi Agata
IPC分类号： G11C7/00 , G06F1/04 , G06F1/06 , G06F1/10 , G11C11/407 , G11C11/4076 , H03K3/02 , H03K3/10 , H03K5/13 , H03K5/131 , H03K5/19 , H04L7/00 , H03H11/26
CPC分类号： G06F1/04 , G06F1/10 , H03K5/131 , H03K5/133 , H03K5/135 , H03K2005/00052 , H03K2005/00286
摘要： A timing signal generation circuit according to the present invention includes: a delay circuit for transmitting an input clock signal while delaying the clock signal, the delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the delay circuit; a detection delay circuit for transmitting the clock signal while delaying the clock signal, the detection delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the detection delay circuit; a plurality of sample/hold circuits each having a sampling signal terminal, the sampling signal terminals being connected to corresponding ones of the plurality of intermediate taps of the detection delay circuit; a plurality of boundary delay circuits for detecting an edge of the clock signal, the boundary detection circuits being connected to respective output terminals of the sample/hold circuits; and an output selection circuit for extracting the clock signal via at least one of the plurality of intermediate taps selected in accordance with an edge position of the clock signal detected by the boundary detection circuits, the output selection circuit outputting the extracted clock signal as a timing signal.

4. 发明授权

US5680366A Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory 失效
标题翻译：数据传输电路，数据线驱动电路，放大电路，半导体集成电路和半导体存储器
公开(公告)号：US5680366A
公开(公告)日：1997-10-21
申请号：US573133
申请日：1995-12-15
申请人： Hisakazu Kotani , Hironori Akamatsu , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
发明人： Hisakazu Kotani , Hironori Akamatsu , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
IPC分类号： G11C5/02 , G11C7/10 , G11C11/4096 , H03K3/26
CPC分类号： G11C7/1057 , G11C11/4096 , G11C5/025 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1069
摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.
摘要翻译：在用于驱动一对数据线的驱动电路中，差分输入信号的幅度从2.5V减小到小于常规下限电源电压（约1.5V）的0.6V。通过一对数据线传输的差分信号的幅度被放大电路放大到2.5V，然后由锁存电路锁存所得到的信号。在锁存电路锁存之后，停止放大电路的工作。驱动电路仅由多个NMOS晶体管构成，以便不增加在断开状态下流动的漏电流。这里，位于地侧的NMOS晶体管的阈值电压降低到常规的下限值（0.3V〜0.6V），而电源侧的NMOS晶体管的阈值电压低于上述下限值（0V至0.3V），从而增强了在电源侧的NMOS晶体管的驱动力。

5. 发明授权

US5515334A Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory 失效
公开(公告)号：US5515334A
公开(公告)日：1996-05-07
申请号：US260922
申请日：1994-06-15
申请人： Hisakazu Kotani , Hironori Akamatsu , Ichiro Nakao , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
发明人： Hisakazu Kotani , Hironori Akamatsu , Ichiro Nakao , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
IPC分类号： G11C5/02 , G11C7/10 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/1057 , G11C11/4096 , G11C5/025 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1069
摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

6. 发明授权

US5719531A Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory 失效
公开(公告)号：US5719531A
公开(公告)日：1998-02-17
申请号：US739841
申请日：1996-10-30
申请人： Hisakazu Kotani , Hironori Akamatsu , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
发明人： Hisakazu Kotani , Hironori Akamatsu , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
IPC分类号： G11C5/02 , G11C7/10 , G11C11/4096 , H03F3/45
CPC分类号： G11C7/1057 , G11C11/4096 , G11C5/025 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1069
摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

7. 发明授权

US5642323A Semiconductor integrated circuit with a data transmission circuit 失效
标题翻译：具有数据传输电路的半导体集成电路
公开(公告)号：US5642323A
公开(公告)日：1997-06-24
申请号：US573076
申请日：1995-12-15
申请人： Hisakazu Kotani , Hironori Akamatsu , Ichiro Nakao , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
发明人： Hisakazu Kotani , Hironori Akamatsu , Ichiro Nakao , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
IPC分类号： G11C5/02 , G11C7/10 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/1057 , G11C11/4096 , G11C5/025 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1069
摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.
摘要翻译：在用于驱动一对数据线的驱动电路中，差分输入信号的幅度从2.5V减小到小于常规下限电源电压（约1.5V）的0.6V。通过一对数据线传输的差分信号的幅度被放大电路放大到2.5V，然后由锁存电路锁存所得到的信号。在锁存电路锁存之后，停止放大电路的工作。驱动电路仅由多个NMOS晶体管构成，以便不增加在断开状态下流动的漏电流。这里，位于地侧的NMOS晶体管的阈值电压降低到常规的下限值（0.3V〜0.6V），而电源侧的NMOS晶体管的阈值电压低于上述下限值（0V至0.3V），从而增强了在电源侧的NMOS晶体管的驱动力。

8. 发明授权

US6118319A Timing signal generation circuit 失效
标题翻译：定时信号发生电路
公开(公告)号：US6118319A
公开(公告)日：2000-09-12
申请号：US17363
申请日：1998-02-02
申请人： Toshio Yamada , Masashi Agata
发明人： Toshio Yamada , Masashi Agata
IPC分类号： G11C7/00 , G06F1/04 , G06F1/06 , G06F1/10 , G11C11/407 , G11C11/4076 , H03K3/02 , H03K3/10 , H03K5/13 , H03K5/131 , H03K5/19 , H04L7/00
CPC分类号： G06F1/04 , G06F1/10 , H03K5/131 , H03K5/133 , H03K5/135 , H03K2005/00052 , H03K2005/00286
摘要： A timing signal generation circuit according to the present invention includes: a delay circuit for transmitting an input clock signal while delaying the clock signal, the delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the delay circuit; a detection delay circuit for transmitting the clock signal while delaying the clock signal, the detection delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the detection delay circuit; a plurality of sample/hold circuits each having a sampling signal terminal, the sampling signal terminals being connected to corresponding ones of the plurality of intermediate taps of the detection delay circuit; a plurality of boundary delay circuits for detecting an edge of the clock signal, the boundary detection circuits being connected to respective output terminals of the sample/hold circuits; and an output selection circuit for extracting the clock signal via at least one of the plurality of intermediate taps selected in accordance with an edge position of the clock signal detected by the boundary detection circuits, the output selection circuit outputting the extracted clock signal as a timing signal.
摘要翻译：根据本发明的定时信号产生电路包括：延迟电路，用于在延迟时钟信号的同时传输输入时钟信号，延迟电路具有多个中间抽头，能够在延迟电路的相应位置输出时钟信号 ; 用于在延迟时钟信号的同时发送时钟信号的检测延迟电路，所述检测延迟电路具有能够在其检测延迟电路中的相应位置处输出时钟信号的多个中间抽头; 多个采样/保持电路，每个采样/保持电路均具有采样信号端子，采样信号端子连接到检测延迟电路的多个中间抽头中的相应的一个; 用于检测时钟信号的边沿的多个边界延迟电路，边界检测电路连接到取样/保持电路的各个输出端; 以及输出选择电路，用于经由根据由边界检测电路检测的时钟信号的边缘位置选择的多个中间抽头中的至少一个提取时钟信号，输出选择电路将提取的时钟信号作为定时输出信号。

9. 发明授权

US5818782A Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory 失效
公开(公告)号：US5818782A
公开(公告)日：1998-10-06
申请号：US814507
申请日：1997-03-10
申请人： Hisakazu Kotani , Hironori Akamatsu , Ichiro Nakao , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
发明人： Hisakazu Kotani , Hironori Akamatsu , Ichiro Nakao , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
IPC分类号： G11C5/02 , G11C7/10 , G11C11/4096 , G11C13/00
CPC分类号： G11C7/1057 , G11C11/4096 , G11C5/025 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1069
摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

10. 发明授权

US5389810A Semiconductor device having at least one symmetrical pair of MOSFETs 失效
标题翻译：具有至少一对对称的MOSFET的半导体器件
公开(公告)号：US5389810A
公开(公告)日：1995-02-14
申请号：US35731
申请日：1993-03-23
申请人： Masashi Agata , Hiroyuki Yamauchi , Toshio Yamada
发明人： Masashi Agata , Hiroyuki Yamauchi , Toshio Yamada
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L27/088
摘要： A semiconductor device having at least one symmetrical pair of MOSFETs is provided. The device includes a semiconductor layer having an upper surface, an active region formed in the upper surface, an isolation region formed in the upper surface and enclosing the active region, and a pair of MOSFETs formed in the active region, wherein the pair of MOSFETs are symmetrical with respect to a first symmetric plane substantially vertical to the upper surface and also with respect to a second symmetric plane vertical both to the upper surface and to the first symmetric plane, each of the pair of MOSFETs includes a source region, a drain region, and a channel region formed in an upper surface of the active region, the source region is shared by the pair of MOSFETs, and the drain region is spatially isolated from the source region by the channel region.
摘要翻译：提供了具有至少一对对称的MOSFET的半导体器件。该器件包括具有上表面的半导体层，形成在上表面中的有源区，形成在上表面并包围有源区的隔离区，以及形成在有源区中的一对MOSFET，其中，所述一对MOSFET 相对于基本上垂直于上表面的第一对称平面以及垂直于上表面和第一对称平面的第二对称平面是对称的，所述一对MOSFET中的每一个包括源极区域，漏极区域和形成在有源区的上表面中的沟道区域，源极区域被该对MOSFET共享，并且漏极区域通过沟道区域与源极区域空间隔离。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式