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1. 发明授权

US5545977A Reference potential generating circuit and semiconductor integrated circuit arrangement using the same 失效
标题翻译：参考电位发生电路和使用其的半导体集成电路布置
公开(公告)号：US5545977A
公开(公告)日：1996-08-13
申请号：US74561
申请日：1993-06-09
申请人： Toshio Yamada , Akinori Shibayama , Shunichi Iwanari , Atsushi Fujiwara
发明人： Toshio Yamada , Akinori Shibayama , Shunichi Iwanari , Atsushi Fujiwara
IPC分类号： G05F1/24 , G05F1/613 , G05F3/24 , G11C11/407 , G11C11/408 , H01L27/10 , H03K19/00 , G05F3/22
CPC分类号： G05F3/245 , Y10S323/907
摘要： In a circuit, a resistance element is interposed between a positive power supply line (external power supply voltage level VCC) and an output node. To feedback an output potential, there is disposed an N-type MOSFET of which gate is connected to the output node and of which source is connected to the earth line (earth potential VSS) in the circuit. Another three N-type MOSFETs which are so connected in series to one another as to form a MOS diode, are interposed between the drain of the feedback N-type MOSFET and the output node. The earth line also serves as a reference potential line for the potential of the output node. Variations of the threshold voltages of the MOSFETs due to temperature variations are compensated. This restrains the output potential from varying.
摘要翻译：在电路中，在正电源线（外部电源电压电平VCC）和输出节点之间插入电阻元件。为了反馈输出电位，设置了一个N型MOSFET，其栅极连接到输出节点，并且其中的源极连接到电路中的地线（地电位VSS）。在反馈N型MOSFET的漏极和输出节点之间插入另外三个彼此串联连接形成MOS二极管的N型MOSFET。地线也可作为输出节点电位的参考电位线。由于温度变化导致的MOSFET的阈值电压的变化被补偿。这就抑制了输出电位的变化。

2. 发明授权

US5554953A Internal reduced-voltage generator for semiconductor integrated circuit 失效
公开(公告)号：US5554953A
公开(公告)日：1996-09-10
申请号：US132322
申请日：1993-10-06
申请人： Akinori Shibayama , Toshio Yamada
发明人： Akinori Shibayama , Toshio Yamada
IPC分类号： G11C11/407 , G05F1/46 , G05F1/56 , G05F3/26 , G11C11/403 , H01L27/10 , G05F3/02
CPC分类号： G05F1/465
摘要： A reference voltage generator is composed of a first constant-voltage generator consisting of three p-type MOS transistors for generating a first reference voltage Vref for use in the normal operation, which is independent of an external power-supply voltage VCC and of a second constant-voltage generator consisting of two p-type MOS transistors and one n-type MOS transistor for generating a second reference voltage Vrefbi for use in a burn-in acceleration test, which is dependent on VCC. The output of each of the constant-voltage generators is feedbacked to the other constant-voltage generator as its input. Two differential amplifiers and two output drivers output, as an internal reduced voltage Vint, the higher one of Vref and Vrefbi which are outputted from the reference voltage generator. Since Vint is generated based on the two outputs Vref and Vrefbi which are outputted from the single reference voltage generator and which are related to each other, the power consumption and layout area of an internal reduced-voltage generator, which is suitable for the burn-in, can be reduced.

3. 发明授权

US5341035A Substrate potential generator 失效
标题翻译：基板电位发生器
公开(公告)号：US5341035A
公开(公告)日：1994-08-23
申请号：US709961
申请日：1991-06-04
申请人： Akinori Shibayama , Toshio Yamada
发明人： Akinori Shibayama , Toshio Yamada
IPC分类号： G05F3/20 , H03L1/00 , H03L5/00
CPC分类号： G05F3/205
摘要： In a substrate potential generator, a substrate potential is supplied by a substrate potential supplier controlled by a substrate potential detector. The substrate potential detector sends a setting signal having a hysteresis characteristic relative to the substrate potential. That is, the setting signal is higher when the substrate potential supplier is stopped than when the substrate potential supplier is activated or when negative charges are injected into the substrate potential. Thus, the operation of the substrate potential supplier is stopped after the substrate potential becomes lower than the lower setting potential when the substrate potential supplier is activated, while the operation of the substrate potential supplier is started after the substrate potential becomes higher than the upper setting potential after the operation of the substrate potential supplier is stopped. Therefore, the starting and stopping of the substrate potential supplier is not repeated so frequently, so that the dissipating charge and discharge currents accompanied with the starting and stopping will not be enhanced wastefully.
摘要翻译：在衬底电位发生器中，由衬底电位检测器控制的衬底电位供给器提供衬底电位。衬底电位检测器发送具有相对于衬底电位的滞后特性的设置信号。也就是说，当衬底电位供给器停止时，设置信号比衬底电位供应器被激活时或当负电荷注入衬底电位时更高。因此，在基板电位供给器被激活之后，在基板电位变得低于基板电位供给器的下限设定电位之后，基板电位供给器的动作停止，同时基板电位供给器的动作在基板电位变得高于上限值之后开始在停止基板电位供给器的操作之后的潜力。因此，不会如此频繁地重复基板电位供给器的启动和停止，从而不会浪费地增加伴随启动和停止的耗散充放电电流。

4. 发明授权

US06275434B1 Semiconductor memory 失效
公开(公告)号：US06275434B1
公开(公告)日：2001-08-14
申请号：US09523205
申请日：2000-03-10
申请人： Toshio Yamada , Akinori Shibayama
发明人： Toshio Yamada , Akinori Shibayama
IPC分类号： G11C702
CPC分类号： G11C29/785 , G11C7/062 , G11C7/14 , G11C11/406 , G11C11/4091 , G11C11/4099 , H01L27/10808
摘要： A plurality of information memory cells and a single reference memory cell are coupled to a single word line. The reference memory cell stores reference information equivalent to a reference potential to information readout. Pieces of information, stored in the information memory cells, are fed, over respective bit lines, to first input terminals of sense amplifiers. The reference information, stored in the reference memory cell, is fed, over a bit line, to second input terminals of the sense amplifiers. When the potential of signal charges stored in the information memory cells falls due to leakage current, the potential of a signal charge stored in the reference memory cell correspondingly falls due to leakage current. This prolongs a length of time taken for a difference between these potentials to reach a sense limit, thereby achieving a longer data retention time. As a result of such arrangement, even when there occurs a small current leakage from memory cells, it is possible to secure a long data retention time thereby making it possible to obtain a long refresh cycle period.

5. 发明授权

US06392953B2 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US06392953B2
公开(公告)日：2002-05-21
申请号：US09875960
申请日：2001-06-08
申请人： Toshio Yamada , Akinori Shibayama
发明人： Toshio Yamada , Akinori Shibayama
IPC分类号： G11C800
CPC分类号： G11C29/785 , G11C7/062 , G11C7/14 , G11C11/406 , G11C11/4091 , G11C11/4099 , H01L27/10808
摘要： A plurality of information memory cells and a single reference memory cell are coupled to a single word line. The reference memory cell stores reference information equivalent to a reference potential to information readout. Pieces of information, stored in the information memory cells, are fed, over respective bit lines, to first input terminals of sense amplifiers. The reference information, stored in the reference memory cell, is fed, over a bit line, to second input terminals of the sense amplifiers. When the potential of signal charges stored in the information memory cells falls due to leakage current, the potential of a signal charge stored in the reference memory cell correspondingly falls due to leakage current. This prolongs a length of time taken for a difference between these potentials to reach a sense limit, thereby achieving a longer data retention time. As a result of such arrangement, even when there occurs a small current leakage from memory cells, it is possible to secure a long data retention time thereby making it possible to obtain a long refresh cycle period.
摘要翻译：多个信息存储单元和单个参考存储单元耦合到单个字线。参考存储单元存储与参考电位等同于信息读出的参考信息。存储在信息存储单元中的信息块通过各自的位线被馈送到读出放大器的第一输入端。存储在参考存储单元中的参考信息通过位线被馈送到读出放大器的第二输入端。当存储在信息存储单元中的信号电荷的电位由于泄漏电流而下降时，存储在参考存储单元中的信号电荷的电位由于泄漏电流而相应地下降。这延长了这些电位之间的差异达到感测极限所需的时间长度，从而实现更长的数据保留时间。作为这种安排的结果，即使当从存储器单元发生小的电流泄漏时，也可以确保长的数据保持时间，从而可以获得长的刷新周期。

6. 发明授权

US6091655A Semiconductor memory 失效
公开(公告)号：US6091655A
公开(公告)日：2000-07-18
申请号：US972444
申请日：1997-11-18
申请人： Toshio Yamada , Akinori Shibayama
发明人： Toshio Yamada , Akinori Shibayama
IPC分类号： G11C11/409 , G11C7/06 , G11C7/14 , G11C11/401 , G11C11/406 , G11C11/4091 , G11C11/4099 , G11C29/00 , G11C29/04 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , G11C7/02
CPC分类号： G11C29/785 , G11C11/406 , G11C11/4091 , G11C11/4099 , G11C7/062 , G11C7/14 , H01L27/10808
摘要： A plurality of information memory cells and a single reference memory cell are coupled to a single word line. The reference memory cell stores reference information equivalent to a reference potential to information readout. Pieces of information, stored in the information memory cells, are fed, over respective bit lines, to first input terminals of sense amplifiers. The reference information, stored in the reference memory cell, is fed, over a bit line, to second input terminals of the sense amplifiers. When the potential of signal charges stored in the information memory cells falls due to leakage current, the potential of a signal charge stored in the reference memory cell correspondingly falls due to leakage current. This prolongs a length of time taken for a difference between these potentials to reach a sense limit, thereby achieving a longer data retention time. As a result of such arrangement, even when there occurs a small current leakage from memory cells, it is possible to secure a long data retention time thereby making it possible to obtain a long refresh cycle period.

7. 发明授权

US6005436A Internal reduced-voltage generator for semiconductor integrated circuit 失效
标题翻译：用于半导体集成电路的内部降压发生器
公开(公告)号：US6005436A
公开(公告)日：1999-12-21
申请号：US857648
申请日：1997-05-16
申请人： Akinori Shibayama , Toshio Yamada
发明人： Akinori Shibayama , Toshio Yamada
IPC分类号： G05F1/46 , G11C7/00
CPC分类号： G05F1/465
摘要： A reference voltage generator is composed of a first constant-voltage generator consisting of three p-type MOS transistors for generating a first reference voltage Vref for use in the normal operation, which is independent of an external power-supply voltage VCC and of a second constant-voltage generator consisting of two p-type MOS transistors and one n-type MOS transistor for generating a second reference voltage Vrefbi for use in a burn-in acceleration test, which is dependent on VCC. The output of each of the constant-voltage generators is feedbacked to the other constant-voltage generator as its input. Two differential amplifiers and two output drivers output, as an internal reduced voltage Vint, the higher one of Vref and Vrefbi which are outputted from the reference voltage generator. Since Vint is generated based on the two outputs Vref and Vrefbi which are outputted from the single reference voltage generator and which are related to each other, the power consumption and layout area of an internal reduced-voltage generator, which is suitable for the burn-in, can be reduced.
摘要翻译：一个参考电压发生器由一个由三个p型MOS晶体管组成的第一恒压发生器组成，这三个p型MOS晶体管用于产生用于正常工作的第一参考电压Vref，其独立于外部电源电压VCC和第二恒定电压发生器由两个p型MOS晶体管和一个n型MOS晶体管组成的恒压发生器，用于产生依赖于VCC的老化加速度测试中使用的第二参考电压Vrefbi。每个恒压发生器的输出作为其输入被反馈到另一恒压发生器。两个差分放大器和两个输出驱动器作为内部降低电压Vint输出从参考电压发生器输出的Vref和Vrefbi中较高的一个。由于Vint基于从单个参考电压发生器输出并且彼此相关的两个输出Vref和Vrefbi产生，所以内部降压发生器的功耗和布局面积适合于燃烧 - 在，可以减少。

8. 发明授权

US6160753A Semiconductor integrated circuit device having main word lines and sub-word lines 失效
标题翻译：具有主字线和子字线的半导体集成电路器件
公开(公告)号：US6160753A
公开(公告)日：2000-12-12
申请号：US504781
申请日：2000-02-15
申请人： Akinori Shibayama
发明人： Akinori Shibayama
IPC分类号： G11C11/41 , G11C8/14 , G11C11/401 , G11C11/407 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , G11C8/08
CPC分类号： G11C8/14
摘要： Each sub-word line drive circuit SWD in a sub-word line drive section SWLB receives a signal carried by a main word line MWL0, a sub-word line non-selection signal XWD, and a sub-word line drive signal WD to drive a sub-word line SW. The sub-word line non-selection signal XWD is generated by an inverter XWDG in an intersection region SDR based on the sub-word line drive signal WD received by the inverter. The active level of the sub-word line drive signal WD is an internal boosted potential VPP which is higher than the external supply potential VDD. By using as the inactive level of the sub-word line non-selection signal XWD an internal lowered potential VINT which is lower than the external supply potential VDD, power consumption of an internal boosted potential generation circuit is reduced.
摘要翻译：子字线驱动部分SWLB中的每个子字线驱动电路SWD接收由主字线MWL0，子字线非选择信号XWD和子字线驱动信号WD所携带的信号以驱动子字线SW。子字线非选择信号XWD由交流区域SDR中的反相器XWDG基于由逆变器接收的子字线驱动信号WD产生。子字线驱动信号WD的有效电平是比外部电源电位VDD高的内部升压电位VPP。通过将子字线非选择信号XWD的无效电平用作低于外部电源VDD的内部降低电位VINT，内部升压电位产生电路的功耗降低。

9. 发明授权

US4293819A High-speed low-drift operational amplifier 失效
标题翻译：高速低漂移运算放大器
公开(公告)号：US4293819A
公开(公告)日：1981-10-06
申请号：US76428
申请日：1979-09-17
申请人： Akinori Shibayama , Kenji Maio , Norio Yokozawa
发明人： Akinori Shibayama , Kenji Maio , Norio Yokozawa
IPC分类号： H03F3/34 , H03F1/30 , H03F3/45 , H03F1/02
CPC分类号： H03F3/45479 , H03F1/30
摘要： A high-speed low-drift operational amplifier is disclosed in which a coefficient circuit having a voltage gain of more than 1 is formed employing a low frequency operational amplifier with a low-drift characteristic to multiply an input voltage by the voltage gain, the coefficient circuit and a low pass filter are connected in cascade to form a drift compensating circuit, and the inverting and non-inverting input terminals of a wide-band operational amplifier are connected to the input and output terminals of the drift compensating circuit, respectively.
摘要翻译：公开了一种高速低漂移运算放大器，其中使用具有低漂移特性的低频运算放大器形成具有大于1的电压增益的系数电路，以将输入电压乘以电压增益，系数电路和低通滤波器级联连接形成漂移补偿电路，宽带运算放大器的反相和非反相输入端分别连接到漂移补偿电路的输入和输出端。

10. 发明授权

US07290234B2 Method for computer aided design of semiconductor integrated circuits 有权
标题翻译：半导体集成电路计算机辅助设计方法
公开(公告)号：US07290234B2
公开(公告)日：2007-10-30
申请号：US11122221
申请日：2005-05-05
申请人： Akinori Shibayama
发明人： Akinori Shibayama
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L27/0207
摘要： In transistor layout design, a plurality of distances Lfig1, Lfig2, Lfig3 from a gate electrode of a transistor to the edge of a diffusion layer are displayed by multiple lines according to a variation amount of a transistor characteristic with the use of a CAD tool. A layer for defining an isolation region between adjacent transistors is extended automatically by the CAD tool. Accordingly, even in the case where the transistor characteristic varies depending on the distance from the gate electrode of the transistor to the edge of the diffusion layer, the isolation region between the adjacent transistors can be layouted and designed optimally with no measurement of the distance by designer's visual observation necessitated.
摘要翻译：在晶体管布局设计中，从晶体管的栅电极到扩散层的边缘的多个距离Lfig 1，Lfig 2，Lfig 3根据晶体管特性的变化量通过多行显示，使用 CAD工具。用于定义相邻晶体管之间的隔离区域的层由CAD工具自动扩展。因此，即使在晶体管特性根据从晶体管的栅电极到扩散层的边缘的距离而变化的情况下，相邻晶体管之间的隔离区域可以被布置和设计为最佳而不测量距离设计师的视觉观察需要。

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