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    • 79. 发明授权
    • Integrated circuit packaging configuration for rapid customized design
and unique test capability
    • 集成电路封装配置,快速定制设计和独特的测试能力
    • US5214655A
    • 1993-05-25
    • US784094
    • 1991-10-28
    • Charles W. EichelbergerKenneth B. Welles, IIRobert J. Wojnarowski
    • Charles W. EichelbergerKenneth B. Welles, IIRobert J. Wojnarowski
    • G01R31/3185H01L23/538
    • H01L23/5382G01R31/318505H01L2924/0002H01L2924/3011
    • A packaged electronics system, having respective portions each with respective input and output ports, and having interconnection busses between certain of these ports, is tested as follows. Each input port has a set of first transmission gates associated therewith for selectively disconnecting it during testing from the end of each interconnection bus connected bit during normal operation. Each input port has a second set of transmission gates associated therewith for selectively applying test vectors thereto during testing as provided in parallel form from a serially loaded shift register. Each output port connects to the input connections of a respective set of tristate drivers for selectively applying its output signals at relatively low source impedance to at least one interconnection bus connected from the output connections of that set of tristate drivers. A shift register converts the signals appearing in parallel at least one end of each interconnection bus to a concatenation of test results in serial form.
    • 具有相应部分的封装电子系统各自具有相应的输入和输出端口,并且在这些端口中的某些端口之间具有互连总线,如下进行测试。 每个输入端口具有与其相关联的一组第一传输门,用于在正常操作期间从每个互连总线连接的位的端部进行测试时选择性地断开它。 每个输入端口具有与之相关联的第二组传输门,用于在测试期间选择性地将测试向量应用于串行装载的移位寄存器的并行形式。 每个输出端口连接到相应组的三态驱动器的输入连接,用于选择性地将其输出信号以相对低的源阻抗施加到从该组三态驱动器的输出连接连接的至少一个互连总线。 移位寄存器将并联出现的每个互连总线的至少一端的信号以串行形式连接到测试结果。