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    • 5. 发明授权
    • Static CMOS programmable logic array
    • 静态CMOS可编程逻辑阵列
    • US4782249A
    • 1988-11-01
    • US81076
    • 1987-08-03
    • William E. EngelerMenahem LowyJohn T. Pedicone
    • William E. EngelerMenahem LowyJohn T. Pedicone
    • H03K19/177
    • H03K19/1772
    • A CMOS programmable logic array includes a logical AND plane receiving a first group of input logic signals for forming a second group of logic minterms, and a logical OR plane receiving the logic minterms for forming a third group of output logic signals. Each type of logical plane contains a plurality of logic gates. Each plane type can be formed from the other plane type by the addition of a logic inverter to each input, and output of, that other-type plane. Interconnections determine the combination of input signals used to define the logic equation of the signal at the output of each logic gate of each plane. Static latches are used to retain the states of input and minterm logic signals. Logic planes and latches can be operated responsive to a two-phase clock signal.
    • CMOS可编程逻辑阵列包括接收用于形成第二组逻辑小区的第一组输入逻辑信号的逻辑“与”面和接收用于形成第三组输出逻辑信号的逻辑最小值的逻辑“或”平面。 每种类型的逻辑平面包含多个逻辑门。 每个平面类型可以通过向每个输入添加一个逻辑反相器并输出该另一个平面类型而形成。 互连确定用于定义每个平面的每个逻辑门的输出处的信号的逻辑方程的输入信号的组合。 静态锁存器用于保持输入和最小逻辑信号的状态。 逻辑平面和锁存器可以响应于两相时钟信号而被操作。