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71. 发明申请

US20110169064A1 READ TRANSISTOR FOR SINGLE POLY NON-VOLATILE MEMORY USING BODY CONTACTED SOI DEVICE 失效
标题翻译：使用身体接触式SOI器件的单个非易失性存储器的读取晶体管
公开(公告)号：US20110169064A1
公开(公告)日：2011-07-14
申请号：US12685335
申请日：2010-01-11
申请人： Anthony I. Chou , Arvind Kumar
发明人： Anthony I. Chou , Arvind Kumar
IPC分类号： H01L29/94 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/11558 , H01L29/1087 , H01L29/78615
摘要： A read transistor for single poly non-volatile memory using a body contacted SOI transistor and a method of manufacturing the same is provided. The non-volatile random access memory is formed in silicon on insulator (SOI). The non-volatile random access memory includes a read field effect transistor (FET) having a body contact formed in the silicon of the SOI. The body contact is in electrical contact with a diffusion region under a gate of the read FET.
摘要翻译：提供了一种用于使用身体接触的SOI晶体管的单个多重非易失性存储器的读取晶体管及其制造方法。非易失性随机存取存储器形成在绝缘体上硅（SOI）中。非易失性随机存取存储器包括在SOI的硅中形成有体接触的读取场效应晶体管（FET）。身体接触与读取FET的栅极下方的扩散区域电接触。

72. 发明申请

US20110145274A1 Exemplary Data Guidance in a Multi-Modality Data Viewer 审中-公开
标题翻译：多模式数据查看器中的示例性数据指导
公开(公告)号：US20110145274A1
公开(公告)日：2011-06-16
申请号：US12639648
申请日：2009-12-16
申请人： Gopal Avinash , Chetan Hd , Arun Kumar Chandrashekarappa , Arvind Kumar , Raja Shekhara
发明人： Gopal Avinash , Chetan Hd , Arun Kumar Chandrashekarappa , Arvind Kumar , Raja Shekhara
IPC分类号： G06F17/30 , G06F3/048
CPC分类号： G06F19/321
摘要： Systems, methods and mediums with instructions for viewing medical data are provided. A system for viewing medical data can include a computer processor, a database and a user interface. The database can include numerous entries from numerous clinical modalities. Each entry can include image data and/or non-image data. Each entry can include annotated medical information from a previous study. The annotated medical information can include comments and markings. The database can be searchable to identify an entry based on input medical information relating to a current study. The user interface can be configured to simultaneously display annotated medical information from an identified entry and medical information from the current study. The system can further include a second user interface configured to display medical information, allow a user to annotate the medical information, and allow the user to save the annotated medical information as an entry in the database.
摘要翻译：提供了具有查看医疗数据说明的系统，方法和介质。用于查看医疗数据的系统可以包括计算机处理器，数据库和用户界面。数据库可以包括许多临床模式的许多条目。每个条目可以包括图像数据和/或非图像数据。每个条目都可以包括以前研究的注释医学信息。注释的医疗信息可以包括评论和标记。可以搜索数据库以基于与当前研究相关的输入医疗信息来识别条目。用户界面可以被配置为从当前研究中同时显示来自识别的条目的注释医学信息和医学信息。该系统还可以包括被配置为显示医疗信息的第二用户界面，允许用户注释医疗信息，并允许用户将注释的医疗信息作为条目存储在数据库中。

73. 发明授权

US07956415B2 SOI transistor having a carrier recombination structure in a body 失效
标题翻译：在体内具有载流子复合结构的SOI晶体管
公开(公告)号：US07956415B2
公开(公告)日：2011-06-07
申请号：US12133686
申请日：2008-06-05
申请人： Anthony I. Chou , Andres Bryant , Arvind Kumar , Shreesh Narasimha
发明人： Anthony I. Chou , Andres Bryant , Arvind Kumar , Shreesh Narasimha
IPC分类号： H01L27/12
CPC分类号： H01L29/66772 , H01L29/78603 , H01L29/78612
摘要： A top semiconductor layer is formed with two different thicknesses such that a step is formed underneath a body region of a semiconductor-on-insulator (SOI) field effect transistor at the interface between a top semiconductor layer and an underlying buried insulator layer. The interface and the accompanying interfacial defects in the body region provide recombination centers, which increase the recombination rate between the holes and electrons in the body region. Optionally, a spacer portion, comprising a material that functions as recombination centers, is formed on sidewalls of the step to provide an enhanced recombination rate between holes and electrons in the body region, which increases the bipolar breakdown voltage of a SOI field effect transistor.
摘要翻译：顶部半导体层形成有两个不同的厚度，使得在顶部半导体层和下面的掩埋绝缘体层之间的界面处在绝缘体上半导体（SOI）场效应晶体管的体区之下形成台阶。身体区域中的界面和伴随的界面缺陷提供了复合中心，这增加了身体区域中的空穴和电子之间的复合速率。任选地，包括作为复合中心的材料的间隔物部分形成在台阶的侧壁上，以在体区中的空穴和电子之间提供增强的复合率，这增加了SOI场效应晶体管的双极击穿电压。

74. 发明申请

US20100164011A1 Techniques for Enabling Multiple Vt Devices Using High-K Metal Gate Stacks 有权
标题翻译：使用高K金属栅极堆栈启用多个Vt器件的技术
公开(公告)号：US20100164011A1
公开(公告)日：2010-07-01
申请号：US12720354
申请日：2010-03-09
申请人： Martin M. Frank , Arvind Kumar , Vijay Narayanan , Vamsi K. Paruchuri , Jeffrey Sleight
发明人： Martin M. Frank , Arvind Kumar , Vijay Narayanan , Vamsi K. Paruchuri , Jeffrey Sleight
IPC分类号： H01L29/78
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108
摘要： Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.
摘要翻译：提供了用于组合彼此具有不同阈值电压要求的晶体管的技术。在一个方面，一种半导体器件包括具有第一和第二nFET区的衬底以及第一和第二pFET区; 在第一nFET区域上的衬底上的逻辑nFET; 在第一pFET区上的衬底上的逻辑pFET; 位于第二nFET区上的衬底上的SRAM nFET; 以及在第二pFET区上的衬底上的SRAM pFET，每个包括在高K层上具有金属层的栅极堆叠。逻辑nFET栅极堆叠还包括将金属层与高K层分隔开的覆盖层，其中封盖层还被配置为相对于逻辑pFET中的一个或多个的阈值电压移动逻辑nFET的阈值电压，SRAM nFET和SRAM pFET。

75. 发明申请

US20080258221A1 SUBSTRATE SOLUTION FOR BACK GATE CONTROLLED SRAM WITH COEXISTING LOGIC DEVICES 有权
标题翻译：用于具有共同逻辑设备的后盖控制SRAM的基板解决方案
公开(公告)号：US20080258221A1
公开(公告)日：2008-10-23
申请号：US12144272
申请日：2008-06-23
申请人： Robert H. Dennard , Wilfried E. Haensch , Arvind Kumar , Robert J. Miller
发明人： Robert H. Dennard , Wilfried E. Haensch , Arvind Kumar , Robert J. Miller
IPC分类号： H01L27/11
CPC分类号： H01L27/1108
摘要： A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.
摘要翻译：一种半导体结构，其包括至少一个逻辑器件区域和至少一个静态随机存取存储器（SRAM）器件区域，其中每个器件区域包括双门控场效应晶体管（FET），其中每个FET器件的背栅极掺杂提供了特定的水平，以提高不同器件区域内的FET器件的性能。特别地，SRAM器件区域内的背栅极比逻辑器件区域内的后栅极重掺杂。为了控制短沟道效应，逻辑器件区域内的FET器件包括掺杂沟道，而SRAM器件区域内的FET器件不是。在源极/漏极区域之下具有低净掺杂的非均匀横向掺杂分布和在沟道下方的高净掺杂将为逻辑器件提供附加的SCE控制。

76. 发明授权

US07407871B2 Method for passivation of plasma etch defects in DRAM devices 失效
公开(公告)号：US07407871B2
公开(公告)日：2008-08-05
申请号：US11515534
申请日：2006-09-05
申请人： Arvind Kumar , Keen Wah Chow , Devesh Kumar Datta , Subramanian Krishnan
发明人： Arvind Kumar , Keen Wah Chow , Devesh Kumar Datta , Subramanian Krishnan
IPC分类号： H01L21/322
CPC分类号： H01L21/26513 , H01L27/10873
摘要： A process for fabricating an MOS device specifically a DRAM device, featuring passivation of defects in regions of a semiconductor substrate wherein defects left unpassivated can deleteriously influence data retention time, has been developed. A high density plasma dry etching procedure used to define the DRAM conductive gate electrode can create unwanted defects in a region near the surface of uncovered portions of the semiconductor substrate during the high density plasma procedure over etch cycle. Implantation of a group V element such as arsenic can be used to passivate the unwanted plasma etch defects, thus reducing the risk of defect related device leakage phenomena. However to insure the group V implanted species remain at or near the semiconductor surface for optimum defect passivation, the group V element implantation procedure is performed after all high temperature DRAM fabrication steps, such as selective oxidation for creation of oxide spacers on the sides of the conductive gate electrode, have been completed. A slow diffusing implanted arsenic ion is the optimum candidate for passivation while faster diffusing group V elements such as phosphorous are not as attractive for defect passivation.

77. 发明申请

US20080124814A1 Method for passivation of plasma etch defects in DRAM devices 失效
标题翻译： DRAM器件中等离子体蚀刻缺陷钝化的方法
公开(公告)号：US20080124814A1
公开(公告)日：2008-05-29
申请号：US11515534
申请日：2006-09-05
申请人： Arvind Kumar , Keen Wah Chow , Devesh Kumar Datta , Subramanian Krishnan
发明人： Arvind Kumar , Keen Wah Chow , Devesh Kumar Datta , Subramanian Krishnan
IPC分类号： H01L21/02
CPC分类号： H01L21/26513 , H01L27/10873
摘要： A process for fabricating an MOS device specifically a DRAM device, featuring passivation of defects in regions of a semiconductor substrate wherein defects left unpassivated can deleteriously influence data retention time, has been developed. A high density plasma dry etching procedure used to define the DRAM conductive gate electrode can create unwanted defects in a region near the surface of uncovered portions of the semiconductor substrate during the high density plasma procedure over etch cycle. Implantation of a group V element such as arsenic can be used to passivate the unwanted plasma etch defects, thus reducing the risk of defect related device leakage phenomena. However to insure the group V implanted species remain at or near the semiconductor surface for optimum defect passivation, the group V element implantation procedure is performed after all high temperature DRAM fabrication steps, such as selective oxidation for creation of oxide spacers on the sides of the conductive gate electrode, have been completed. A slow diffusing implanted arsenic ion is the optimum candidate for passivation while faster diffusing group V elements such as phosphorous are not as attractive for defect passivation.
摘要翻译：已经开发了制造具有DRAM器件的MOS器件的工艺，其特征在于半导体衬底的区域中的缺陷钝化，其中缺陷未被激活可以有害地影响数据保留时间。用于限定DRAM导电栅电极的高密度等离子体干蚀刻方法可以在蚀刻周期的高密度等离子体工艺期间在半导体衬底的未覆盖部分的表面附近的区域中产生不想要的缺陷。可以使用诸如砷的V族元素的植入来钝化不需要的等离子体蚀刻缺陷，从而降低与缺陷相关的器件泄漏现象的风险。然而，为了确保V族植入物质保留在半导体表面处或附近，以获得最佳缺陷钝化，在所有高温DRAM制造步骤之后执行V族元素注入程序，例如用于在导电栅电极，已经完成。缓慢扩散的注入砷离子是钝化的最佳候选物，而较快扩散V族元素（如磷）对缺陷钝化不具有吸引力。

78. 发明申请

US20070088067A1 Novel amidine compounds for treating microbial infections 审中-公开
标题翻译：用于治疗微生物感染的新型脒化合物
公开(公告)号：US20070088067A1
公开(公告)日：2007-04-19
申请号：US10570584
申请日：2003-09-05
申请人： Richards Tidwell , David Boykin , Reto Brun , Chad Stephens , Arvind Kumar
发明人： Richards Tidwell , David Boykin , Reto Brun , Chad Stephens , Arvind Kumar
IPC分类号： A61K31/42 , C07D261/06 , A61K31/155 , C07C257/18
CPC分类号： C07C257/18 , C07C259/18 , C07D235/20 , C07D307/52 , C07D403/12 , C07D403/14 , C07D405/04 , C07D405/12 , C07D409/14
摘要： Novel amidine and diamidine compounds are useful in the treatment of microbial infections, including mycobacterial, fungal and protozoal infections. Pharmaceutical formulations comprising these compounds can be used in methods of treating microbial infections.
摘要翻译：新型脒和脒化合物可用于治疗微生物感染，包括分枝杆菌，真菌和原生动物感染。包含这些化合物的药物制剂可用于治疗微生物感染的方法。

79. 发明授权

US07024695B1 Method and apparatus for secure remote system management 失效
标题翻译：用于安全远程系统管理的方法和装置
公开(公告)号：US07024695B1
公开(公告)日：2006-04-04
申请号：US09476737
申请日：1999-12-30
申请人： Mohan J. Kumar , Arvind Kumar
发明人： Mohan J. Kumar , Arvind Kumar
IPC分类号： G06F11/00 , G06F11/22 , G06F11/30 , G06F11/32 , G06F11/34 , G06F11/36 , G06F12/14 , G06F12/16 , G06F15/18 , G08B23/00
CPC分类号： G06F21/31 , G06F11/0748 , G06F11/0793 , G06F21/305 , G06F2221/2103 , H04L41/00 , H04L41/22 , H04L63/083
摘要： To prevent unauthorized access to hardware management information in an out-of-band mode, i.e., when the operating system of the hardware is not executing, a method and apparatus employ an authentication protocol. Upon receiving a request for hardware component information in a service processor that is disposed in a hardware component, which request is received as an open session request and which request passes external to an operating system controlling the hardware component, the service processor transmits a challenge string to the requesting client application. In response to a challenge response received from the requesting client application, the service processor compares the challenge response to an expected response to the challenge. The expected challenge response is calculated by the service processor. Based on the result of the comparison, the service processor transmits an authentication response to the requesting client application indicating success or failure of the authentication process. On the client side, in response to a challenge string from the service processor, the requesting client application transmits to the service processor a challenge response, which includes an sequence number that increments with every new message from the requesting client application. The challenge response also includes a hash number calculated by the requesting client application, which hash number is a function of the challenge string, session identification number, sequence number and/or a password. Each new packet including data and/or commands from the client application includes a similarly calculated hash number.
摘要翻译：为了防止在带外模式（即，硬件的操作系统未执行）下的硬件管理信息的未经授权的访问，方法和装置采用认证协议。在接收到在硬件组件中设置的服务处理器中的硬件组件信息的请求时，该请求作为开放会话请求被接收，并且哪个请求在控制硬件组件的操作系统外部通过，服务处理器发送挑战串到请求的客户端应用程序。响应于从请求客户端应用程序接收到的挑战响应，服务处理器将挑战响应与对挑战的期望响应进行比较。预期的挑战响应由服务处理器计算。基于比较的结果，服务处理器向请求客户端应用发送认证响应，指示认证过程的成败。在客户端，响应于来自服务处理器的挑战串，请求客户端应用程序向服务处理器发送挑战响应，该响应响应包括随请求的客户端应用程序的每个新消息递增的序列号。挑战响应还包括由请求客户端应用计算的哈希号，该哈希号是挑战串，会话识别号，序列号和/或密码的函数。包括来自客户端应用程序的数据和/或命令的每个新分组包括类似地计算的散列数。

80. 发明申请

US20060063931A1 Compounds, methods and compositions useful for the treatment of bovine viral diarrhea virus (BVDV) infection and hepatitis C virus (HCV) infection 失效
公开(公告)号：US20060063931A1
公开(公告)日：2006-03-23
申请号：US11262427
申请日：2005-10-28
申请人： Christine Dykstra , Maurice Givens , David Stringfellow , Kenny Brock , David Boykin , Arvind Kumar , W. David Wilson , Richard Tidwell , Chad Stephens
发明人： Christine Dykstra , Maurice Givens , David Stringfellow , Kenny Brock , David Boykin , Arvind Kumar , W. David Wilson , Richard Tidwell , Chad Stephens
IPC分类号： C07D405/14
CPC分类号： C07D405/14 , A61K31/341 , A61K31/381 , A61K31/401 , A61K31/4178 , A61K31/4184 , A61K31/423 , A61K31/426 , A61K31/428 , A61K31/506 , C07D207/08 , C07D207/09 , C07D277/28 , C07D307/14 , C07D333/20 , C07D405/04 , C07D405/10
摘要： The present invention relates to novel compounds and methods that are useful in treating members of the Flaviviridae family of viruses. Compounds of the present invention will have a structure according to Formulas (I)-(VI) as recited throughout the application.

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