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1. 发明申请

US20130234280A1 SHALLOW TRENCH ISOLATION IN DYNAMIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：动态随机访问存储器中的轻微分离分离及其制造方法
公开(公告)号：US20130234280A1
公开(公告)日：2013-09-12
申请号：US13421979
申请日：2012-03-16
申请人： ARVIND KUMAR , ERIC LAHAUG , DEVESH KUMAR DATTA , KEEN WAH CHOW , CHIA MING YANG , CHIEN-CHI LEE , FREDERICK DAVID FISHBURN
发明人： ARVIND KUMAR , ERIC LAHAUG , DEVESH KUMAR DATTA , KEEN WAH CHOW , CHIA MING YANG , CHIEN-CHI LEE , FREDERICK DAVID FISHBURN
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76224 , H01L27/10847
摘要： A manufacturing method of STI in DRAM includes the following steps. Step 1 is providing a substrate and step 2 is forming at least one trench in the substrate. Step 3 is doping at least one of side portions and bottom portions of the trench with a dopant. Step 4 is forming an oxidation inside the trench and step 5 is providing a planarization step to remove the oxidation. The stress of the corners of STI is reduced so as to modify the defect of the substrate and improve the DRAM variability in retention time.
摘要翻译： DRAM中的STI的制造方法包括以下步骤。步骤1是提供衬底，步骤2在衬底中形成至少一个沟槽。步骤3是用掺杂剂掺杂沟槽的侧部和底部中的至少一个。步骤4在沟槽内形成氧化，步骤5提供平面化步骤以去除氧化。 STI的拐角应力减小，从而改变了基板的缺陷，提高了保留时间的DRAM变化。

2. 发明申请

US20110201185A1 Method to improve transistor performance matching for plasma-assisted source/drain formation 审中-公开
标题翻译：提高等离子体辅助源极/漏极形成的晶体管性能匹配的方法
公开(公告)号：US20110201185A1
公开(公告)日：2011-08-18
申请号：US12658931
申请日：2010-02-17
申请人： Devesh Kumar Datta , Keen Wah Chow , Chun Kit Kwok , Wai Khin Joshua Lee
发明人： Devesh Kumar Datta , Keen Wah Chow , Chun Kit Kwok , Wai Khin Joshua Lee
IPC分类号： H01L21/3213
CPC分类号： H01L21/2236
摘要： Methods to dope transistors with equal or similar dopant concentration are described. In a first alternative, a slow dose per pulse ramp during plasma-assisted doping is proposed. This method results in a thinner surface deposited layer resulting in equal dopant concentration throughout the area. In a second alternative, transistors are placed away from the mask edge in order to achieve equal dopant concentration.
摘要翻译：描述了掺杂浓度相等或相似的掺杂晶体管的方法。在第一替代方案中，提出了在等离子体辅助掺杂期间每脉冲斜坡的缓慢剂量。这种方法导致较薄的表面沉积层，导致整个区域的掺杂剂浓度相等。在第二替代方案中，为了实现相等的掺杂剂浓度，将晶体管放置在远离掩模边缘的位置。

3. 发明授权

US07407871B2 Method for passivation of plasma etch defects in DRAM devices 失效
公开(公告)号：US07407871B2
公开(公告)日：2008-08-05
申请号：US11515534
申请日：2006-09-05
申请人： Arvind Kumar , Keen Wah Chow , Devesh Kumar Datta , Subramanian Krishnan
发明人： Arvind Kumar , Keen Wah Chow , Devesh Kumar Datta , Subramanian Krishnan
IPC分类号： H01L21/322
CPC分类号： H01L21/26513 , H01L27/10873
摘要： A process for fabricating an MOS device specifically a DRAM device, featuring passivation of defects in regions of a semiconductor substrate wherein defects left unpassivated can deleteriously influence data retention time, has been developed. A high density plasma dry etching procedure used to define the DRAM conductive gate electrode can create unwanted defects in a region near the surface of uncovered portions of the semiconductor substrate during the high density plasma procedure over etch cycle. Implantation of a group V element such as arsenic can be used to passivate the unwanted plasma etch defects, thus reducing the risk of defect related device leakage phenomena. However to insure the group V implanted species remain at or near the semiconductor surface for optimum defect passivation, the group V element implantation procedure is performed after all high temperature DRAM fabrication steps, such as selective oxidation for creation of oxide spacers on the sides of the conductive gate electrode, have been completed. A slow diffusing implanted arsenic ion is the optimum candidate for passivation while faster diffusing group V elements such as phosphorous are not as attractive for defect passivation.

4. 发明申请

US20080124814A1 Method for passivation of plasma etch defects in DRAM devices 失效
标题翻译： DRAM器件中等离子体蚀刻缺陷钝化的方法
公开(公告)号：US20080124814A1
公开(公告)日：2008-05-29
申请号：US11515534
申请日：2006-09-05
申请人： Arvind Kumar , Keen Wah Chow , Devesh Kumar Datta , Subramanian Krishnan
发明人： Arvind Kumar , Keen Wah Chow , Devesh Kumar Datta , Subramanian Krishnan
IPC分类号： H01L21/02
CPC分类号： H01L21/26513 , H01L27/10873
摘要： A process for fabricating an MOS device specifically a DRAM device, featuring passivation of defects in regions of a semiconductor substrate wherein defects left unpassivated can deleteriously influence data retention time, has been developed. A high density plasma dry etching procedure used to define the DRAM conductive gate electrode can create unwanted defects in a region near the surface of uncovered portions of the semiconductor substrate during the high density plasma procedure over etch cycle. Implantation of a group V element such as arsenic can be used to passivate the unwanted plasma etch defects, thus reducing the risk of defect related device leakage phenomena. However to insure the group V implanted species remain at or near the semiconductor surface for optimum defect passivation, the group V element implantation procedure is performed after all high temperature DRAM fabrication steps, such as selective oxidation for creation of oxide spacers on the sides of the conductive gate electrode, have been completed. A slow diffusing implanted arsenic ion is the optimum candidate for passivation while faster diffusing group V elements such as phosphorous are not as attractive for defect passivation.
摘要翻译：已经开发了制造具有DRAM器件的MOS器件的工艺，其特征在于半导体衬底的区域中的缺陷钝化，其中缺陷未被激活可以有害地影响数据保留时间。用于限定DRAM导电栅电极的高密度等离子体干蚀刻方法可以在蚀刻周期的高密度等离子体工艺期间在半导体衬底的未覆盖部分的表面附近的区域中产生不想要的缺陷。可以使用诸如砷的V族元素的植入来钝化不需要的等离子体蚀刻缺陷，从而降低与缺陷相关的器件泄漏现象的风险。然而，为了确保V族植入物质保留在半导体表面处或附近，以获得最佳缺陷钝化，在所有高温DRAM制造步骤之后执行V族元素注入程序，例如用于在导电栅电极，已经完成。缓慢扩散的注入砷离子是钝化的最佳候选物，而较快扩散V族元素（如磷）对缺陷钝化不具有吸引力。

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