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71. 发明申请

US20120206374A1 SYSTEMS AND METHODS FOR SCREEN DATA MANAGEMENT 审中-公开
标题翻译：用于屏幕数据管理的系统和方法
公开(公告)号：US20120206374A1
公开(公告)日：2012-08-16
申请号：US13026610
申请日：2011-02-14
申请人： Ying-Ju CHEN , Hsueh-Chun CHEN , Nicole Alexandra CODDINGTON
发明人： Ying-Ju CHEN , Hsueh-Chun CHEN , Nicole Alexandra CODDINGTON
IPC分类号： G06F3/041
CPC分类号： G06F3/03545 , G06F3/04883
摘要： Methods and systems for screen data management are provided. First, a screenshot is generated for screen data displayed in a touch-sensitive display unit. Contacts and movements of an object on the touch-sensitive display unit are received. It is determined whether the object is a pen or not. When the object is a pen, gestures corresponding to the contacts and movements of the object are recorded. Then, an event is received. In response to the event, the screenshot and the gestures corresponding to the contacts and movements of the object are merged to generate an integrated screenshot.
摘要翻译：提供了屏幕数据管理的方法和系统。首先，生成用于在触敏显示单元中显示的画面数据的截图。接收触敏显示单元上的物体的触点和移动。确定对象是否是笔。当物体是笔时，记录与物体的触点和移动相对应的手势。然后，收到一个事件。响应于该事件，与对象的联系人和移动相对应的屏幕截图和手势被合并以产生集成屏幕截图。

72. 发明申请

US20120193712A1 FinFET STRUCTURE HAVING FULLY SILICIDED FIN 有权
标题翻译：具有完全硅化物的FinFET结构
公开(公告)号：US20120193712A1
公开(公告)日：2012-08-02
申请号：US13015123
申请日：2011-01-27
申请人： Andres Bryant , Huiming Bu , Dechao Guo , Wilfried E. Haensch , Chun-Chen Yeh
发明人： Andres Bryant , Huiming Bu , Dechao Guo , Wilfried E. Haensch , Chun-Chen Yeh
IPC分类号： H01L29/786 , H01L21/28
CPC分类号： H01L29/41791 , H01L21/28518 , H01L21/76895 , H01L29/66795 , H01L29/7843 , H01L29/785
摘要： A semiconductor device which includes fins of a semiconductor material formed on a semiconductor substrate and then a gate electrode formed over and in contact with the fins. An insulator layer is deposited over the gate electrode and the fins. A trench opening is then etched in the insulator layer. The trench opening exposes the fins and extends between the fins. The fins are then silicided through the trench opening. Then, the trench opening is filled with a metal in contact with the silicided fins to form a local interconnect connecting the fins.
摘要翻译：一种半导体器件，其包括在半导体衬底上形成的半导体材料的散热片，然后形成在鳍片上并与翅片接触的栅电极。绝缘体层沉积在栅电极和鳍片上。然后在绝缘体层中蚀刻沟槽开口。沟槽开口暴露翅片并在翅片之间延伸。然后将鳍片通过沟槽开口硅化。然后，沟槽开口填充有与硅化物翅片接触的金属，以形成连接翅片的局部互连。

73. 发明授权

US08228302B2 Display apparatus and data read-out controller thereof 有权
标题翻译：显示装置和数据读出控制器
公开(公告)号：US08228302B2
公开(公告)日：2012-07-24
申请号：US12235991
申请日：2008-09-23
申请人： Chung-Chun Chen , Cheng-Chiu Pai , Yu-Hsuan Li
发明人： Chung-Chun Chen , Cheng-Chiu Pai , Yu-Hsuan Li
IPC分类号： G06F3/041
CPC分类号： G06F3/0416 , G06F1/32
摘要： A display apparatus and a data read-out controller thereof are provided. The display apparatus comprises a touch display module, a first data read-out controller, and a second data read-out controller. Each of the first and the second data read-out controllers comprises a first read-out switch, a second read-out switch, a first sampling unit, and a second sampling unit. According to the time division multiple output operated by the first sampling units, the first read-out switches, the second sampling units, and the second read-out switches of the first and the second data read-out controllers, the number of the output points and power loss can be reduced effectively.
摘要翻译：提供了显示装置和数据读出控制器。显示装置包括触摸显示模块，第一数据读出控制器和第二数据读出控制器。第一和第二数据读出控制器中的每一个包括第一读出开关，第二读出开关，第一采样单元和第二采样单元。根据由第一采样单元操作的时分多路输出，第一和第二数据读出控制器的第一读出开关，第二采样单元和第二读出开关，输出的数量点和功率损耗可以有效降低。

74. 发明申请

US20120181591A1 NON-VOLATILE FINFET MEMORY ARRAY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性FINFET存储器阵列及其制造方法
公开(公告)号：US20120181591A1
公开(公告)日：2012-07-19
申请号：US13006339
申请日：2011-01-13
申请人： Chun CHEN , Shenqing Fang
发明人： Chun CHEN , Shenqing Fang
IPC分类号： H01L27/105 , H01L21/762
CPC分类号： H01L21/28282 , H01L21/76224 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11568 , H01L27/1211 , H01L29/66795 , H01L29/66833
摘要： An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device, the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the dielectric isolation material in the select gate regions have a height greater than or equal to than a height of the projections in the select gate regions. The electronic device further includes gate features disposed on the substrate within the memory cell region and the select gate regions over the projections and the dielectric isolation material, where the gate features coextend in a second direction transverse to the first direction.
摘要翻译：一种电子器件包括具有半导体表面的衬底，具有通过存储单元区域和选择栅极区域沿第一方向共同延伸的多个鳍式突起。电子设备还包括设置在突起之间的空间中的电介质隔离材料。在电子设备中，存储单元区域中的介质隔离材料的高度小于存储单元区域中的突起的高度，并且选择栅极区域中的介电隔离材料的高度大于或等于突起在选择栅极区域的高度。电子设备还包括设置在存储单元区域内的衬底上的栅极特征以及突出部分和介电隔离材料上的选择栅极区域，其中栅极特征在横向于第一方向的第二方向上共同延伸。

75. 发明申请

US20120170590A1 Bandwidth Arrangement Method and Transmitter Thereof 审中-公开
标题翻译：带宽排列方法及其发射机
公开(公告)号：US20120170590A1
公开(公告)日：2012-07-05
申请号：US13073874
申请日：2011-03-28
申请人： Shen-Ming Chung , Chi-Chun Chen , Lung-Chih Kuo , Chang-Hsien Chen
发明人： Shen-Ming Chung , Chi-Chun Chen , Lung-Chih Kuo , Chang-Hsien Chen
IPC分类号： H04L12/56
CPC分类号： H04L47/562 , H04L47/568
摘要： A bandwidth arranging method includes the following steps of: registering isochronous packets of N isochronous streams, N is a natural number greater than 1; segmenting an isochronous transmission period into M sub-periods, M is a natural number greater than 1; arranging operation of transmitting each of the N isochronous streams in one of the M sub-periods and allocating corresponding bandwidth according to bandwidth requirement information corresponding to each of the N isochronous streams; arranging the isochronous packets into M output queues corresponding to the respective M sub-periods; outputting isochronous packets stored in the M output queues in the respective M sub-periods.
摘要翻译：带宽排列方法包括以下步骤：注册N个同步流的等时分组，N是大于1的自然数; 将同步传输周期分段为M个子周期，M是大于1的自然数; 安排在所述M个子周期之一中发送所述N个等时流中的每一个的操作，并根据对应于所述N个同步流中的每一个的带宽要求信息分配相应的带宽; 将等时分组布置成对应于各M个子周期的M个输出队列; 输出存储在M个输出队列中的各个M个子周期中的同步分组。

76. 发明授权

US08212253B2 Shallow junction formation and high dopant activation rate of MOS devices 有权
标题翻译：浅结点形成和MOS器件的高掺杂剂激活率
公开(公告)号：US08212253B2
公开(公告)日：2012-07-03
申请号：US13228182
申请日：2011-09-08
申请人： Chun-Feng Nieh , Keh-Chiang Ku , Nai-Han Cheng , Chi-Chun Chen , Li-Te S. Lin
发明人： Chun-Feng Nieh , Keh-Chiang Ku , Nai-Han Cheng , Chi-Chun Chen , Li-Te S. Lin
IPC分类号： H01L29/167 , H01L29/26 , H01L29/24 , H01L21/22
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/26586 , H01L29/1083 , H01L29/66492 , H01L29/665 , H01L29/6659
摘要： A semiconductor structure comprises a gate stack in a semiconductor substrate and a lightly doped source/drain (LDD) region in the semiconductor substrate. The LDD region is adjacent to a region underlying the gate stack. The LDD region comprises carbon and an n-type impurity, and the n-type impurity comprises phosphorus tetramer.
摘要翻译：半导体结构包括半导体衬底中的栅极堆叠和半导体衬底中的轻掺杂源极/漏极（LDD）区域。 LDD区域与栅堆叠下方的区域相邻。 LDD区域包含碳和n型杂质，n型杂质包括磷四聚体。

77. 发明申请

US20120139599A1 MULTIPLEX DRIVING CIRCUIT 有权
标题翻译：多路驱动电路
公开(公告)号：US20120139599A1
公开(公告)日：2012-06-07
申请号：US13198862
申请日：2011-08-05
申请人： Chung-Chun CHEN , Hsiao-Wen Wang
发明人： Chung-Chun CHEN , Hsiao-Wen Wang
IPC分类号： H03K3/289
CPC分类号： H03K17/102 , G09G3/3677 , G09G2310/0286
摘要： A multiplex driving circuit receives m master signals and n slave signals, and includes m driving modules for generating m×n gate driving signals. Each driving module includes a voltage boost stage and n driving stages. The voltage boost stage is used for receiving a first master signal of the m master signals and converting the first master signal into a first high voltage signal, wherein a high logic level of the first master signal is increased to a highest voltage by the voltage boost stage. The n driving stages receives the n slave signals, respectively, and receives the first high voltage signal. In response to the highest voltage of the first high voltage signal, the n driving stages sequentially generates n gate driving signals according to the n slave signals.
摘要翻译：复用驱动电路接收m个主信号和n个从机信号，并且包括用于产生m×n个门驱动信号的m个驱动模块。每个驱动模块包括升压级和n个驱动级。升压级用于接收m个主信号的第一主信号并将第一主信号转换成第一高电压信号，其中第一主信号的高逻辑电平通过升压增加到最高电压阶段。 n个驱动级分别接收n个从机信号，并接收第一高电压信号。响应于第一高电压信号的最高电压，n个驱动级根据n个从机信号顺序产生n个门驱动信号。

78. 发明授权

US08193325B2 Processing method for nano-miniaturizing chitosan of modifying property 有权
标题翻译：壳聚糖纳米小型化改性的加工方法
公开(公告)号：US08193325B2
公开(公告)日：2012-06-05
申请号：US12318550
申请日：2008-12-31
申请人： Wen-Tung Chou , Ming-Yi Lai , Kun-Shan Huang , Wei-Chun Chen
发明人： Wen-Tung Chou , Ming-Yi Lai , Kun-Shan Huang , Wei-Chun Chen
IPC分类号： C08B37/08 , C07H5/06
CPC分类号： C07H1/00 , C08B37/003 , C08L5/08
摘要： The present invention relates a processing method for nano-miniaturizing chitosan of modifying property, which degrades the chitosan of high molecular weight down to the chitosan of middle and low molecular weight, then primarily nano-miniaturizes the interim chitosan by quaternary ammonium salt/synthesis, finally yield the nano-miniaturized chitosan of modified property by sol-gel method to have features in good biocompatibility and bioactivity to be served as additive material in products of cosmetics, medical treatment, hygiene, health care, biomedicine, agriculture, textile, food and so like so that not only the antiseptic, moisture-retentive and deodorizing capabilities can be promoted but also the processing cost can be reduced due to easiness of the mass production.
摘要翻译：本发明涉及壳聚糖纳米小型改性性能的加工方法，其将高分子量壳聚糖降解为中低分子量的壳聚糖，然后主要通过季铵盐/合成来使临时壳聚糖纳米微小化，最终通过溶胶 - 凝胶法生产具有良好生物相容性和生物活性的纳米小型化壳聚糖，作为化妆品，医疗，卫生，保健，生物医药，农业，纺织，食品和食品等产品中的添加剂。所以不仅可以促进防腐，保湿和除臭的能力，而且由于大量生产的容易性，可以降低加工成本。

79. 发明申请

US20120136094A1 VARNISH COMPOSITION, AND PRE-IMPREGNATED MANUFACTURE THEREOF 有权
标题翻译： VARNISH组合物及其预先制备
公开(公告)号：US20120136094A1
公开(公告)日：2012-05-31
申请号：US12955382
申请日：2010-11-29
申请人： LI-CHUN CHEN , Chun-Chieh Huang
发明人： LI-CHUN CHEN , Chun-Chieh Huang
IPC分类号： C08K5/5313
CPC分类号： C08G59/226 , C08G59/26 , C08G59/3218 , C08G59/38 , C08K5/0066 , C08K5/51 , C08L63/00 , C09D163/00 , Y10T428/24994 , Y10T428/31511
摘要： A varnish composition includes composition (A): an epoxy resin, composition (B): a hardener, composition (C): an accelerator, composition (D): phosphor-containing flame retardant, and composition (E): fillers, wherein composition (A) includes composition (A-1): phosphor-containing epoxy resin, phosphor-containing and silicon-containing epoxy resin, or a mixture thereof; composition (A-2): dicyclopentadiene epoxy resin; and composition (A-3): oxazolidone epoxy resin.
摘要翻译：清漆组合物包括组合物（A）：环氧树脂，组合物（B）：硬化剂，组合物（C）：促进剂，组合物（D）：含磷阻燃剂和组合物（E）：其中组合物（A）包括组合物（A-1）：含荧光体的环氧树脂，含荧光体的含硅环氧树脂或其混合物; 组合物（A-2）：二环戊二烯环氧树脂; （A-3）：恶唑烷酮环氧树脂。

80. 发明申请

US20120132404A1 USE OF A GRAPHITE HEAT-DISSIPATION DEVICE INCLUDING A PLATING METAL LAYER 有权
标题翻译：使用包括镀金属层的石墨加热装置
公开(公告)号：US20120132404A1
公开(公告)日：2012-05-31
申请号：US13366353
申请日：2012-02-05
申请人： Ko-Chun CHEN , Chiu-Lang LIN
发明人： Ko-Chun CHEN , Chiu-Lang LIN
IPC分类号： F28F13/00
CPC分类号： F28F7/00
摘要： The present invention relates to a heat-dissipating device for an electronic device, comprising a graphite planar body, one or more metal layers, an insulation film and an adhesive. The heat-dissipating device is optionally attached to a heat sink. The method of using the heat-dissipating device to dissipate heat is also disclosed.
摘要翻译：本发明涉及一种电子装置的散热装置，其特征在于，包括石墨平面体，一个或多个金属层，绝缘膜和粘合剂。散热装置可选地连接到散热器。还公开了使用散热装置散热的方法。

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