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61. 发明授权

US08217819B2 Multiplying DAC and a method thereof 有权
标题翻译：乘法DAC及其方法
公开(公告)号：US08217819B2
公开(公告)日：2012-07-10
申请号：US12941510
申请日：2010-11-08
申请人： Soon-Jyh Chang , Jin-Fu Lin
发明人： Soon-Jyh Chang , Jin-Fu Lin
IPC分类号： H03M1/66
CPC分类号： H03M1/0653 , H03M1/806
摘要： The present invention is directed to a multiplying digital-to-analog converter (MDAC) and its method. First ends of capacitors are electrically coupled to an inverting input node of an amplifier, wherein two of the capacitors are alternatively configured as a feedback capacitor. Each capacitor is composed of at least two sub-capacitors. Second ends of capacitors are electrically coupled to an input signal via a number of sampling switches, and the second ends of the capacitors are electrically coupled to DAC voltages respectively via a number of amplifying switches. A sorting circuit is configured to sort the sub-capacitors, wherein the sorted sub-capacitors are then paired in a manner such that variance of mismatch among the sub-capacitors is thus averaged.
摘要翻译：本发明涉及一种乘法数模转换器（MDAC）及其方法。电容器的第一端电耦合到放大器的反相输入节点，其中两个电容器被配置为反馈电容器。每个电容器由至少两个子电容器组成。电容器的第二端通过多个采样开关电耦合到输入信号，并且电容器的第二端分别经由多个放大开关电耦合到DAC电压。排序电路被配置为对子电容器进行排序，其中分选的子电容器然后被配对，使得子电容器之间的失配的变化被平均化。

62. 发明申请

US20110309963A1 SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER, METHOD OF CONTROLLING SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER, SOLID-STATE IMAGING DEVICE, AND IMAGING APPARATUS 有权
标题翻译：连续逼近型A / D转换器，控制类似A / D转换器，固态成像装置和成像装置的控制方法
公开(公告)号：US20110309963A1
公开(公告)日：2011-12-22
申请号：US13222062
申请日：2011-08-31
申请人： Masaki Sakakibara
发明人： Masaki Sakakibara
IPC分类号： H03M1/34
CPC分类号： H03M1/0675 , H03M1/066 , H03M1/20 , H03M1/40 , H03M1/462 , H03M1/806 , H04N5/363 , H04N5/378
摘要： A successive approximation type A/D converter includes: a reference signal generating section generating a reference signal; a comparator comparing an analog signal input thereto with the reference signal and converting the analog signal into a digital signal; and a control section controlling the reference signal to perform oversampling by executing an A/D conversion process on the analog signal at the comparator plural times such that the analog signal is A/D-converted into a digital value of N bits at the first A/D conversion process and such that the second and subsequent A/D conversion processes are performed starting with a lower bit of the (N−n)-th or lower order with upper n bits of the N-bit digital value obtained at the first A/D conversion process fixed.
摘要翻译：逐次逼近型A / D转换器包括：产生参考信号的参考信号产生部分; 比较将输入的模拟信号与参考信号进行比较并将模拟信号转换为数字信号的比较器; 以及控制部，通过对比较器的模拟信号多次执行A / D转换处理，控制参考信号进行过采样，使得模拟信号在A的第一个A处被A / D转换成N位的数字值 / D转换处理，并且使得从第（N-n）个或更低阶的较低位开始执行第二和随后的A / D转换处理，其中在第一（N-n）位获得的N位数字值的高n位 A / D转换过程固定。

63. 发明申请

US20110261086A1 TWO-STAGE DAC ARCHITECTURE FOR LCD SOURCE DRIVER UTILIZING ONE-BIT SERIAL CHARGE REDISTRIBUTION DAC 有权
标题翻译：用于液晶源驱动器的两级DAC架构使用单位串行充电重分配DAC
公开(公告)号：US20110261086A1
公开(公告)日：2011-10-27
申请号：US12859893
申请日：2010-08-20
申请人： Nang-Ping TU
发明人： Nang-Ping TU
IPC分类号： G09G3/36 , H03M1/06 , G09G5/10 , H03M1/66
CPC分类号： G09G3/3696 , G09G3/3688 , G09G2310/027 , H03M1/687 , H03M1/72 , H03M1/76 , H03M1/804 , H03M1/806
摘要： A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage. A voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.
摘要翻译：用于响应于M位数字输入代码输出模拟电压的两级数模转换器包括具有高参考电压输入节点的一位串行电荷再分配数模转换器，用于接收高电平参考电压和低参考电压输入节点，用于接收低参考电压。电压选择器根据M位数字输入代码的至少一部分将高参考电压和低参考电压设置为选定电平。

64. 发明授权

US07884746B2 Noise limitation of a signal dependent multibit digital to analog signal conversion 有权
标题翻译：信号相关多位数字到模拟信号转换的噪声限制
公开(公告)号：US07884746B2
公开(公告)日：2011-02-08
申请号：US12422304
申请日：2009-04-13
申请人： Sandeep Oswal , Jagannathan Venkataraman
发明人： Sandeep Oswal , Jagannathan Venkataraman
IPC分类号： H03M1/66
CPC分类号： H03M1/0665 , H03M1/806 , H03M3/464
摘要： Several methods and a system of noise limitation of a signal dependent multibit digital to analog signal conversion are disclosed. An exemplary embodiment provides a method that includes receiving an output of a multibit analog to digital circuit of a continuous time sigma delta converter. The method further includes limiting a noise generation by adaptively selecting a digital to analog converter element out of a plurality of digital to analog converter elements in accordance with an input signal magnitude. In addition, the method includes implementing a selected digital to analog converter element to generate an analog signal.
摘要翻译：公开了一种信号相关多位数字到模拟信号转换的几种方法和噪声限制系统。示例性实施例提供了一种方法，其包括接收连续时间Σ-Δ转换器的多位模拟数字电路的输出。该方法还包括根据输入信号幅度自适应地选择多个数模转换器元件中的数模转换器元件来限制噪声产生。此外，该方法包括实现所选择的数模转换器元件以产生模拟信号。

65. 发明申请

US20100066577A1 DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译： DELTA-SIGMA模拟到数字转换器
公开(公告)号：US20100066577A1
公开(公告)日：2010-03-18
申请号：US12485924
申请日：2009-06-17
申请人： Sheng-Jui Huang
发明人： Sheng-Jui Huang
IPC分类号： H03M3/00
CPC分类号： H03F3/45475 , H03F1/0277 , H03F3/211 , H03F3/45179 , H03F3/4565 , H03F3/45932 , H03F2200/408 , H03F2203/45366 , H03F2203/45418 , H03F2203/45424 , H03F2203/45514 , H03F2203/45562 , H03F2203/45594 , H03F2203/45644 , H03H11/1252 , H03H11/1291 , H03M1/0663 , H03M1/0809 , H03M1/206 , H03M1/361 , H03M1/806 , H03M3/424 , H03M3/448 , H03M3/464
摘要： An exemplary continuous-time delta-sigma analog-to-digital converter includes a loop filter, a quantizer, a dynamic element matching circuit, a latch, and a digital-to-analog converter (DAC). The loop filter contains a plurality of integrators coupled in series, including a first integrator and a second integrator; a first positive feedback resistive element, placed in a first positive feedback path between a first output node of the second integrator and a first input node of the first integrator; and a first negative feedback resistive element, placed in a first negative feedback path between a second output node of the second integrator and the first second input node of the first integrator. The quantizer is implemented using a domino quantizer. The DAC contains a plurality of DAC units each having a capacitive device, a resistive device, and a switch device coupled between the capacitive device and the resistive device.
摘要翻译：示例性连续时间Δ-Σ模数转换器包括环路滤波器，量化器，动态元件匹配电路，锁存器和数模转换器（DAC）。环路滤波器包括串联耦合的多个积分器，包括第一积分器和第二积分器; 第一正反馈电阻元件，放置在第二积分器的第一输出节点与第一积分器的第一输入节点之间的第一正反馈路径中; 以及第一负反馈电阻元件，放置在第二积分器的第二输出节点与第一积分器的第一第二输入节点之间的第一负反馈路径中。量化器使用多米诺量化器实现。 DAC包含多个DAC单元，每个DAC单元均具有电容性器件，电阻器件和耦合在电容器件和电阻器件之间的开关器件。

66. 发明授权

US07379012B2 Capacitive digital to analog and analog to digital converters 有权
标题翻译：电容式数模转换器和模数转换器
公开(公告)号：US07379012B2
公开(公告)日：2008-05-27
申请号：US11481477
申请日：2006-07-06
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： H03M1/12
CPC分类号： H03M1/682 , H03M1/168 , H03M1/46 , H03M1/765 , H03M1/804 , H03M1/806
摘要： A pipelined analog-to-digital converter (ADC) comprises a first stage that receives an input voltage signal and that comprises an analog-to-digital converter (ADC). The ADC includes an amplifier having an input and an output. N capacitances are connected in parallel and include first ends that selectively communicate with the input and second ends. N switches selectively connect the second ends of the N capacitances to the voltage input during a first phase, one of the second ends of the N capacitances to the output of the amplifier during a second phase, and others of the second ends of the N capacitances to one of a voltage reference and a reference potential during the second phase. A second stage communicates with the output the amplifier.
摘要翻译：流水线模数转换器（ADC）包括接收输入电压信号并包括模数转换器（ADC）的第一级。 ADC包括具有输入和输出的放大器。 N个电容并联连接并且包括选择性地与输入端和第二端连通的第一端。 N个开关选择性地将N个电容的第二端连接到第一阶段期间的电压输入，N个电容的第二端中的一个在第二阶段期间连接到放大器的输出，并且N个电容的第二端中的另一个到第二阶段期间的电压参考和参考电位之一。第二级与放大器的输出通信。

67. 发明申请

US20070216558A1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US20070216558A1
公开(公告)日：2007-09-20
申请号：US11657485
申请日：2007-01-25
申请人： Hiroyuki Tsunakawa , Akihiro Kitagawa
发明人： Hiroyuki Tsunakawa , Akihiro Kitagawa
IPC分类号： H03M1/66
CPC分类号： H03M1/466 , H03M1/682 , H03M1/765 , H03M1/806
摘要： One input terminals of switches respectively coupled to capacitors of a capacitance array type D/A converter configured as a main DAC are coupled to a first external terminal of an IC. On the other hand, a current switching type D/A converter of a resistance string type D/A converter configured as a sub DAC that causes a DC current to flow therethrough is coupled to a second external terminal of the IC.
摘要翻译：分别耦合到配置为主DAC的电容阵列型D / A转换器的电容器的开关的一个输入端子耦合到IC的第一外部端子。另一方面，构成为使DC电流流过的副DAC的电阻串型D / A转换器的电流开关型D / A转换器与IC的第二外部端子耦合。

68. 发明授权

US07095350B2 DA converter circuit provided with DA converter of segment switched capacitor type 失效
标题翻译： DA转换电路配有片段开关电容型DA转换器
公开(公告)号：US07095350B2
公开(公告)日：2006-08-22
申请号：US11157923
申请日：2005-06-22
申请人： Hiroyuki Hagiwara , Haruo Kobayashi , Hao San , Atsushi Wada
发明人： Hiroyuki Hagiwara , Haruo Kobayashi , Hao San , Atsushi Wada
IPC分类号： H03M1/66 , H03M3/00
CPC分类号： H03M1/0665 , H03M1/806 , H03M3/43 , H03M3/464
摘要： A DA converter circuit is provided for use in a ΔΣ AD modulator. The DA converter circuit includes a DA converter of segment switched capacitor type. The DA converter includes an operational amplifier, capacitors as connected in parallel to each other to supply electric charges to the operational amplifier, an electrically charging switch for switching of electrically charging electric charges onto the respective capacitors or not, and an electrically discharging switch for switching or not electrically discharging electric charges from the respective capacitors or not. A switch device performs either one of the electrically charging, the electrically discharging, grounding, and polarity inversion onto the respective capacitors. A controller controls the electrically charging switch, the electrically discharging switch and the switch device to execute a process of second-order DWA algorithm for performing a second-order noise shaping of a non-linearity of the DA converter circuit.
摘要翻译：提供了用于DeltaSigma AD调制器的DA转换器电路。 DA转换器电路包括段转换电容器类型的DA转换器。 DA转换器包括运算放大器，彼此并联连接的电容器，以向运算放大器提供电荷，用于将充电电荷转换到各个电容器上的充电开关，以及用于切换的放电开关或不从各个电容器中电荷放电。开关装置对各个电容器进行充电，放电，接地和极性反转之一。控制器控制充电开关，放电开关和开关装置，以执行用于执行DA转换器电路的非线性的二阶噪声整形的二阶DWA算法的处理。

69. 发明授权

US06879277B1 Differential pipelined analog to digital converter with successive approximation register subconverter stages 有权
标题翻译：差分流水线模数转换器，具有逐次逼近寄存器子转换器级
公开(公告)号：US06879277B1
公开(公告)日：2005-04-12
申请号：US10682301
申请日：2003-10-09
申请人： Qi Cai
发明人： Qi Cai
IPC分类号： H03M1/06 , H03M1/12 , H03M1/14 , H03M1/16 , H03M1/34 , H03M1/46 , H03M1/80
CPC分类号： H03M1/164 , H03M1/0695 , H03M1/46 , H03M1/804 , H03M1/806
摘要： Pipelined analog to digital conversion systems are provided having cascaded multi-bit successive approximation register subconverter stages. Capacitor arrays are provided in the subconverter stages, where switching logic selectively couples the capacitors to operate in sample, conversion, and residue amplification modes for generating multi-bit subconverter digital outputs and analog subconverter residue outputs. In one implementation, the capacitors are switched according to a thermometer code to reduce differential converter non-linearity, and the first subconverter stage gain is reduced to improve the conversion system bandwidth.
摘要翻译：提供了流水线模数转换系统，其具有级联的多位逐次逼近寄存器子转换器级。在次级转换器级中提供电容器阵列，其中开关逻辑选择性地耦合电容器以在采样，转换和残余放大模式下操作，用于产生多位子转换器数字输出和模拟子转换器残余输出。在一个实现中，根据温度计代码切换电容器以减小差分转换器的非线性，并且减小第一子转换器级增益以提高转换系统带宽。

70. 发明授权

US06873278B1 Method and apparatus for use in switched capacitor systems 有权
标题翻译：用于开关电容器系统的方法和装置
公开(公告)号：US06873278B1
公开(公告)日：2005-03-29
申请号：US09575561
申请日：2000-05-21
申请人： Paul F. Ferguson, Jr. , Xavier S. Haurie , Gabor C. Temes
发明人： Paul F. Ferguson, Jr. , Xavier S. Haurie , Gabor C. Temes
IPC分类号： H03F3/70 , H03M1/68 , H03M1/80 , H03M1/66
CPC分类号： H03M1/682 , H03M1/46 , H03M1/806
摘要： Systems and methods receive a digital signal and generate an analog signal indicative thereof. In one embodiment, a system includes a DAC that receives a multi-bit digital signal, generates at least two analog signals each indicative of the value of the multi-bit digital signal, and filters two or more of the at least two analog signals. In another embodiment, a system includes a DAC that receives digital input signals at an input data rate and outputs analog signals Indicative of the digital signals to a signal conditioning stage at an output data rate different the input data mute.
摘要翻译：系统和方法接收数字信号并产生指示其的模拟信号。在一个实施例中，系统包括DAC，其接收多位数字信号，产生每个指示多位数字信号的值的至少两个模拟信号，并且对至少两个模拟信号中的两个或更多个进行滤波。在另一个实施例中，系统包括DAC，其以输入数据速率接收数字输入信号，并以与输入数据静音不同的输出数据速率将指示数字信号的模拟信号输出到信号调节级。

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