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1. 发明申请

US20120112944A1 MULTIPLYING DAC AND A METHOD THEREOF 有权
标题翻译：多功能DAC及其方法
公开(公告)号：US20120112944A1
公开(公告)日：2012-05-10
申请号：US12941510
申请日：2010-11-08
申请人： Soon-Jyh Chang , Jin-Fu Lin
发明人： Soon-Jyh Chang , Jin-Fu Lin
IPC分类号： H03M1/66
CPC分类号： H03M1/0653 , H03M1/806
摘要： The present invention is directed to a multiplying digital-to-analog converter (MDAC) and its method. First ends of capacitors are electrically coupled to an inverting input node of an amplifier, wherein two of the capacitors are alternatively configured as a feedback capacitor. Each capacitor is composed of at least two sub-capacitors. Second ends of capacitors are electrically coupled to an input signal via a number of sampling switches, and the second ends of the capacitors are electrically coupled to DAC voltages respectively via a number of amplifying switches. A sorting circuit is configured to sort the sub-capacitors, wherein the sorted sub-capacitors are then paired in a manner such that variance of mismatch among the sub-capacitors is thus averaged.
摘要翻译：本发明涉及一种乘法数模转换器（MDAC）及其方法。电容器的第一端电耦合到放大器的反相输入节点，其中两个电容器被配置为反馈电容器。每个电容器由至少两个子电容器组成。电容器的第二端通过多个采样开关电耦合到输入信号，并且电容器的第二端分别经由多个放大开关电耦合到DAC电压。排序电路被配置为对子电容器进行排序，其中分选的子电容器然后被配对，使得子电容器之间的失配的变化因此被平均化。

2. 发明申请

US20100085227A1 Stage-Resolution Scalable Opamp-Sharing Technique for Pipelined/Cyclic ADC 有权
标题翻译：流水线/循环ADC的阶段分辨率可扩展运算放大器共享技术
公开(公告)号：US20100085227A1
公开(公告)日：2010-04-08
申请号：US12247186
申请日：2008-10-07
申请人： Soon-Jyh Chang , Jin-Fu Lin , Chih-Haur Huang
发明人： Soon-Jyh Chang , Jin-Fu Lin , Chih-Haur Huang
IPC分类号： H03M1/10
CPC分类号： H03M1/1225 , H03M1/0695 , H03M1/162 , H03M1/164 , H03M1/40 , H03M1/44
摘要： An analog-to-digital converter (ADC) for pipelined ADCs or cyclic ADCs is disclosed. The ADC includes at least one pair of two stages connected in series, and the two stages have different bits of resolution. An amplifier is shared by the pair of two stages such that the two stages operate in an interleaved manner. Accordingly, this stage-resolution scalable opamp-sharing technique is adaptable for pipelined ADC or cyclic ADC, which substantially reduces power consumption and increases operating speed.
摘要翻译：公开了一种用于流水线ADC或循环ADC的模数转换器（ADC）。 ADC包括串联连接的至少一对两级，两级具有不同的分辨率。放大器由一对两个级共享，使得两个级以交错方式操作。因此，这种阶段分辨率可扩展的运算放大器共享技术适用于流水线ADC或循环ADC，这大大降低了功耗并提高了运行速度。

3. 发明授权

US07724063B1 Integrator-based common-mode stabilization technique for pseudo-differential switched-capacitor circuits 有权
标题翻译：用于伪差分开关电容电路的基于积分器的共模稳定技术
公开(公告)号：US07724063B1
公开(公告)日：2010-05-25
申请号：US12326854
申请日：2008-12-02
申请人： Soon-Jyh Chang , Jin-Fu Lin , Chih-Haur Huang
发明人： Soon-Jyh Chang , Jin-Fu Lin , Chih-Haur Huang
IPC分类号： H03F1/02
CPC分类号： H03F3/005 , H03F3/45179 , H03F3/45183 , H03F3/45475 , H03F3/45654 , H03F2200/78 , H03F2203/45136 , H03F2203/45404 , H03F2203/45648
摘要： A pseudo-differential switched-capacitor circuit using integrator-based common-mode stabilization technique is disclosed. A pseudo-differential switched-capacitor circuit with the differential floating sampling (DFS) technique has a common-mode gain value of one (1). An integrator is electrically coupled to the differential positive/negative outputs of the DFS circuit, and the integrator feeds back integrator output to the DFS circuit by detecting common-mode voltage disturbance at the differential positive output (Vout+) and negative output (Vout−), thereby stabilizing output common-mode level of the differential positive output (Vout+) and negative output (Vout−) at a desirable level.
摘要翻译：公开了一种使用基于积分器的共模稳定技术的伪差分开关电容器电路。具有差分浮动采样（DFS）技术的伪差分开关电容电路具有1（1）的共模增益值。积分器电耦合到DFS电路的差分正/负输出，积分器通过检测差分正输出（Vout +）和负输出（Vout-）的共模电压干扰，将积分器输出反馈到DFS电路。从而将差分正输出（Vout +）和负输出（Vout-）的输出共模电平稳定在理想水平。

4. 发明申请

US20100134173A1 INTEGRATOR-BASED COMMON-MODE STABILIZATION TECHNIQUE FOR PSEUDO-DIFFERENTIAL SWITCHED-CAPACITOR CIRCUITS 有权
标题翻译：基于集成电路的共模开关电容电路的共模稳定技术
公开(公告)号：US20100134173A1
公开(公告)日：2010-06-03
申请号：US12326854
申请日：2008-12-02
申请人： Soon-Jyh Chang , Jin-Fu Lin , Chih-Haur Huang
发明人： Soon-Jyh Chang , Jin-Fu Lin , Chih-Haur Huang
IPC分类号： G06G7/184
CPC分类号： H03F3/005 , H03F3/45179 , H03F3/45183 , H03F3/45475 , H03F3/45654 , H03F2200/78 , H03F2203/45136 , H03F2203/45404 , H03F2203/45648
摘要： A pseudo-differential switched-capacitor circuit using integrator-based common-mode stabilization technique is disclosed. A pseudo-differential switched-capacitor circuit with the differential floating sampling (DFS) technique has a common-mode gain value of one (1). An integrator is electrically coupled to the differential positive/negative outputs of the DFS circuit, and the integrator feeds back integrator output to the DFS circuit by detecting common-mode voltage disturbance at the differential positive output (Vout+) and negative output (Vout−), thereby stabilizing output common-mode level of the differential positive output (Vout+) and negative output (Vout−) at a desirable level.
摘要翻译：公开了一种使用基于积分器的共模稳定技术的伪差分开关电容器电路。具有差分浮动采样（DFS）技术的伪差分开关电容电路具有1（1）的共模增益值。积分器电耦合到DFS电路的差分正/负输出，积分器通过检测差分正输出（Vout +）和负输出（Vout-）的共模电压干扰，将积分器输出反馈到DFS电路。从而将差分正输出（Vout +）和负输出（Vout-）的输出共模电平稳定在理想水平。

5. 发明授权

US08390501B2 Successive approximation register ADC with a window predictive function 有权
标题翻译：具有窗口预测功能的逐次逼近寄存器ADC
公开(公告)号：US08390501B2
公开(公告)日：2013-03-05
申请号：US13096908
申请日：2011-04-28
申请人： Soon-Jyh Chang , Guan-Ying Huang , Chun-Cheng Liu , Chung-Ming Huang , Jin-Fu Lin , Chih-Haur Huang
发明人： Soon-Jyh Chang , Guan-Ying Huang , Chun-Cheng Liu , Chung-Ming Huang , Jin-Fu Lin , Chih-Haur Huang
IPC分类号： H03M1/34
CPC分类号： H03M1/462 , H03M1/466
摘要： A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window. The SAR controller decodes the outputs of the first and second coarse comparators and the fine comparator to obtain a converted output of the SAR ADC.
摘要翻译：公开了逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。第一和第二电容器DAC分别接收第一和第二输入信号。第一粗略比较器将第一电容器DAC的输出与窗口参考电压进行比较，第二粗略比较器将第二电容器DAC的输出与窗口参考电压进行比较，精细比较器将第一电容器DAC的输出与第二电容DAC的输出。 SAR控制器接收第一和第二粗略比较器的输出，以确定第一和第二电容器DAC的输出是否在由窗口参考电压确定的预测窗口内。当第一电容器DAC和第二电容器DAC的输出被确定为在预测窗口内时，SAR控制器绕过至少一个SAR模数转换阶段。 SAR控制器解码第一和第二粗略比较器和精细比较器的输出，以获得SAR ADC的转换输出。

6. 发明授权

US08217819B2 Multiplying DAC and a method thereof 有权
标题翻译：乘法DAC及其方法
公开(公告)号：US08217819B2
公开(公告)日：2012-07-10
申请号：US12941510
申请日：2010-11-08
申请人： Soon-Jyh Chang , Jin-Fu Lin
发明人： Soon-Jyh Chang , Jin-Fu Lin
IPC分类号： H03M1/66
CPC分类号： H03M1/0653 , H03M1/806
摘要： The present invention is directed to a multiplying digital-to-analog converter (MDAC) and its method. First ends of capacitors are electrically coupled to an inverting input node of an amplifier, wherein two of the capacitors are alternatively configured as a feedback capacitor. Each capacitor is composed of at least two sub-capacitors. Second ends of capacitors are electrically coupled to an input signal via a number of sampling switches, and the second ends of the capacitors are electrically coupled to DAC voltages respectively via a number of amplifying switches. A sorting circuit is configured to sort the sub-capacitors, wherein the sorted sub-capacitors are then paired in a manner such that variance of mismatch among the sub-capacitors is thus averaged.
摘要翻译：本发明涉及一种乘法数模转换器（MDAC）及其方法。电容器的第一端电耦合到放大器的反相输入节点，其中两个电容器被配置为反馈电容器。每个电容器由至少两个子电容器组成。电容器的第二端通过多个采样开关电耦合到输入信号，并且电容器的第二端分别经由多个放大开关电耦合到DAC电压。排序电路被配置为对子电容器进行排序，其中分选的子电容器然后被配对，使得子电容器之间的失配的变化被平均化。

7. 发明授权

US07924204B2 Stage-resolution scalable opamp-sharing technique for pipelined/cyclic ADC 有权
标题翻译：流水线/循环ADC的阶段分辨率可扩展运算放大器共享技术
公开(公告)号：US07924204B2
公开(公告)日：2011-04-12
申请号：US12247186
申请日：2008-10-07
申请人： Soon-Jyh Chang , Jin-Fu Lin , Chih-Haur Huang
发明人： Soon-Jyh Chang , Jin-Fu Lin , Chih-Haur Huang
IPC分类号： H03M1/38
CPC分类号： H03M1/1225 , H03M1/0695 , H03M1/162 , H03M1/164 , H03M1/40 , H03M1/44
摘要： An analog-to-digital converter (ADC) for pipelined ADCs or cyclic ADCs is disclosed. The ADC includes at least one pair of two stages connected in series, and the two stages have different bits of resolution. An amplifier is shared by the pair of two stages such that the two stages operate in an interleaved manner. Accordingly, this stage-resolution scalable opamp-sharing technique is adaptable for pipelined ADC or cyclic ADC, which substantially reduces power consumption and increases operating speed.
摘要翻译：公开了一种用于流水线ADC或循环ADC的模数转换器（ADC）。 ADC包括串联连接的至少一对两个级，两级具有不同的分辨率。放大器由一对两个级共享，使得两个级以交错方式操作。因此，这种阶段分辨率可扩展的运算放大器共享技术适用于流水线ADC或循环ADC，这大大降低了功耗并提高了运行速度。

8. 发明授权

US08416116B2 Successive approximation analog-to-digital converter having auxiliary prediction circuit and method thereof 有权
标题翻译：具有辅助预测电路的逐次近似模数转换器及其方法
公开(公告)号：US08416116B2
公开(公告)日：2013-04-09
申请号：US13052462
申请日：2011-03-21
申请人： Soon-Jyh Chang , Chun-Cheng Liu , Guan-Ying Huang
发明人： Soon-Jyh Chang , Chun-Cheng Liu , Guan-Ying Huang
IPC分类号： H03M1/12
CPC分类号： H03M1/002 , H03M1/0682 , H03M1/466
摘要： The configurations and adjusting method of a successive approximation analog-to-digital converter (SAR ADC) are provided. The provided SAR ADC includes at least one capacitor with a first and a second terminals, and a plurality of bits, each of which is connected to the at least one capacitor, wherein the first terminal receives an input signal, and the second terminal selectively receives one of a first and a second reference voltages, and a first comparator receiving an adjustable third reference voltage and a first voltage value generated by the input signal, wherein a connection of the second terminal of each the capacitor of the capacitor array is switched when the first voltage value is larger than the third reference voltage.
摘要翻译：提供了逐次逼近模数转换器（SAR ADC）的配置和调整方法。所提供的SAR ADC包括具有第一和第二端子的至少一个电容器和多个位，每个电容器连接到至少一个电容器，其中第一端子接收输入信号，并且第二端子选择性地接收第一参考电压和第二参考电压之一，以及接收可调节的第三参考电压和由输入信号产生的第一电压值的第一比较器，其中当电容器阵列的每个电容器的第二端子的连接被切换时第一电压值大于第三参考电压。

9. 发明申请

US20090112499A1 DEVICE FOR JITTER MEASUREMENT AND METHOD THEREOF 有权
标题翻译：用于抖动测量的设备及其方法
公开(公告)号：US20090112499A1
公开(公告)日：2009-04-30
申请号：US12117176
申请日：2008-05-08
申请人： An-Sheng Chao , Soon-Jyh Chang , Chih-Haur Huang , Kuo-Chan Huang , Shih-Ming Luo
发明人： An-Sheng Chao , Soon-Jyh Chang , Chih-Haur Huang , Kuo-Chan Huang , Shih-Ming Luo
IPC分类号： G01R29/26
CPC分类号： G01R31/31709
摘要： The device for jitter measurement and a method thereof are provided. The device for jitter measure includes a signal retrieving module, a signal amplifying module, an edge detecting module, and a time-to-digital converting module. The signal retrieving module receives a signal-under-test, and retrieves a first pulse signal having a pulse width equal to a period of the signal-under-test. The signal amplifying module amplifies the pulse width of the first pulse signal and thereby generates a second pulse signal. The edge detecting module detects a rising edge and a falling edge of the second pulse signal, and generates a first indication signal and a second indication signal according to the respective detected results. The time-to-digital converting module converts the pulse width of the second pulse signal existed in time domain to a digital signal according to the first indication signal and the second indication signal.
摘要翻译：提供抖动测量装置及其方法。用于抖动测量的装置包括信号检索模块，信号放大模块，边缘检测模块和时间 - 数字转换模块。信号检索模块接收待测信号，并检索具有等于被测信号的周期的脉冲宽度的第一脉冲信号。信号放大模块放大第一脉冲信号的脉冲宽度，从而产生第二脉冲信号。边缘检测模块检测第二脉冲信号的上升沿和下降沿，并根据各个检测结果生成第一指示信号和第二指示信号。时间 - 数字转换模块根据第一指示信号和第二指示信号将时域中存在的第二脉冲信号的脉冲宽度转换为数字信号。

10. 发明授权

US08477058B2 Successive approximation analog to digital converter with a direct switching technique for capacitor array through comparator output and method thereof 有权
标题翻译：通过比较器输出的电容器阵列的直接开关技术的逐次逼近模数转换器及其方法
公开(公告)号：US08477058B2
公开(公告)日：2013-07-02
申请号：US13272110
申请日：2011-10-12
申请人： Soon-Jyh Chang , Guan-Ying Huang , Chung-Ming Huang
发明人： Soon-Jyh Chang , Guan-Ying Huang , Chung-Ming Huang
IPC分类号： H03M1/34
CPC分类号： H03M1/462 , H03M1/466
摘要： A method for a successive approximation register ADC which includes at least one capacitor array and a plurality of switches is provided, in which the capacitors of the capacitor array are one-to-one corresponding to the switches. The method includes the following steps: firstly, at least one multiplexer is configured. Then, a first comparison voltage is outputted based on the terminal voltages on the terminals of the capacitor array, and a comparison result is outputted according to the first comparison voltage and a second comparison voltage. Afterwards, a sequence of comparisons is controlled based on the comparison result to enter into a sequence of comparison phases. Finally, the switches are orderly selected, by the multiplexer based on the comparison phases, to switch directly according to the comparison result.
摘要翻译：提供一种包括至少一个电容器阵列和多个开关的逐次逼近寄存器ADC的方法，其中电容器阵列的电容器对应于开关一一对应。该方法包括以下步骤：首先配置至少一个多路复用器。然后，基于电容器阵列的端子上的端子电压输出第一比较电压，并且根据第一比较电压和第二比较电压输出比较结果。之后，根据比较结果控制比较序列，进入比较阶段。最后，通过多路复用器根据比较阶段有序地选择开关，根据比较结果直接切换。

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