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61. 发明申请

US20060022726A1 Method of switching PLL characteristics and PLL circuit 失效
标题翻译：切换PLL特性和PLL电路的方法
公开(公告)号：US20060022726A1
公开(公告)日：2006-02-02
申请号：US11189115
申请日：2005-07-26
申请人： Masakatsu Maeda
发明人： Masakatsu Maeda
IPC分类号： H03L7/06
CPC分类号： H03L7/093 , H03L7/0891 , H03L7/107 , H03L7/1075 , H03L7/18 , H03L2207/04
摘要： A loop filter which is a component of a PLL circuit includes a switching element for switching a capacitance value which connects and disconnects a second capacitive element to a first capacitive element according to a natural angular frequency switching signal, and a switching element for switching a resistance value which short-circuits and opens between both ends of a resistance element according to a natural angular frequency switching signal in order to keep a damping factor at a constant value. It further includes an operational amplifier for charging the second capacitive element at the same potential as the first capacitive element when the second capacitive element is isolated from the first capacitive element.
摘要翻译：作为PLL电路的分量的环路滤波器包括用于根据自然角频率切换信号切换连接和断开第二电容元件到第一电容元件的电容值的开关元件，以及用于切换电阻的开关元件根据固有角频率切换信号在电阻元件的两端之间短路和断开的值，以将阻尼因子保持在恒定值。还包括一个运算放大器，用于当第二电容元件与第一电容元件隔离时，使与第一电容元件相同电位的第二电容元件充电。

62. 发明申请

US20050156277A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050156277A1
公开(公告)日：2005-07-21
申请号：US11011788
申请日：2004-12-15
申请人： Hideo Nakano , Shoji Yoshida , Masakatsu Maeda
发明人： Hideo Nakano , Shoji Yoshida , Masakatsu Maeda
IPC分类号： H01L21/822 , H01L23/522 , H01L23/528 , H01L27/04 , H01L27/06 , H01L27/08 , H01L29/94 , H01L29/00
CPC分类号： H01L29/94 , H01L23/5223 , H01L23/5286 , H01L24/48 , H01L24/49 , H01L27/0635 , H01L27/0811 , H01L2224/48091 , H01L2224/49 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/01082 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： There is provided a semiconductor device, wherein a digital circuit region and an analog circuit region are located independently. A power supply wiring and a ground wiring are placed on the periphery of each circuit region and are connected to elements in each circuit region. A MOS capacitor is formed under the power supply wiring and the ground wiring. The terminals of the MOS capacity are connected to the power supply wiring and the ground wiring. Pads are placed in each circuit region surrounded by the power supply wiring, the ground wiring, and the MOS capacitor and are connected to the elements of each circuit region.
摘要翻译：提供了一种半导体器件，其中数字电路区域和模拟电路区域独立地定位。电源布线和接地布线被放置在每个电路区域的周边上并且连接到每个电路区域中的元件。在电源布线和接地布线下面形成MOS电容器。 MOS电容的端子连接到电源线和接地线。垫被放置在由电源布线，接地布线和MOS电容器包围的每个电路区域中，并且连接到每个电路区域的元件。

63. 外观设计

USD391721S Electric iron 失效
公开(公告)号：USD391721S
公开(公告)日：1998-03-03
申请号：US65611
申请日：1997-01-30
申请人： Osamu Kondo , Toru Abe , Masakatsu Maeda
设计人： Osamu Kondo , Toru Abe , Masakatsu Maeda

64. 外观设计

USD341516S Automatic bread maker 失效
公开(公告)号：USD341516S
公开(公告)日：1993-11-23
申请号：US851144
申请日：1992-03-13
申请人： Masanori Hamada , Masakatsu Maeda , Kumiko Ito
设计人： Masanori Hamada , Masakatsu Maeda , Kumiko Ito

65. 外观设计

USD341515S Automatic bread maker 失效
公开(公告)号：USD341515S
公开(公告)日：1993-11-23
申请号：US850781
申请日：1992-03-13
申请人： Masanori Hamada , Masakatsu Maeda , Kumiko Ito , Takako Tsubaki
设计人： Masanori Hamada , Masakatsu Maeda , Kumiko Ito , Takako Tsubaki

66. 发明授权

US08433267B2 Amplitude modulator 有权
标题翻译：幅度调制器
公开(公告)号：US08433267B2
公开(公告)日：2013-04-30
申请号：US13380687
申请日：2010-04-08
申请人： Masakatsu Maeda , Taichi Ikedo
发明人： Masakatsu Maeda , Taichi Ikedo
IPC分类号： H04B1/04
CPC分类号： H04L27/04 , H03C1/02 , H03C1/06 , H04L27/12
摘要： An amplitude modulator comprises: a signal processing section for receiving a source signal for wide bandwidth use, splitting the source signal into two source signals for lower frequency use and for higher frequency use, respectively, signal processing the two source signals individually, and outputting a lower-frequency-use source signal and a higher-frequency-use source signal; a first modulation section for modulating the lower-frequency-use source signal and outputting a lower-frequency-use modulation signal; a second modulation section for modulating the higher-frequency-use source signal and outputting a higher-frequency-use modulation signal; a synthesis output section for inputting the lower-frequency-use modulation signal to a first input terminal, the input thereof causing extraction of only a lower-frequency component, for inputting the higher-frequency-use modulation signal to a second input terminal, the input thereof causing extraction of only a higher-frequency component, for synthesizing the higher-frequency component and the lower-frequency component, and for outputting a modulated signal corresponding to the source signal for wide bandwidth use, to a next step.
摘要翻译：振幅调制器包括：信号处理部分，用于接收用于宽带宽使用的源信号，将源信号分别分成用于较低频率使用和较高频率使用的两个源信号，分别对两个源信号进行信号处理，并输出较低频率的源信号和较高频率的源信号; 第一调制部分，用于调制较低频率使用的源信号并输出较低频率的调制信号; 第二调制部分，用于调制高频用途信号并输出较高频率的调制信号; 合成输出部分，用于将低频用调制信号输入到第一输入端，其输入仅引起较低频分量，用于将较高频率的调制信号输入到第二输入端，其输入引起仅提取较高频率分量，用于合成高频分量和较低频分量，并输出对应于用于宽带宽使用的源信号的调制信号到下一步骤。

67. 发明申请

US20120217639A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的半导体器件和制造方法
公开(公告)号：US20120217639A1
公开(公告)日：2012-08-30
申请号：US13499652
申请日：2010-09-02
申请人： Masahiro Sugimoto , Akinori Seki , Akira Kawahashi , Yasuo Takahashi , Masakatsu Maeda
发明人： Masahiro Sugimoto , Akinori Seki , Akira Kawahashi , Yasuo Takahashi , Masakatsu Maeda
IPC分类号： H01L23/482 , H01L21/74
CPC分类号： H01L29/452 , H01L21/28575 , H01L29/2003 , H01L33/0095 , H01L33/32 , H01L33/40
摘要： A manufacturing method of a semiconductor device including an electrode having low contact resistivity to a nitride semiconductor is provided. The manufacturing method includes a carbon containing layer forming step of forming a carbon containing layer containing carbon on a nitride semiconductor layer, and a titanium containing layer forming step of forming a titanium containing layer containing titanium on the carbon containing layer. A complete solid solution Ti (C, N) layer of TiN and TiC is formed between the titanium containing layer and the nitride semiconductor layer. As a result, the titanium containing layer comes to be in ohmic contact with the nitride semiconductor layer throughout the border therebetween.
摘要翻译：提供了包括对氮化物半导体具有低接触电阻的电极的半导体器件的制造方法。制造方法包括在氮化物半导体层上形成含有碳的含碳层的含碳层形成工序和在含碳层上形成含有钛的含钛层的含钛层形成工序。在含钛层和氮化物半导体层之间形成TiN和TiC的完全固溶Ti（C，N）层。结果，含钛层在其间的整个边界处与氮化物半导体层欧姆接触。

68. 发明申请

US20100183898A1 METALLIZED SUBSTRATE AND METHOD FOR PRODUCING THE SAME 有权
标题翻译：金属化基板及其制造方法
公开(公告)号：US20100183898A1
公开(公告)日：2010-07-22
申请号：US12602828
申请日：2008-06-10
申请人： Tetsuo Imai , Osamu Yatabe , Masakatsu Maeda
发明人： Tetsuo Imai , Osamu Yatabe , Masakatsu Maeda
IPC分类号： B32B15/01 , B05D3/02 , C25D5/50 , C25D5/54
CPC分类号： H01L23/498 , B22F7/04 , B22F2998/00 , C22C5/02 , C22C5/04 , C22C19/03 , C22C27/04 , C22C32/0047 , C23C18/32 , C23C18/54 , C25D5/48 , C25D5/50 , H01L21/4853 , H01L23/15 , H01L23/49811 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48227 , H01L2224/48599 , H01L2224/48644 , H01L2224/48699 , H01L2224/48744 , H01L2224/85444 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01027 , H01L2924/01028 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15787 , H01L2924/20752 , Y10T428/12889 , H01L2924/00014 , B22F9/04 , H01L2924/00
摘要： A metallized substrate having, disposed in the order mentioned: a ceramics substrate; a high-melting point metal layer; a base nickel plating layer; a layered nickel-phosphorous plating layer; a diffusion-inhibiting plating layer; and a gold plating layer. The base nickel plating layer being any one of a nickel plating layer, a nickel-boron plating layer, or a nickel-cobalt plating layer. The diffusion-inhibiting plating layer being any one of a columnar nickel-phosphorous plating layer, a palladium-phosphorous plating layer, or a palladium plating layer. According to the above composition, even after heating the semiconductor chips in a mounted state, the metallized substrate can make the connection strength of wire bonding favorable.
摘要翻译：金属化基板，具有按照以下顺序设置的陶瓷基板; 高熔点金属层; 基底镍镀层; 层状镍 - 磷电镀层; 扩散抑制镀层; 和镀金层。基底镀镍层是镀镍层，镍 - 硼镀层或镍钴镀层中的任意一种。扩散抑制镀层是柱状镍 - 磷镀层，钯 - 磷镀层或钯镀层中的任一种。根据上述组成，即使在安装状态下加热半导体芯片之后，金属化基板也可以使引线接合的连接强度有利。

69. 发明申请

US20100102332A1 METHOD OF FORMING AN OHMIC CONTACT ON A P-TYPE 4H-SIC SUBSTRATE 有权
标题翻译：在P型4H-SIC基板上形成OHMIC接触的方法
公开(公告)号：US20100102332A1
公开(公告)日：2010-04-29
申请号：US12530901
申请日：2008-03-13
申请人： Yasuo Takahashi , Masakatsu Maeda , Akinori Seki , Akira Kawahashi , Masahiro Sugimoto
发明人： Yasuo Takahashi , Masakatsu Maeda , Akinori Seki , Akira Kawahashi , Masahiro Sugimoto
IPC分类号： H01L29/24 , H01L21/768
CPC分类号： H01L29/7813 , H01L21/0485 , H01L29/1608 , H01L29/41766 , H01L29/45 , H01L29/732 , Y10S438/931
摘要： A method of forming an Ohmic contact on a P-type 4H—SiC and an Ohmic contact formed by the same are provided. A method of forming an Ohmic contact on a P-type 4H—SiC substrate including a deposition step of successively depositing a 1 to 60 nm thick first Al layer, Ti layer, and second Al layer on a P-type 4H—SiC substrate and an alloying step of forming an alloy layer between the SiC substrate and the Ti layer through the first Al layer by heat treatment in a nonoxidizing atmosphere. An Ohmic contact on a P-type 4H—SiC substrate formed by this method is also provided.
摘要翻译：提供了在P型4H-SiC上形成欧姆接触的方法和由其形成的欧姆接触。在P型4H-SiC衬底上形成欧姆接触的方法，包括在P型4H-SiC衬底上依次沉积1至60nm厚的第一Al层，Ti层和第二Al层的沉积步骤;以及合金化步骤，通过在非氧化气氛中的热处理，通过第一Al层在SiC衬底和Ti层之间形成合金层。还提供了通过该方法形成的P型4H-SiC衬底上的欧姆接触。

70. 发明授权

US07595702B2 Modulation apparatus capable of correcting non-linearity of voltage controlled oscillator 失效
公开(公告)号：US07595702B2
公开(公告)日：2009-09-29
申请号：US11822369
申请日：2007-07-05
申请人： Masakatsu Maeda
发明人： Masakatsu Maeda
IPC分类号： H04L27/20
CPC分类号： H03C5/00 , H03C3/08
摘要： A modulation apparatus 24 comprises a monitoring section 207 operable to monitor information about a control voltage applied to a VCO 201 as control voltage information, during any period, when a low-frequency signal having a frequency within a loop band of a PLL circuit is input at least before an LPF 209, a correction table storing section 206 operable to associate the control voltage information monitored by the monitoring section 207 as information about a control voltage after correction with information about a control voltage before correction, and store the associated information as a correction table, and a correction section 204 operable to correct a control voltage applied to the VCO 201 based on the correction table stored in the correction table storing section.

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