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61. 发明申请

US20070238267A1 Epitaxy of Silicon-Carbon Substitutional Solid Solutions by Ultra-Fast Annealing of Amorphous Material 审中-公开
标题翻译：通过非晶材料的超快退火，硅 - 碳替代固溶体的外延
公开(公告)号：US20070238267A1
公开(公告)日：2007-10-11
申请号：US11308463
申请日：2006-03-28
申请人： Yaocheng Liu , Oleg Gluschenkov , Anita Madan , Kern Rim , Judson Holt
发明人： Yaocheng Liu , Oleg Gluschenkov , Anita Madan , Kern Rim , Judson Holt
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/02667 , H01L21/02524 , H01L21/2022 , H01L21/2026 , H01L21/268 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/6656 , H01L29/78 , H01L29/7848
摘要： Expitaxial substitutional solid solutions of silicon carbon can be obtained by an ultrafast anneal of an amorphous carbon-containing silicon material. The anneal is performed at a temperature above the recrystallization point, but below the melting point of the material and preferably lasts for less than 100 milliseconds in this temperature regime. The anneal is preferably a flash anneal or laser anneal. This approach is able to produce epitaxial silicon and carbon-containing materials with a substantial portion of the carbon atoms at substitutional lattice positions. The approach is especially useful in CMOS processes and other electronic device manufacture where the presence of epitaxial Si1−yCy, y
摘要翻译：可以通过非晶态含碳硅材料的超快速退火获得硅碳的外延取代固溶体。退火在高于再结晶点的温度下进行，但低于材料的熔点，并且在该温度范围内优选持续小于100毫秒。退火优选是闪光退火或激光退火。这种方法能够产生具有相当大部分碳原子在取代晶格位置的外延硅和含碳材料。该方法在CMOS工艺和其它电子器件制造中特别有用，其中外延Si 1-y C y y y的存在y <0.1对于应变工程或带隙工程是理想的。

62. 发明授权

US07227205B2 Strained-silicon CMOS device and method 有权
标题翻译：应变硅CMOS器件及方法
公开(公告)号：US07227205B2
公开(公告)日：2007-06-05
申请号：US10930404
申请日：2004-08-31
申请人： Andres Bryant , Qiqing Ouyang , Kern Rim
发明人： Andres Bryant , Qiqing Ouyang , Kern Rim
IPC分类号： H01L29/76
CPC分类号： H01L29/165 , H01L29/1054 , H01L29/24 , H01L29/7842 , H01L29/7843
摘要： The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to the device channel. The uniaxial strain can be produced in a biaxially strained substrate surface by strain inducing liners, strain inducing wells or a combination thereof. The uniaxial strain may be produced in a relaxed substrate by the combination of strain inducing wells and a strain inducing liner. The present invention also provides a means for increasing biaxial strain with strain inducing isolation regions. The present invention further provides CMOS devices in which the device regions of the CMOS substrate may be independently processed to provide uniaxially strained semiconducting surfaces in compression or tension.
摘要翻译：本发明提供半导体器件及其形成方法，其中在半导体器件的器件沟道中产生单轴应变。单轴应变可以处于张力或压缩状态，并且在平行于装置通道的方向上。单轴应变可以通过应变诱导衬片，应变诱导孔或其组合在双轴应变衬底表面中产生。单轴应变可以通过应变诱导孔和应变诱导衬垫的组合在松弛的衬底中产生。本发明还提供了用应变诱导隔离区增加双轴应变的方法。本发明还提供了CMOS器件，其中可以独立地处理CMOS衬底的器件区域以提供压缩或张力的单轴应变半导体表面。

63. 发明授权

US07132322B1 Method for forming a SiGe or SiGeC gate selectively in a complementary MIS/MOS FET device 有权
标题翻译：在互补的MIS / MOS FET器件中选择性地形成SiGe或SiGeC栅极的方法
公开(公告)号：US07132322B1
公开(公告)日：2006-11-07
申请号：US10908411
申请日：2005-05-11
申请人： Brian Joseph Greene , Kern Rim , Clement Wann
发明人： Brian Joseph Greene , Kern Rim , Clement Wann
IPC分类号： H01L21/8238 , H01L21/8242 , H01L21/336
CPC分类号： H01L21/823842 , H01L29/785
摘要： Form a dielectric layer on a semiconductor substrate. Deposit an amorphous Si film or a poly-Si film on the dielectric layer. Then deposit a SiGe amorphous-Ge or polysilicon-Ge thin film theteover. Pattern and etch the SiGe film using a selective etch leaving the SiGe thin film intact in a PFET region and removing the SiGe film exposing the top surface of the Si film in an NFET region. Anneal to drive Ge into the Si film in the PFET region. Deposit a gate electrode layer covering the SiGe film in the PFET region and cover the exposed portion of the Si film in the NFET region. Pattern and etch the gate electrode layer to form gates. Form FET devices with sidewall spacers and source regions and drains regions in the substrate aligned with the gates.
摘要翻译：在半导体衬底上形成电介质层。在介电层上沉积非晶Si膜或多晶硅膜。然后沉积SiGe非晶Ge或多晶硅Ge薄膜。使用选择性蚀刻对SiGe膜进行刻蚀和蚀刻，在PFET区域中完整地离开SiGe薄膜，并去除在NFET区域暴露Si膜顶表面的SiGe膜。退火以将Ge驱入PFET区域中的Si膜。在PFET区域中沉积覆盖SiGe膜的栅极电极层，并覆盖NFET区域中的Si膜的露出部分。图案化并蚀刻栅极电极层以形成栅极。形成具有侧壁间隔件的FET器件，并且衬底中的源极区域和漏极区域与栅极对准。

64. 发明申请

US20050236687A1 Strained silicon CMOS on hybrid crystal orientations 失效
标题翻译：应变硅CMOS在混合晶体取向上
公开(公告)号：US20050236687A1
公开(公告)日：2005-10-27
申请号：US10830347
申请日：2004-04-22
申请人： Kevin Chan , Bruce Doris , Kathryn Guarini , Meikei Ieong , Shreesh Narasimha , Alexander Reznicek , Kern Rim , Devendra Sadana , Leathen Shi , Jeffrey Sleight , Min Yang
发明人： Kevin Chan , Bruce Doris , Kathryn Guarini , Meikei Ieong , Shreesh Narasimha , Alexander Reznicek , Kern Rim , Devendra Sadana , Leathen Shi , Jeffrey Sleight , Min Yang
IPC分类号： H01L27/08 , H01L21/02 , H01L21/20 , H01L21/336 , H01L21/762 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/04 , H01L29/76 , H01L29/78 , H01L29/786
CPC分类号： H01L29/7842 , H01L21/2022 , H01L21/76275 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78687
摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.
摘要翻译：提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。该方法提供混合基板，其中至少一个器件层包括应变Si。

65. 发明授权

US07713807B2 High-performance CMOS SOI devices on hybrid crystal-oriented substrates 失效
标题翻译：高性能CMOS SOI器件在混合晶体取向衬底上
公开(公告)号：US07713807B2
公开(公告)日：2010-05-11
申请号：US11958877
申请日：2007-12-18
申请人： Bruce B. Doris , Kathryn W. Guarini , Meikei Ieong , Shreesh Narasimha , Kern Rim , Jeffrey W. Sleight , Min Yang
发明人： Bruce B. Doris , Kathryn W. Guarini , Meikei Ieong , Shreesh Narasimha , Kern Rim , Jeffrey W. Sleight , Min Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/76275 , H01L21/823807 , H01L21/84
摘要： An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.
摘要翻译：提供包含至少一个器件的集成半导体结构，所述器件形成在对于该器件最佳的第一晶体表面上，而另一器件形成在对于另一器件最佳的第二不同晶体表面上。形成集成结构的方法包括提供包括至少第一晶体取向的第一半导体层和第二不同晶体取向的第二半导体层的键合衬底。键合衬底的一部分被保护以限定第一器件区域，而键合衬底的另一部分是未受保护的。然后蚀刻键合衬底的未保护部分以暴露第二半导体层的表面，并将半导体材料重新生长在暴露表面上。在平坦化之后，在第一器件区域中形成第一半导体器件，并且在再生长材料上形成第二半导体器件。

66. 发明申请

US20080224218A1 CMOS STRUCTURE INCLUDING DIFFERENTIAL CHANNEL STRESSING LAYER COMPOSITIONS 有权
标题翻译： CMOS结构包括差分通道应力层组成
公开(公告)号：US20080224218A1
公开(公告)日：2008-09-18
申请号：US11685458
申请日：2007-03-13
申请人： Yaocheng Liu , Ricardo A. Donaton , Kern Rim
发明人： Yaocheng Liu , Ricardo A. Donaton , Kern Rim
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/66545 , H01L29/66636
摘要： A CMOS structure includes an n-FET device comprising an n-FET channel region and a p-FET device comprising a p-FET channel region. The n-FET channel region includes a first silicon material layer located upon a silicon-germanium alloy material layer. The p-FET channel includes a second silicon material layer located upon a silicon-germanium-carbon alloy material layer. The silicon-germanium alloy material layer induces a desirable tensile strain within the n-FET channel. The silicon-germanium-carbon alloy material layer suppresses an undesirable tensile strain within the p-FET channel region. A silicon-germanium-carbon alloy material from which is comprised the silicon-germanium-carbon alloy material layer may be formed by selectively incorporating carbon into a silicon-germanium alloy material from which is formed the silicon-germanium alloy material layer.
摘要翻译： CMOS结构包括包括n-FET沟道区的n-FET器件和包括p-FET沟道区的p-FET器件。 n-FET沟道区包括位于硅 - 锗合金材料层上的第一硅材料层。 p-FET沟道包括位于硅 - 锗 - 碳合金材料层上的第二硅材料层。硅 - 锗合金材料层在n-FET通道内引起所需的拉伸应变。硅 - 锗 - 合金材料层抑制了p-FET沟道区内的不希望的拉伸应变。可以通过选择性地将碳包含在形成硅 - 锗合金材料层的硅 - 锗合金材料中来形成由硅 - 锗 - 碳合金材料层构成的硅 - 锗 - 碳合金材料。

67. 发明申请

US20070278517A1 HETERO-INTEGRATED STRAINED SILICON n- AND p- MOSFETS 有权
标题翻译： HETERO-INTEGRATED应变硅n-和p- MOSFET
公开(公告)号：US20070278517A1
公开(公告)日：2007-12-06
申请号：US11840029
申请日：2007-08-16
申请人： Diane Boyd , Juan Cai , Kevin Chan , Patricia Mooney , Kern Rim
发明人： Diane Boyd , Juan Cai , Kevin Chan , Patricia Mooney , Kern Rim
IPC分类号： H01L35/26 , H01L21/20
CPC分类号： H01L29/1054 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/02664 , H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L29/7842 , Y10S438/938
摘要： The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.
摘要翻译：本发明提供半导体结构和制造用于施加MOSFET器件的这种结构的方法。以这样的方式制造半导体结构，使得制造n-MOSFET的晶片区域中的层结构不同于制造p-MOSFET的晶片的区域中的层结构。通过首先通过离子注入诸如He的光原子形成具有含Si衬底的表面的损伤区域来制造结构。然后在含有受损区域的含Si衬底上形成应变SiGe合金。然后采用退火步骤通过缺陷引发的应变弛豫引起应变SiGe合金的显着松弛。接下来，在弛豫的SiGe合金上形成诸如应变Si的应变半导体盖。

68. 发明申请

US20070228458A1 DUAL METAL INTEGRATION SCHEME BASED ON FULL SILICIDATION OF THE GATE ELECTRODE 失效
标题翻译：基于门电极全硅酸化的双金属一体化方案
公开(公告)号：US20070228458A1
公开(公告)日：2007-10-04
申请号：US11308486
申请日：2006-03-29
申请人： William Henson , Kern Rim , Jack Mandelman
发明人： William Henson , Kern Rim , Jack Mandelman
IPC分类号： H01L21/8234
CPC分类号： H01L21/823443 , H01L21/82345 , H01L21/823835 , H01L21/823842
摘要： An integration scheme that enables full silicidation (FUSI) of the nFET and pFET gate electrodes at the same time as that of the source/drain regions is provided. The FUSI of the gate electrodes eliminates the gate depletion problem that is observed with polysilicon gate electrodes. In addition, the inventive integration scheme creates different silicon thicknesses of the gate electrode just prior to silicidation. This feature of the present invention allows for fabricating nFETs and pFETs that have a band edge workfunction that is tailored for the specific device region.
摘要翻译：提供了与源极/漏极区域同时实现nFET和pFET栅电极的全硅化（FUSI）的集成方案。栅电极的FUSI消除了多晶硅栅电极观察到的栅耗尽问题。此外，本发明的集成方案刚好在硅化之前产生栅电极的不同硅厚度。本发明的该特征允许制造具有针对特定器件区域定制的带边缘功能函数的nFET和pFET。

69. 发明申请

US20070161244A1 METHOD AND APPARATUS FOR POST SILICIDE SPACER REMOVAL 有权
标题翻译：硅胶分离器去除后的方法和装置
公开(公告)号：US20070161244A1
公开(公告)日：2007-07-12
申请号：US11164417
申请日：2005-11-22
申请人： Brian J. Greene , Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Siddhartha Panda , Kern Rim , Young Way Teh
发明人： Brian J. Greene , Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Siddhartha Panda , Kern Rim , Young Way Teh
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31116 , H01L21/31144 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.
摘要翻译：后硅化物间隔物去除的方法（和装置）包括通过使用氧化物层和氮化物层中的至少一种来防止对硅化物间隔物的损害。

70. 发明授权

US07217949B2 Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) 失效
标题翻译：拉伸应变SiGe绝缘体上的应变Si MOSFET（SGOI）
公开(公告)号：US07217949B2
公开(公告)日：2007-05-15
申请号：US10883443
申请日：2004-07-01
申请人： Kevin K. Chan , Jack O. Chu , Kern Rim , Leathen Shi
发明人： Kevin K. Chan , Jack O. Chu , Kern Rim , Leathen Shi
IPC分类号： H01L29/06
CPC分类号： H01L29/78687 , H01L21/2007 , H01L29/1054 , H01L29/517 , H01L29/66742 , H01L29/7833 , H01L29/7842 , H01L29/78603
摘要： A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.
摘要翻译：提供了用作形成高性能金属氧化物半导体场效应晶体管（MOSFET）器件的模板的半导体结构。更具体地，本发明提供一种包括绝缘体上硅衬底的结构，其包括位于绝缘层顶部的拉伸应变SiGe合金层; 以及拉伸应变SiGe合金层顶部的应变Si层。本发明还提供了形成拉伸应变SGOI基板以及上述异质结构的方法。本发明的方法通过在绝缘层上直接提供拉伸应变SiGe合金层来分离应变Si层中的高应变和下层中的Ge含量的偏好。

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