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61. 发明申请

US20080179297A1 Bevel etcher with gap control 有权
标题翻译：斜角蚀刻机具有间隙控制
公开(公告)号：US20080179297A1
公开(公告)日：2008-07-31
申请号：US11698191
申请日：2007-01-26
申请人： Andrew D. Bailey , Alan M. Schoepp , Gregory Sexton , Andras Kuthi , Yunsang Kim , William S. Kennedy
发明人： Andrew D. Bailey , Alan M. Schoepp , Gregory Sexton , Andras Kuthi , Yunsang Kim , William S. Kennedy
IPC分类号： B23H1/04
CPC分类号： H01L21/0209 , H01J37/32366 , H01J37/32568 , H01J2237/335 , H01L21/67069
摘要： A device for cleaning a bevel edge of a semiconductor substrate. The device includes a lower electrode assembly that has a top surface and is adapted to support the substrate and an upper electrode assembly that has a bottom surface opposing the top surface. The lower and upper electrode assemblies generate plasma for cleaning the bevel edge of the substrate disposed between the top and bottom surfaces during operation. The device also includes a mechanism for suspending the upper electrode assembly over the lower support and adjusting the tilt angle and horizontal translation of the bottom surface relative to the top surface.
摘要翻译：一种用于清洁半导体衬底的斜边缘的装置。该装置包括具有顶表面并适于支撑基底的下电极组件和具有与顶表面相对的底表面的上电极组件。下部和上部电极组件在操作期间产生用于清洁设置在顶部和底部表面之间的衬底的斜面边缘的等离子体。该装置还包括用于将上电极组件悬挂在下支撑件上并且调节底表面相对于顶表面的倾斜角度和水平平移的机构。

62. 发明申请

US20080156772A1 METHOD AND APPARATUS FOR WAFER EDGE PROCESSING 审中-公开
标题翻译： WAF边缘加工方法与装置
公开(公告)号：US20080156772A1
公开(公告)日：2008-07-03
申请号：US11618572
申请日：2006-12-29
申请人： Yunsang Kim , Jack Chen , Grace Fang , Andrew Bailey
发明人： Yunsang Kim , Jack Chen , Grace Fang , Andrew Bailey
IPC分类号： H01L21/306 , C23F1/02
CPC分类号： H01J37/32706 , H01J37/32532 , H01J37/32623 , H01L21/02087 , H01L21/0209 , H01L21/67069
摘要： Methods and apparatus for remedying arc-related damage to the substrate during plasma bevel etching. A plasma shield is disposed above the substrate to prevent plasma, which is generated in between two annular grounded plates, from reaching the exposed metallization on the substrate. Additionally or alternatively, a carbon-free fluorinated process source gas may be employed and/or the RF bias power may be ramped up gradually during plasma generation to alleviate arc-related damage during bevel etching. Also additionally or alternatively, helium and/or hydrogen may be added to the process source gas to alleviate arc-related damage during bevel etching.
摘要翻译：在等离子体斜面蚀刻期间用于补救对基板的电弧相关损伤的方法和装置。等离子体屏蔽设置在衬底之上，以防止在两个环形接地板之间产生的等离子体到达衬底上暴露的金属化。另外或替代地，可以采用无碳氟化处理源气体和/或在等离子体产生期间逐渐斜升RF偏置功率以减轻斜面蚀刻期间的电弧相关损伤。另外或替代地，可以将氦和/或氢加入到工艺源气体中以减轻斜面蚀刻期间的电弧相关损伤。

63. 发明授权

US07256134B2 Selective etching of carbon-doped low-k dielectrics 失效
标题翻译：选择性蚀刻碳掺杂低k电介质
公开(公告)号：US07256134B2
公开(公告)日：2007-08-14
申请号：US10632873
申请日：2003-08-01
申请人： Yunsang Kim , Neungho Shin , Heeyeop Chae , Joey Chiu , Yan Ye , Fang Tian , Xiaoye Zhao
发明人： Yunsang Kim , Neungho Shin , Heeyeop Chae , Joey Chiu , Yan Ye , Fang Tian , Xiaoye Zhao
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , Y10S438/963
摘要： The present invention includes a process for selectively etching a low-k dielectric material formed on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a fluorine-rich fluorocarbon or hydrofluorocarbon gas, a nitrogen-containing gas, and one or more additive gases, such as a hydrogen-rich hydrofluorocarbon gas, an inert gas and/or a carbon-oxygen gas. The process provides a low-k dielectric to a photoresist mask etching selectivity ratio greater than about 5:1, a low-k dielectric to a barrier/liner layer etching selectivity ratio greater about 10:1, and a low-k dielectric etch rate higher than about 4000 Å/min.
摘要翻译：本发明包括使用等离子体蚀刻室中的气体混合物的等离子体来选择性地蚀刻形成在衬底上的低k电介质材料的方法。气体混合物包括富氟碳氟化合物或氢氟烃气体，含氮气体和一种或多种添加剂气体，例如富氢氢氟烃气体，惰性气体和/或碳 - 氧气体。该方法提供了大于约5:1的光致抗蚀剂掩模蚀刻选择比的低k电介质，大于10:1的低k电介质到阻挡层/衬层蚀刻选择比，以及低k电介质蚀刻速率高于约4000Å/ min。

64. 发明申请

US20060128152A1 Plasma oxidation and removal of oxidized material 失效
公开(公告)号：US20060128152A1
公开(公告)日：2006-06-15
申请号：US11076725
申请日：2005-03-09
申请人： Yunsang Kim , Andrew Bailey , Hyungsuk Yoon , Arthur Howald
发明人： Yunsang Kim , Andrew Bailey , Hyungsuk Yoon , Arthur Howald
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/32136 , H01L21/31683 , H01L21/321 , H01L21/32115 , H01L21/32135 , H01L21/32138 , H01L21/32139 , H01L21/7684 , H01L21/76865 , H01L21/76885
摘要： A method of etching a conductive layer includes converting at least a portion of the conductive layer and etching the conductive layer to substantially remove the converted portion of the conductive layer and thereby expose a remaining surface. The remaining surface has an average surface roughness of less than about 10 nm. A system for etching a conductive layer is also disclosed.

65. 发明申请

US20050023694A1 Integrated low k dielectrics and etch stops 有权
标题翻译：集成的低k电介质和蚀刻停止
公开(公告)号：US20050023694A1
公开(公告)日：2005-02-03
申请号：US10924551
申请日：2004-08-24
申请人： Claes Bjorkman , Melissa Yu , Hongqing Shan , David Cheung , Wai-Fan Yau , Kuowei Liu , Nasreen Chapra , Gerald Yin , Farhad Moghadam , Judy Huang , Dennis Yost , Betty Tang , Yunsang Kim
发明人： Claes Bjorkman , Melissa Yu , Hongqing Shan , David Cheung , Wai-Fan Yau , Kuowei Liu , Nasreen Chapra , Gerald Yin , Farhad Moghadam , Judy Huang , Dennis Yost , Betty Tang , Yunsang Kim
IPC分类号： H01L21/302 , A01C15/02 , A01C17/00 , C23C16/40 , H01L21/3065 , H01L21/31 , H01L21/311 , H01L21/312 , H01L21/316 , H01L21/768 , H01L23/522 , H01L23/48
CPC分类号： H01L21/76835 , C23C16/401 , H01L21/02126 , H01L21/022 , H01L21/02208 , H01L21/02274 , H01L21/02304 , H01L21/31116 , H01L21/31138 , H01L21/3121 , H01L21/31612 , H01L21/31633 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76829
摘要： A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.
摘要翻译：沉积和蚀刻具有低介电常数和蚀刻速率的介电层的方法，该介电层变化至少3:1以形成水平互连。电介质层中的碳或氢的量可以通过沉积条件的变化来改变，以提供低k电介质层，其可代替蚀刻停止层或在镶嵌应用中的常规电介质层。具有介电常数低于约4的两个或多个电介质层的双镶嵌结构可以沉积在单个反应器中，然后通过改变碳：氧气如一氧化碳的浓度进行蚀刻以形成垂直和水平互连。用于形成垂直互连的蚀刻气体优选地包括CO和碳氟化合物，并且CO优选从用于形成水平互连的蚀刻气体中排除。

66. 发明授权

US06686293B2 Method of etching a trench in a silicon-containing dielectric material 失效
标题翻译：在含硅介电材料中蚀刻沟槽的方法
公开(公告)号：US06686293B2
公开(公告)日：2004-02-03
申请号：US10144570
申请日：2002-05-10
申请人： Yunsang Kim , Kenny L. Doan , Claes H. Björkman , Hongqing Shan
发明人： Yunsang Kim , Kenny L. Doan , Claes H. Björkman , Hongqing Shan
IPC分类号： H01L21302
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76804 , H01L21/76808 , H01L2221/1063
摘要： Disclosed herein is a method of etching a trench in a silicon-containing dielectric material, in the absence of a trench etch-stop layer, where the silicon-containing dielectric material has a dielectric constant of about 4 or less. The method comprises exposing the dielectric material to a plasma generated from a source gas comprising a fluorine-containing etchant gas and an additive gas selected from the group consisting of carbon monoxide (CO), argon, and combinations thereof. A volumetric flow ratio of the additive gas to the fluorine-containing etchant gas is within the range of about 1.25:1 to about 20:1 (more typically, about 2.5:1 to about 20:1), depending on the particular fluorine-containing etchant gas used. The method provides good control over critical dimensions and etch profile during trench etching. Also disclosed herein is a method of forming a dual damascene structure, without the need for an intermediate etch stop layer.
摘要翻译：本文公开了一种在不存在沟槽蚀刻停止层的情况下，在含硅介电材料中蚀刻沟槽的方法，其中含硅介电材料具有约4或更小的介电常数。该方法包括将电介质材料暴露于由包含含氟蚀刻剂气体和选自一氧化碳（CO），氩气及其组合的添加剂气体的源气体产生的等离子体。添加气体与含氟蚀刻剂气体的体积流量比在约1.25:1至约20:1（更典型地为约2.5:1至约20:1）的范围内，这取决于具体的氟 - 含有腐蚀剂气体。该方法在沟槽蚀刻期间提供了对临界尺寸和蚀刻轮廓的良好控制。本文还公开了形成双镶嵌结构的方法，而不需要中间蚀刻停止层。

67. 发明授权

US06511920B2 Optical marker layer for etch endpoint determination 失效
标题翻译：用于蚀刻终点测定的光学标记层
公开(公告)号：US06511920B2
公开(公告)日：2003-01-28
申请号：US09882111
申请日：2001-06-14
申请人： Huong Thanh Nguyen , Yunsang Kim , Ellie Yieh , Li-Qun Xia
发明人： Huong Thanh Nguyen , Yunsang Kim , Ellie Yieh , Li-Qun Xia
IPC分类号： H01L2131
CPC分类号： H01L21/76832 , H01L21/76813 , H01L21/76826 , H01L21/76829 , H01L22/24 , Y10S438/931
摘要： A method of forming an optical marker layer for etch endpoint determination in integrated circuit fabrication processes is disclosed. The optical marker layer is used in conjunction with organic and/or carbon-containing material layers that are used as bulk insulating materials and barrier materials. The optical marker layer is formed on the bulk insulating material layer and/or the barrier material layer by incorporating an optical marker into the surface thereof. The optical marker is incorporated into the surface of the bulk insulating material layer and/or the barrier material layer by treating such layer with an optical marker-containing gas. The optical marker layer provides an optical marker emission spectrum when it is etched during a subsequent patterning step.
摘要翻译：公开了一种在集成电路制造工艺中形成用于蚀刻端点确定的光学标记层的方法。光学标记层与用作体绝缘材料和阻隔材料的有机和/或含碳材料层结合使用。通过在其表面上并入光学标记物，在体绝缘材料层和/或阻挡材料层上形成光学标记层。通过用含有光学标记的气体处理该层，将光学标记物结合到体绝缘材料层和/或阻挡材料层的表面中。当在随后的图案化步骤中蚀刻时，光学标记层提供光学标记发射光谱。

68. 发明授权

US06403491B1 Etch method using a dielectric etch chamber with expanded process window 失效
标题翻译：使用具有扩展工艺窗口的电介质蚀刻室的蚀刻方法
公开(公告)号：US06403491B1
公开(公告)日：2002-06-11
申请号：US09704867
申请日：2000-11-01
申请人： Jingbao Liu , Judy Wang , Takehiko Komatsu , Bryan Y Pu , Kenny L Doan , Claes Bjorkman , Melody Chang , Yunsang Kim , Hongching Shan , Ruiping Wang
发明人： Jingbao Liu , Judy Wang , Takehiko Komatsu , Bryan Y Pu , Kenny L Doan , Claes Bjorkman , Melody Chang , Yunsang Kim , Hongching Shan , Ruiping Wang
IPC分类号： H01L213065
CPC分类号： H01L21/6875 , H01J37/32522 , H01L21/31116 , H01L21/67069 , H01L21/6833 , H01L21/68757 , H01L21/68785 , H01L21/68792 , H01L21/76802 , H01L21/76807 , H01L21/76897 , H01L2924/3011
摘要： A method for etching a dielectric in a thermally controlled plasma etch chamber with an expanded processing window. The method is adapted to incorporate benefits of a the thermal control and high evacuation capability of the chamber. Etchent gases include hydrocarbons, oxygen and inert gas. Explanation is provided for enablling the use of hexafluoro-1,3-butadiene in a capacitively coupled etch plasma. The method is very useful for creating via, self aligned contacts, dual damascene, and other dielectric etch.
摘要翻译：一种用于在具有扩展的处理窗口的热控等离子体蚀刻室中蚀刻电介质的方法。该方法适于结合腔室的热控制和高排气能力的优点。 Etchent气体包括碳氢化合物，氧气和惰性气体。提供了解释在电容耦合蚀刻等离子体中使用六氟-1,3-丁二烯的方法。该方法对于创建通孔，自对准触点，双镶嵌和其他电介质蚀刻非常有用。

69. 发明授权

US08562750B2 Method and apparatus for processing bevel edge 有权
标题翻译：斜边加工方法及装置
公开(公告)号：US08562750B2
公开(公告)日：2013-10-22
申请号：US12640926
申请日：2009-12-17
申请人： Jack Chen , Yunsang Kim
发明人： Jack Chen , Yunsang Kim
IPC分类号： B08B7/04
CPC分类号： H01L21/02274 , C23C16/0245 , C23C16/04 , C23C16/509 , H01L21/02087 , H01L21/02115 , H01L21/3083 , H01L21/31144
摘要： A method and apparatus for processing a bevel edge is provided. A substrate is placed in a bevel processing chamber and a passivation layer is formed on the substrate only around a bevel region of the substrate using a passivation plasma confined in a peripheral region of the bevel processing chamber. The substrate may undergo a subsequent semiconductor process, during which the bevel edge region of the substrate is protected by the passivation layer. Alternatively, the passivation layer may be patterned using a patterning plasma formed in an outer peripheral region of the processing chamber, the patterning plasma being confined by increasing plasma confinement. The passivation layer on outer edge portion of the bevel region is removed, while the passivation layer on an inner portion of the bevel region is maintained. The bevel edge of the substrate may be cleaned using the patterned passivation layer as a protective mask.
摘要翻译：提供了一种用于处理斜边的方法和装置。将衬底放置在斜面处理室中，并且使用限制在斜面处理室的周边区域中的钝化等离子体在衬底的仅一个斜面区域周围形成钝化层。衬底可以经历随后的半导体工艺，在此期间衬底的斜边缘区域被钝化层保护。或者，可以使用在处理室的外围区域中形成的图案化等离子体对钝化层进行图案化，通过增加等离子体限制来限制图形化等离子体。去除斜面区域的外边缘部分上的钝化层，同时保持斜面区域的内部部分上的钝化层。可以使用图案化的钝化层作为保护掩模来清洁基底的斜边缘。

70. 发明授权

US08500951B2 Low-K damage avoidance during bevel etch processing 有权
标题翻译：斜角蚀刻加工期间的低K损伤避免
公开(公告)号：US08500951B2
公开(公告)日：2013-08-06
申请号：US12730146
申请日：2010-03-23
申请人： Yunsang Kim , Andrew Bailey, III , Jack Chen
发明人： Yunsang Kim , Andrew Bailey, III , Jack Chen
IPC分类号： C23F1/00 , H01L21/306
CPC分类号： H01L21/02041 , H01L21/02087 , H01L21/31116 , H01L21/31138 , H01L21/67069 , H01L21/6833
摘要： A method for etching a bevel edge of a substrate is provided. A patterned photoresist mask is formed over the etch layer. The bevel edge is cleaned comprising providing a cleaning gas comprising at least one of a CO2, CO, CxHy, H2, NH3, CxHyFz and a combination thereof, forming a cleaning plasma from the cleaning gas, and exposing the bevel edge to the cleaning plasma. Features are etched into the etch layer through the photoresist features and the photoresist mask is removed.
摘要翻译：提供了蚀刻基板的斜边缘的方法。在蚀刻层上形成图案化的光致抗蚀剂掩模。清洁斜面边缘，包括提供包括CO 2，CO，C x H y，H 2，NH 3，C x H y Fz及其组合中的至少一种的清洁气体，从清洁气体形成清洁等离子体，并将斜面边缘暴露于清洁等离子体。通过光致抗蚀剂特征将特征蚀刻到蚀刻层中，并去除光致抗蚀剂掩模。

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