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1. 发明申请

US20050023694A1 Integrated low k dielectrics and etch stops 有权
标题翻译：集成的低k电介质和蚀刻停止
公开(公告)号：US20050023694A1
公开(公告)日：2005-02-03
申请号：US10924551
申请日：2004-08-24
申请人： Claes Bjorkman , Melissa Yu , Hongqing Shan , David Cheung , Wai-Fan Yau , Kuowei Liu , Nasreen Chapra , Gerald Yin , Farhad Moghadam , Judy Huang , Dennis Yost , Betty Tang , Yunsang Kim
发明人： Claes Bjorkman , Melissa Yu , Hongqing Shan , David Cheung , Wai-Fan Yau , Kuowei Liu , Nasreen Chapra , Gerald Yin , Farhad Moghadam , Judy Huang , Dennis Yost , Betty Tang , Yunsang Kim
IPC分类号： H01L21/302 , A01C15/02 , A01C17/00 , C23C16/40 , H01L21/3065 , H01L21/31 , H01L21/311 , H01L21/312 , H01L21/316 , H01L21/768 , H01L23/522 , H01L23/48
CPC分类号： H01L21/76835 , C23C16/401 , H01L21/02126 , H01L21/022 , H01L21/02208 , H01L21/02274 , H01L21/02304 , H01L21/31116 , H01L21/31138 , H01L21/3121 , H01L21/31612 , H01L21/31633 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76829
摘要： A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.
摘要翻译：沉积和蚀刻具有低介电常数和蚀刻速率的介电层的方法，该介电层变化至少3:1以形成水平互连。电介质层中的碳或氢的量可以通过沉积条件的变化来改变，以提供低k电介质层，其可代替蚀刻停止层或在镶嵌应用中的常规电介质层。具有介电常数低于约4的两个或多个电介质层的双镶嵌结构可以沉积在单个反应器中，然后通过改变碳：氧气如一氧化碳的浓度进行蚀刻以形成垂直和水平互连。用于形成垂直互连的蚀刻气体优选地包括CO和碳氟化合物，并且CO优选从用于形成水平互连的蚀刻气体中排除。

2. 发明授权

US06858153B2 Integrated low K dielectrics and etch stops 有权
标题翻译：集成的低K电介质和蚀刻停止
公开(公告)号：US06858153B2
公开(公告)日：2005-02-22
申请号：US10011368
申请日：2001-11-05
申请人： Claes H. Bjorkman , Min Melissa Yu , Hongquing Shan , David W. Cheung , Wai-Fan Yau , Kuowei Liu , Nasreen Gazala Chapra , Gerald Yin , Farhad K. Moghadam , Judy H. Huang , Dennis Yost , Betty Tang , Yunsang Kim
发明人： Claes H. Bjorkman , Min Melissa Yu , Hongquing Shan , David W. Cheung , Wai-Fan Yau , Kuowei Liu , Nasreen Gazala Chapra , Gerald Yin , Farhad K. Moghadam , Judy H. Huang , Dennis Yost , Betty Tang , Yunsang Kim
IPC分类号： H01L21/302 , A01C15/02 , A01C17/00 , C23C16/40 , H01L21/3065 , H01L21/31 , H01L21/311 , H01L21/312 , H01L21/316 , H01L21/768 , H01L23/522 , C23F1/00
CPC分类号： H01L21/76835 , C23C16/401 , H01L21/02126 , H01L21/022 , H01L21/02208 , H01L21/02274 , H01L21/02304 , H01L21/31116 , H01L21/31138 , H01L21/3121 , H01L21/31612 , H01L21/31633 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76829
摘要： A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.
摘要翻译：沉积和蚀刻具有低介电常数和蚀刻速率的介电层的方法，该介电层变化至少3:1以形成水平互连。电介质层中的碳或氢的量可以通过沉积条件的变化来改变，以提供低k电介质层，其可代替蚀刻停止层或在镶嵌应用中的常规电介质层。具有介电常数低于约4的两个或多个电介质层的双镶嵌结构可以沉积在单个反应器中，然后通过改变碳：氧气如一氧化碳的浓度进行蚀刻以形成垂直和水平互连。用于形成垂直互连的蚀刻气体优选地包括CO和碳氟化合物，并且CO优选从用于形成水平互连的蚀刻气体中排除。

3. 发明授权

US06340435B1 Integrated low K dielectrics and etch stops 失效
标题翻译：集成的低K电介质和蚀刻停止
公开(公告)号：US06340435B1
公开(公告)日：2002-01-22
申请号：US09329012
申请日：1999-06-09
申请人： Claes H. Bjorkman , Min Melissa Yu , Hongquing Shan , David W. Cheung , Wai-Fan Yau , Kuowei Liu , Nasreen Gazala Chapra , Gerald Yin , Farhad K. Moghadam , Judy H. Huang , Dennis Yost , Betty Tang , Yunsang Kim
发明人： Claes H. Bjorkman , Min Melissa Yu , Hongquing Shan , David W. Cheung , Wai-Fan Yau , Kuowei Liu , Nasreen Gazala Chapra , Gerald Yin , Farhad K. Moghadam , Judy H. Huang , Dennis Yost , Betty Tang , Yunsang Kim
IPC分类号： C23F100
CPC分类号： H01L21/76835 , C23C16/401 , H01L21/02126 , H01L21/022 , H01L21/02208 , H01L21/02274 , H01L21/02304 , H01L21/31116 , H01L21/31138 , H01L21/3121 , H01L21/31612 , H01L21/31633 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76829
摘要： A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.
摘要翻译：沉积和蚀刻具有低介电常数和蚀刻速率的介电层的方法，该介电层变化至少3:1以形成水平互连。电介质层中的碳或氢的量可以通过沉积条件的变化来改变，以提供低k电介质层，其可代替蚀刻停止层或在镶嵌应用中的常规电介质层。具有介电常数低于约4的两个或多个电介质层的双镶嵌结构可以沉积在单个反应器中，然后通过改变碳：氧气如一氧化碳的浓度进行蚀刻以形成垂直和水平互连。用于形成垂直互连的蚀刻气体优选地包括CO和碳氟化合物，并且CO优选从用于形成水平互连的蚀刻气体中排除。

4. 发明授权

US06669858B2 Integrated low k dielectrics and etch stops 有权
公开(公告)号：US06669858B2
公开(公告)日：2003-12-30
申请号：US10011369
申请日：2001-11-05
申请人： Claes H. Bjorkman , Min Melissa Yu , Hongquing Shan , David W. Cheung , Wai-Fan Yau , Kuowei Liu , Nasreen Gazala Chapra , Gerald Yin , Farhad K. Moghadam , Judy H. Huang , Dennis Yost , Betty Tang , Yunsang Kim
发明人： Claes H. Bjorkman , Min Melissa Yu , Hongquing Shan , David W. Cheung , Wai-Fan Yau , Kuowei Liu , Nasreen Gazala Chapra , Gerald Yin , Farhad K. Moghadam , Judy H. Huang , Dennis Yost , Betty Tang , Yunsang Kim
IPC分类号： B44C122
CPC分类号： H01L21/76835 , C23C16/401 , H01L21/02126 , H01L21/022 , H01L21/02208 , H01L21/02274 , H01L21/02304 , H01L21/31116 , H01L21/31138 , H01L21/3121 , H01L21/31612 , H01L21/31633 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76829
摘要： A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.

5. 发明授权

US07227244B2 Integrated low k dielectrics and etch stops 有权
标题翻译：集成的低k电介质和蚀刻停止
公开(公告)号：US07227244B2
公开(公告)日：2007-06-05
申请号：US10924551
申请日：2004-08-24
申请人： Claes H. Bjorkman , Melissa Min Yu , Hongquing Shan , David W. Cheung , Wai-Fan Yau , Kuowei Liu , Nasreen Gazala Chapra , Gerald Yin , Farhad K. Moghadam , Judy H. Huang , Dennis Yost , Betty Tang , Yunsang Kim
发明人： Claes H. Bjorkman , Melissa Min Yu , Hongquing Shan , David W. Cheung , Wai-Fan Yau , Kuowei Liu , Nasreen Gazala Chapra , Gerald Yin , Farhad K. Moghadam , Judy H. Huang , Dennis Yost , Betty Tang , Yunsang Kim
IPC分类号： H01L23/58
CPC分类号： H01L21/76835 , C23C16/401 , H01L21/02126 , H01L21/022 , H01L21/02208 , H01L21/02274 , H01L21/02304 , H01L21/31116 , H01L21/31138 , H01L21/3121 , H01L21/31612 , H01L21/31633 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76829
摘要： A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.
摘要翻译：沉积和蚀刻具有低介电常数和蚀刻速率的介电层的方法，该介电层变化至少3:1以形成水平互连。电介质层中的碳或氢的量可以通过沉积条件的变化来改变，以提供低k电介质层，其可代替蚀刻停止层或在镶嵌应用中的常规电介质层。具有介电常数低于约4的两个或多个电介质层的双镶嵌结构可以沉积在单个反应器中，然后通过改变碳：氧气如一氧化碳的浓度进行蚀刻以形成垂直和水平互连。用于形成垂直互连的蚀刻气体优选地包括CO和碳氟化合物，并且CO优选从用于形成水平互连的蚀刻气体中排除。

6. 发明授权

US07521374B2 Method and apparatus for cleaning semiconductor substrates 失效
标题翻译：用于清洁半导体衬底的方法和装置
公开(公告)号：US07521374B2
公开(公告)日：2009-04-21
申请号：US10997194
申请日：2004-11-23
申请人： Steven Verhaverbeke , Dennis Yost , Roman Gouk
发明人： Steven Verhaverbeke , Dennis Yost , Roman Gouk
IPC分类号： H01L21/461 , H01L21/31
CPC分类号： H01L21/02052 , H01L21/31111 , H01L21/67051
摘要： According to one aspect of the present invention, a method and apparatus for cleaning a semiconductor substrate is provided. The method may include supporting a semiconductor substrate, the semiconductor substrate having a surface, and dispensing an amount of semiconductor substrate processing liquid onto the surface of the semiconductor substrate, the amount of semiconductor substrate processing liquid being such that substantially none of the semiconductor substrate processing liquid flows off the surface of the semiconductor substrate. The semiconductor substrate processing fluid may form a standing puddle on the surface of the semiconductor substrate. The semiconductor substrate may be rotated while the semiconductor substrate processing liquid is on the surface of the semiconductor substrate such that substantially all of the amount of semiconductor substrate processing liquid remains on the surface of the semiconductor substrate during said rotation.
摘要翻译：根据本发明的一个方面，提供了一种用于清洁半导体衬底的方法和装置。该方法可以包括：支撑半导体衬底，半导体衬底具有表面，以及将一定量的半导体衬底处理液体分配到半导体衬底的表面上，半导体衬底处理液体的量基本上不使用半导体衬底处理液体从半导体衬底的表面流出。半导体衬底处理流体可以在半导体衬底的表面上形成站立的水坑。当半导体衬底处理液体在半导体衬底的表面上时半导体衬底可以旋转，使得在所述旋转期间基本上所有量的半导体衬底处理液体都保留在半导体衬底的表面上。

7. 发明申请

US20070082477A1 Integrated circuit fabricating techniques employing sacrificial liners 审中-公开
标题翻译：采用牺牲衬垫的集成电路制造技术
公开(公告)号：US20070082477A1
公开(公告)日：2007-04-12
申请号：US11245712
申请日：2005-10-06
申请人： Mehul Naik , Srinivas Gandikota , Girish Dixit , Dennis Yost
发明人： Mehul Naik , Srinivas Gandikota , Girish Dixit , Dennis Yost
IPC分类号： H01L21/4763 , H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L21/76808 , H01L21/76877
摘要： The present invention provides techniques for fabricating integrated circuit structures in semiconductor wafer fabrication. A via hole is prepared in a dielectric stack having a bottom via etch stop layer. The via hole is not extended through the via etch stop layer at this stage of the process. The via hole is partly filled with a sacrificial via fill such that a recess without sacrificial via fill is formed in the top portion of the via hole. A substantially conformal sacrificial layer is deposited on the top surface of the dielectric stack and in the recess. Then, a photoresist layer is deposited on the sacrificial fill. A trench etch mask overlaying the via hole, is developed in the photoresist layer. This mask is etched through the sacrificial layer that is formed on the top surface of the dielectric stack as well as through the sacrificial fill and sacrificial layer that is present in the via hole. Additionally, the mask is employed for etching a trench partly through the dielectric layer thereby forming a trench and an underlying via hole. The via hole is then extended through the via etch stop layer. Subsequently, the photoresist layer and the sacrificial layer are removed from the top surface of the dielectric stack resulting in a trench and underlying via hole that is suitable for fabricating a dual damascene structure. Alternatively, a recess can be formed by depositing a substantially conformal sacrificial layer on the top surface of the dielectric stack and in the via hole to form a lined via hole. The lined via hole is then partly filled with a sacrificial via fill such that a recess without sacrificial via fill is formed in the top portion of the lined via hole. Next, a photoresist layer is deposited in the recess and on the sacrificial liner that is deposited on the top surface of the dielectric stack.
摘要翻译：本发明提供了在半导体晶片制造中制造集成电路结构的技术。在具有底部通孔蚀刻停止层的电介质叠层中制备通孔。在该过程的这个阶段，通孔不延伸穿过通孔蚀刻停止层。通孔部分地填充有牺牲通孔填充物，使得在通孔的顶部部分中形成没有牺牲通孔填充物的凹部。基本上共形的牺牲层沉积在电介质叠层的顶表面和凹槽中。然后，在牺牲填充物上沉积光致抗蚀剂层。在光致抗蚀剂层中显影覆盖通孔的沟槽蚀刻掩模。该掩模通过形成在电介质堆叠的顶表面上的牺牲层以及穿过存在于通孔中的牺牲填充层和牺牲层进行蚀刻。此外，掩模用于部分地通过介电层蚀刻沟槽，从而形成沟槽和下面的通孔。然后通孔穿过通孔蚀刻停止层。随后，从电介质堆叠的顶表面去除光致抗蚀剂层和牺牲层，产生适于制造双镶嵌结构的沟槽和下面的通孔。或者，可以通过在电介质堆叠的顶表面上和通孔中沉积基本上共形的牺牲层来形成凹槽，以形成衬里的通孔。然后将衬里的通孔部分地填充有牺牲通孔填充物，使得在衬里通孔的顶部部分中形成没有牺牲通孔填充物的凹部。接下来，将光致抗蚀剂层沉积在沉积在电介质堆叠的顶表面上的凹部和牺牲衬垫上。

8. 发明申请

US20050084206A1 Fiberoptic wavelength combiner 审中-公开
标题翻译：光纤波长组合器
公开(公告)号：US20050084206A1
公开(公告)日：2005-04-21
申请号：US10686963
申请日：2003-10-15
申请人： Mikhail Gutin , Boyd Hunter , Dennis Yost
发明人： Mikhail Gutin , Boyd Hunter , Dennis Yost
IPC分类号： G02B6/34 , G02B6/28
CPC分类号： G02B6/2817 , G02B6/29362
摘要： A fiberoptic wavelength combiner comprises: a collimating lens having a first surface and a second surface, opposite the first surface; two input optical fibers secured to the first surface, each input optical fiber conducting light at a wavelength that is different from other input optical fibers; a wedged mirror spaced from the second surface, the wedged mirror having a front surface facing the collimating lens and a rear surface, the front surface provided with a first reflective coating and the rear surface provided with a second reflective coating; and an output optical fiber secured to the first surface, whereby light from the input optical fibers is collimated by the lens and made incident on the wedged mirror and its first and second reflective coatings to thereby direct the light back through the collimating lens onto the output optical fiber. Further, a method of aligning the fiberoptic wavelength combiner is provided.
摘要翻译：光纤波长组合器包括：准直透镜，具有与第一表面相对的第一表面和第二表面; 两个输入光纤被固定到第一表面，每个输入光纤以不同于其他输入光纤的波长传导光; 楔形反射镜与第二表面间隔开，楔形反射镜具有面向准直透镜的前表面和后表面，前表面设置有第一反射涂层，后表面设置有第二反射涂层; 以及固定到第一表面的输出光纤，由此来自输入光纤的光由透镜准直并入射在楔形反射镜及其第一和第二反射涂层上，从而将光通过准直透镜引导到输出光纤。此外，提供了对准光纤波长组合器的方法。

9. 发明申请

US20080041427A1 Temperature control of a substrate during wet processes 审中-公开
标题翻译：湿法加工过程中基材的温度控制
公开(公告)号：US20080041427A1
公开(公告)日：2008-02-21
申请号：US11974825
申请日：2007-10-15
申请人： Brian Brown , Dennis Yost , James Papanu , Jianshe Tang , Alexander Ko
发明人： Brian Brown , Dennis Yost , James Papanu , Jianshe Tang , Alexander Ko
IPC分类号： B08B3/00
CPC分类号： H01L21/67248 , H01L21/67109
摘要： Embodiments of the invention provide methods of applying a liquid to a backside of a substrate to bring the substrate to the temperature of the liquid. By controlling the temperature of the substrate the temperature of the semiconductor processing liquid may be maintained at a particular temperature or a type of reaction occurring in the semiconductor processing liquid may be enhanced or maintained, such as in reactions where relatively small amounts of liquid are used or expensive chemicals are used.
摘要翻译：本发明的实施例提供了将液体施加到基底的背面以使基底达到液体温度的方法。通过控制衬底的温度，可以将半导体处理液的温度保持在特定温度，或者可以增强或维持在半导体处理液中发生的反应类型，例如在使用相对少量液体的反应中或使用昂贵的化学品。

10. 发明申请

US20060088949A1 Early detection of metal wiring reliability using a noise spectrum 失效
标题翻译：使用噪声谱的早期检测金属接线可靠性
公开(公告)号：US20060088949A1
公开(公告)日：2006-04-27
申请号：US10973552
申请日：2004-10-25
申请人： Michael Smayling , Dennis Yost
发明人： Michael Smayling , Dennis Yost
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： The present invention generally provides an apparatus and a method for inspecting a substrate in a substrate processing system. In one aspect, a voltage or current source is used in conjunction with a power density receiving device, such as a spectrometer, to inspect a substrate for various noise spectrum signatures. In one embodiment, spectral data collected from a given substrate is used to generate a current or voltage spectral signature. This spectral signature may then be compared to a reference spectral density signature to predict reliability of a feature structure of a substrate in processing and feedback to the substrate processing system for substrate processing control. Embodiments of the invention further include computer-readable media containing instructions for controlling the substrate processing system, and computer program products having computer-readable program code embodied therein for controlling the substrate processing system and inspecting defects on semiconductor features.
摘要翻译：本发明总体上提供了一种用于检查衬底处理系统中的衬底的装置和方法。在一个方面，电压源或电流源与诸如光谱仪的功率密度接收装置结合使用，以检查衬底以进行各种噪声谱特征。在一个实施例中，从给定衬底收集的光谱数据用于产生电流或电压光谱特征。然后可以将该光谱特征与参考光谱密度特征进行比较，以预测处理中的衬底的特征结构的可靠性并反馈给用于衬底处理控制的衬底处理系统。本发明的实施例还包括包含用于控制基板处理系统的指令的计算机可读介质，以及其中包含用于控制基板处理系统和检查半导体特征缺陷的计算机可读程序代码的计算机程序产品。

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