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61. 发明授权

US06184091B2 Formation of controlled trench top isolation layers for vertical transistors 失效
公开(公告)号：US06184091B2
公开(公告)日：2001-02-06
申请号：US09241756
申请日：1999-02-01
申请人： Ulrike Gruening , Jochen Beintner , Dirk Tobben , Gill Lee , Oswald Spindler , Zvonimir Gabric
发明人： Ulrike Gruening , Jochen Beintner , Dirk Tobben , Gill Lee , Oswald Spindler , Zvonimir Gabric
IPC分类号： H01L21336
CPC分类号： H01L27/10864 , H01L21/02126 , H01L21/02271 , H01L21/02304 , H01L21/31612 , H01L27/10876
摘要： A method for controlling isolation layer thickness in trenches for semiconductor devices includes the steps of providing a trench having a conductive material formed therein, forming a liner on sidewalls of the trench above the conductive material, depositing a selective oxide deposition layer on the buried strap and the sidewalls, the selective oxide deposition layer selectively growing at an increased rate on the conductive material than on the liner of the sidewalls and top surface and removing the selective oxide deposition layer except for a portion in contact with the conductive to form an isolation layer on the conductive material in the trench. A method for fabricating vertical transistors by recessing a substrate to permit increased overlap between a transistor channel and buried strap outdiffusion when the transistor is formed is also included. A semiconductor device is also disclosed.

62. 发明授权

US6093614A Memory cell structure and fabrication 失效
标题翻译：存储单元结构和制造
公开(公告)号：US6093614A
公开(公告)日：2000-07-25
申请号：US34519
申请日：1998-03-04
申请人： Ulrike Gruening , Jochen Beintner , Hans-Oliver Joachim
发明人： Ulrike Gruening , Jochen Beintner , Hans-Oliver Joachim
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A pair of memory cells for use in a DRAM are formed in a monocrystalline bulk portion of a silicon wafer by first forming a pair of vertical trenches spaced apart by a bulk portion of the wafer. After a dielectric layer is formed over the walls of each trench, the trenches are each filled with polycrystalline silicon. By a pair of recess forming and recess filling steps there is formed at the top of each trench a silicon region that was grown epitaxially with the intermediate bulk portion. Each epitaxial region is made to serve as the body of a separate transistor having its drain in the lower polysilicon fill of a trench, and its source in the monocrystalline bulk intermediate between the two epitaxial regions. The lower polysilicon fill of each trench is also made to serve as the storage node of the capacitor of each cell, with the bulk serving as the other plate of the capacitor.
摘要翻译：通过首先形成由晶片的主体部分隔开的一对垂直沟槽，在硅晶片的单晶体部分中形成用于DRAM中的一对存储单元。在每个沟槽的壁之上形成电介质层之后，沟槽各自填充有多晶硅。通过一对凹陷形成和凹陷填充步骤，在每个沟槽的顶部形成有与中间体部分外延生长的硅区域。使每个外延区域用作在沟槽的下多晶硅填充物中具有其漏极的单独晶体管的主体，并且其源于在两个外延区域之间的单晶体体中间。每个沟槽的较低多晶硅填充物也用作每个电池的电容器的存储节点，其体积用作电容器的另一个板。

63. 发明授权

US6013937A Buffer layer for improving control of layer thickness 失效
标题翻译：缓冲层，用于改善层厚度的控制
公开(公告)号：US6013937A
公开(公告)日：2000-01-11
申请号：US938196
申请日：1997-09-26
申请人： Jochen Beintner , Ulrike Gruening , Carl Radens
发明人： Jochen Beintner , Ulrike Gruening , Carl Radens
IPC分类号： H01L21/76 , H01L21/308 , H01L21/31 , H01L21/316 , H01L21/318 , H01L21/763 , H01L21/8242 , H01L27/108 , H01L29/00 , H01L21/336 , H01L21/469 , H01L29/06
CPC分类号： H01L27/1087 , H01L21/3081 , H01L21/31 , H01L21/763 , H01L27/10867 , Y10S438/97
摘要： A pad layer disposed on a semiconductor substrate 102 and a buffer layer 108 disposed within the pad layer such that the pad layer is divided into a dielectric layer 106 below the buffer layer and a mask layer 110 above the buffer layer. A method of forming layers with uniform planarity and thickness on a semiconductor chip includes the steps of providing a substrate having a thermal pad 106 formed thereon, forming a dielectric layer 106 on the thermal pad, forming a buffer layer 108 on the dielectric layer wherein the buffer layer is made from a different material than the dielectric layer and forming a mask layer 110 on the buffer layer wherein the buffer layer is made from a different material than the mask layer.
摘要翻译：设置在半导体衬底102上的衬垫层和布置在焊盘层内的缓冲层108，使得衬垫层被分为缓冲层下面的介电层106和缓冲层上方的掩模层110。在半导体芯片上形成具有均匀平坦度和厚度的层的方法包括以下步骤：提供具有形成在其上的热垫106的衬底，在热衬垫上形成电介质层106，在电介质层上形成缓冲层108，其中，缓冲层由与电介质层不同的材料制成，并在缓冲层上形成掩模层110，其中缓冲层由与掩模层不同的材料制成。

64. 发明申请

US20140167732A1 Micromechanical Electric Field Meter as a Thunderstorm Warning Device 有权
标题翻译：微机电电表作为雷暴警告装置
公开(公告)号：US20140167732A1
公开(公告)日：2014-06-19
申请号：US14100844
申请日：2013-12-09
申请人： Lutz MUELLER , Jochen Beintner
发明人： Lutz MUELLER , Jochen Beintner
IPC分类号： G01R29/12 , G01W1/16
CPC分类号： G01R29/12 , G01W1/16
摘要： A micromechanical structure, in particular a micromechanical electric field meter as a thunderstorm warning device, for detection of an electric field, comprising a substrate having a principal extension plane, a first electrode, a second electrode, and a drive assemblage for producing a relative motion of the second electrode with respect to the first electrode into an overlapping position, the first electrode and the second electrode being, in the overlapping position, disposed above one another in a projection direction extending perpendicularly to the principal extension plane of the substrate, wherein the second electrode has a defined potential for shielding the first electrode with respect to the electric field in the overlapping position.
摘要翻译：微机电结构，特别是用作雷电警报装置的微机电电场仪，用于检测电场，包括具有主延伸面的基板，第一电极，第二电极和用于产生相对运动的驱动组合所述第一电极和所述第二电极处于重叠位置，所述第一电极和所述第二电极在垂直于所述基板的主延伸平面延伸的突出方向上彼此重叠设置，其中，第二电极具有用于相对于重叠位置处的电场屏蔽第一电极的限定电位。

65. 发明授权

US08614485B2 Process for fabrication of FINFETs 有权
标题翻译： FINFET制造工艺
公开(公告)号：US08614485B2
公开(公告)日：2013-12-24
申请号：US12342655
申请日：2008-12-23
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
IPC分类号： H01L29/78
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
摘要翻译：提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离。

66. 发明授权

US07767562B2 Method of implanting using a shadow effect 有权
标题翻译：使用阴影效果进行植入的方法
公开(公告)号：US07767562B2
公开(公告)日：2010-08-03
申请号：US11235330
申请日：2005-09-26
申请人： Helmut Horst Tews , Jochen Beintner
发明人： Helmut Horst Tews , Jochen Beintner
IPC分类号： H01L21/425
CPC分类号： H01L21/823462 , H01L21/26506 , H01L21/26586 , H01L21/2822 , H01L21/823481 , H01L27/0629 , H01L27/10873 , Y10S438/981
摘要： A semiconductor body has a first portion, a second portion, and an active area located between the first portion and the second portion. The first portion and the second portion are a shallow trench isolation region having an exposed surface extending above the surface of the active area. A first ion implantation is performed at a first angle such that a first shaded area defined by the exposed surface of the first portion and the first angle is exposed to fewer ions than a first unshaded area. A second ion implantation is performed at a second angle such that a second shaded area defined by the exposed surface of the second portion and the second angle is exposed to fewer ions than a second unshaded area.
摘要翻译：半导体本体具有位于第一部分和第二部分之间的第一部分，第二部分和有源区域。第一部分和第二部分是具有在有源区域的表面上方延伸的暴露表面的浅沟槽隔离区域。以第一角度执行第一离子注入，使得由第一部分的暴露表面限定的第一阴影区域和第一角度暴露于比第一未阴影区域更少的离子。以第二角度执行第二离子注入，使得由第二部分的暴露表面限定的第二阴影区域和第二角度暴露于比第二未阴影区域更少的离子。

67. 发明授权

US07683428B2 Vertical Fin-FET MOS devices 有权
标题翻译：垂直Fin-FET MOS器件
公开(公告)号：US07683428B2
公开(公告)日：2010-03-23
申请号：US10597288
申请日：2004-01-22
申请人： Dureseti Chidambarrao , Jochen Beintner , Ramachandra Divakaruni
发明人： Dureseti Chidambarrao , Jochen Beintner , Ramachandra Divakaruni
IPC分类号： H01L27/108
CPC分类号： H01L29/78642 , H01L21/2257 , H01L29/66787
摘要： A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon “fins” (12A) that act as the transistor body. Doped source and drain regions (26A, 28A) are formed at the bottoms and tops, respectively, of the fins (12A). Gates (24A, 24B) are formed along sidewalls of the fins. Current flows vertically through the fins (12A) between the source and drain regions (26A, 28A) when an appropriate bias is applied to the gates (24A, 24B). An integrated process for forming pFET, nFET, multi-fin, single-fin, multi-gate and double-gate vertical Fin-FETs simultaneously is described.
摘要翻译：描述了一种新型的具有低接触电阻的高密度垂直Fin-FET器件。这些垂直Fin-FET器件具有用作晶体管体的垂直硅“鳍”（12A）。掺杂的源极和漏极区域（26A，28A）分别形成在鳍片（12A）的底部和顶部。盖板（24A，24B）沿翅片的侧壁形成。当适当的偏压被施加到栅极（24A，24B）时，电流垂直地流过源极和漏极区域（26A，28A）之间的鳍片（12A）。描述了同时形成pFET，nFET，多鳍，单鳍，多栅极和双栅极垂直鳍FET的集成工艺。

68. 发明申请

US20080246059A1 Device Fabrication by Anisotropic Wet Etch 失效
标题翻译：各向异性湿蚀刻器件制造
公开(公告)号：US20080246059A1
公开(公告)日：2008-10-09
申请号：US12141878
申请日：2008-06-18
申请人： Yujun Li , Kenneth T. Settlemyer , Jochen Beintner
发明人： Yujun Li , Kenneth T. Settlemyer , Jochen Beintner
IPC分类号： H01L29/772 , H01L21/306
CPC分类号： H01L21/84 , H01L21/30608 , H01L27/1203 , H01L29/045 , H01L29/66772 , H01L29/66818 , H01L29/785
摘要： A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.
摘要翻译：提出了一种制造方法和场效应器件结构，其减少源/漏电容并允许器件接触。制造基于Si的材料基座，其顶表面和其侧壁的取向方向基本上平行于基座和支撑构件的选定结晶平面。用包含氢氧化铵的各向异性溶液湿式蚀刻基座。基座的侧壁变小，在基座上形成截面减小的部分。选择减小的横截面段中的掺杂剂浓度足够高以使其提供穿过基座的电连续性。

69. 发明授权

US07323374B2 Dense chevron finFET and method of manufacturing same 有权
标题翻译：密集人字形finFET及其制造方法
公开(公告)号：US07323374B2
公开(公告)日：2008-01-29
申请号：US11162663
申请日：2005-09-19
申请人： Jochen Beintner , Thomas Ludwig , Edward Joseph Nowak
发明人： Jochen Beintner , Thomas Ludwig , Edward Joseph Nowak
IPC分类号： H01L21/00
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.
摘要翻译：用于形成finFET的方法，结构和取向程序。该方法包括：用第一掩模限定finFET的第一鳍片，并用第二掩模限定finFET的第二鳍片。该结构包括单晶半导体材料的整体第一和第二鳍片以及第一和第二鳍片的纵向轴线在相同的晶体方向上排列但彼此偏移。对准过程包括同时将栅极掩模上的对准标记对准由通过用于限定第一鳍片的第一掩模单独形成的对准靶和用于限定第二鳍片的第二掩模。

70. 发明申请

US20080006852A1 DENSE CHEVRON finFET AND METHOD OF MANUFACTURING SAME 有权
标题翻译： DENSE CHEVRON finFET及其制造方法
公开(公告)号：US20080006852A1
公开(公告)日：2008-01-10
申请号：US11857806
申请日：2007-09-19
申请人： Jochen Beintner , Thomas Ludwig , Edward Nowak
发明人： Jochen Beintner , Thomas Ludwig , Edward Nowak
IPC分类号： H01L29/78
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.
摘要翻译：用于形成finFET的方法，结构和取向程序。该方法包括：用第一掩模限定finFET的第一鳍片，并用第二掩模限定finFET的第二鳍片。该结构包括单晶半导体材料的整体第一和第二鳍片以及第一和第二鳍片的纵向轴线在相同的晶体方向上排列但彼此偏移。对准过程包括同时将栅极掩模上的对准标记对准由通过用于限定第一鳍片的第一掩模单独形成的对准靶和用于限定第二鳍片的第二掩模。

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