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1. 发明申请

US20070063276A1 DENSE CHEVRON finFET AND METHOD OF MANUFACTURING SAME 有权
标题翻译： DENSE CHEVRON finFET及其制造方法
公开(公告)号：US20070063276A1
公开(公告)日：2007-03-22
申请号：US11162663
申请日：2005-09-19
申请人： Jochen Beintner , Thomas Ludwig , Edward Nowak
发明人： Jochen Beintner , Thomas Ludwig , Edward Nowak
IPC分类号： H01L27/12 , H01L21/20
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.
摘要翻译：用于形成finFET的方法，结构和取向程序。该方法包括：用第一掩模限定finFET的第一鳍片，并用第二掩模限定finFET的第二鳍片。该结构包括单晶半导体材料的整体第一和第二鳍片以及第一和第二鳍片的纵向轴线在相同的晶体方向上排列但彼此偏移。对准过程包括同时将栅极掩模上的对准标记对准由通过用于限定第一鳍片的第一掩模单独形成的对准靶和用于限定第二鳍片的第二掩模。

2. 发明申请

US20080006852A1 DENSE CHEVRON finFET AND METHOD OF MANUFACTURING SAME 有权
标题翻译： DENSE CHEVRON finFET及其制造方法
公开(公告)号：US20080006852A1
公开(公告)日：2008-01-10
申请号：US11857806
申请日：2007-09-19
申请人： Jochen Beintner , Thomas Ludwig , Edward Nowak
发明人： Jochen Beintner , Thomas Ludwig , Edward Nowak
IPC分类号： H01L29/78
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.
摘要翻译：用于形成finFET的方法，结构和取向程序。该方法包括：用第一掩模限定finFET的第一鳍片，并用第二掩模限定finFET的第二鳍片。该结构包括单晶半导体材料的整体第一和第二鳍片以及第一和第二鳍片的纵向轴线在相同的晶体方向上排列但彼此偏移。对准过程包括同时将栅极掩模上的对准标记对准由通过用于限定第一鳍片的第一掩模单独形成的对准靶和用于限定第二鳍片的第二掩模。

3. 发明申请

US20050124099A1 SELFALIGNED SOURCE/DRAIN FINFET PROCESS FLOW 有权
标题翻译：自熔源/漏液FINFET工艺流程
公开(公告)号：US20050124099A1
公开(公告)日：2005-06-09
申请号：US10731584
申请日：2003-12-09
申请人： Jochen Beintner , Edward Nowak
发明人： Jochen Beintner , Edward Nowak
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/84 , H01L27/12 , H01L29/423 , H01L29/786 , H01L21/00
CPC分类号： H01L29/785 , H01L21/823437 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66795
摘要： A selfaligned FinFET is fabricated by defining a set of fins in a semiconductor wafer, depositing gate material over the fins, defining a gate hardmask having a thickness sufficient to withstand later etching steps, etching the gate material outside the hardmask to form the gate, depositing a conformal layer of insulator over the gate and the fins, etching the insulator anistotropically until the insulator over the fins is removed down to the substrate, the hardmask having a thickness such that a portion of the hardmask remains over the gate and sidewalls remain on the gate, and forming source and drain areas in the exposed fins while the gate is protected by the hardmask material.
摘要翻译：通过在半导体晶片中限定一组翅片来制造自对准的FinFET，在栅极上沉积栅极材料，限定具有足以承受后续蚀刻步骤的厚度的栅极硬掩模，蚀刻硬掩模外部的栅极材料以形成栅极，沉积在栅极和散热片上形成绝缘体的保形层，蚀刻绝缘子向各向异性，直到鳍片上的绝缘体向下移动到衬底，硬掩模具有使得硬掩模的一部分保留在栅极和侧壁上的厚度门，并且在暴露的翅片中形成源极和漏极区域，同时门被硬掩模材料保护。

4. 发明申请

US20070108536A1 QUASI SELF-ALIGNED SOURCE/DRAIN FinFET PROCESS 失效
标题翻译： QUASI自对准源/漏极FinFET工艺
公开(公告)号：US20070108536A1
公开(公告)日：2007-05-17
申请号：US11164215
申请日：2005-11-15
申请人： MeiKei Ieong , Thomas Ludwig , Edward Nowak , Qiqing Ouyang
发明人： MeiKei Ieong , Thomas Ludwig , Edward Nowak , Qiqing Ouyang
IPC分类号： H01L21/8244
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66818 , H01L29/785
摘要： A method of forming a semiconductor structure including a plurality of finFFET devices in which crossing masks are employed in providing a rectangular patterns to define relatively thin Fins along with a chemical oxide removal (COR) process is provided. The present method further includes a step of merging adjacent Fins by the use of a selective silicon-containing material. The present invention also relates to the resultant semiconductor structure that is formed utilizing the method of the present invention.
摘要翻译：提供了一种形成包括多个finFFET器件的半导体结构的方法，其中使用交叉掩模提供矩形图案以限定相对薄的金属丝以及化学氧化物去除（COR）工艺。本方法还包括通过使用选择性含硅材料来合并相邻的金属丝的步骤。本发明还涉及利用本发明的方法形成的所得半导体结构。

5. 发明申请

US20080042202A1 QUASI SELF-ALIGNED SOURCE/DRAIN FinFET PROCESS 审中-公开
标题翻译： QUASI自对准源/漏极FinFET工艺
公开(公告)号：US20080042202A1
公开(公告)日：2008-02-21
申请号：US11874753
申请日：2007-10-18
申请人： Meikei Ieong , Thomas Ludwig , Edward Nowak , Qiqing Ouyang
发明人： Meikei Ieong , Thomas Ludwig , Edward Nowak , Qiqing Ouyang
IPC分类号： H01L27/12
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66818 , H01L29/785
摘要： A method of forming a semiconductor structure including a plurality of finFFET devices in which crossing masks are employed in providing a rectangular patterns to define relatively thin Fins along with a chemical oxide removal (COR) process is provided. The present method further includes a step of merging adjacent Fins by the use of a selective silicon-containing material. The present invention also relates to the resultant semiconductor structure that is formed utilizing the method of the present invention.
摘要翻译：提供了一种形成包括多个finFFET器件的半导体结构的方法，其中使用交叉掩模提供矩形图案以限定相对薄的金属丝以及化学氧化物去除（COR）工艺。本方法还包括通过使用选择性含硅材料来合并相邻的金属丝的步骤。本发明还涉及利用本发明的方法形成的所得半导体结构。

6. 发明申请

US20120119681A1 LIGHT DEVICES AND SYSTEMS 审中-公开
标题翻译：光设备和系统
公开(公告)号：US20120119681A1
公开(公告)日：2012-05-17
申请号：US12946682
申请日：2010-11-15
申请人： Ken Seidl , Edward Nowak , Paul Li
发明人： Ken Seidl , Edward Nowak , Paul Li
IPC分类号： H05B37/00
CPC分类号： H05B37/0272
摘要： The present invention provides switches and sensors that automatically turn on and/or off an associated device. In particular, the present invention provides lighting devices containing switches and sensors associated with the device that power/depower the device and systems and objects containing the device.
摘要翻译：本发明提供了自动打开和/或关闭相关设备的开关和传感器。特别地，本发明提供了包含与该装置相关联的开关和传感器的照明装置，其对设备和包含该装置的系统和对象进行功率/耗尽。

7. 发明申请

US20080113476A1 DUAL-PLANE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR 有权
标题翻译：双平面补充金属氧化物半导体
公开(公告)号：US20080113476A1
公开(公告)日：2008-05-15
申请号：US12014850
申请日：2008-01-16
申请人： Brent Anderson , Edward Nowak
发明人： Brent Anderson , Edward Nowak
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823828 , H01L29/7842 , H01L29/7848 , H01L29/785 , H01L29/78687
摘要： Embodiments herein present a device, method, etc. for a dual-plane complementary metal oxide semiconductor. The device comprises a fin-type transistor on a bulk silicon substrate. The fin-type transistor comprises outer fin regions and a center semiconductor fin region, wherein the center fin region has a {110} crystalline oriented channel surface. The outer fin regions comprise a strain inducing impurity that stresses the center semiconductor fin region. The strain inducing impurity contacts the bulk silicon substrate, wherein the strain inducing impurity comprises germanium and/or carbon. Further, the fin-type transistor comprises a thick oxide member on a top face thereof. The fin-type transistor also comprises a first transistor on a first crystalline oriented surface, wherein the device further comprises a second transistor on a second crystalline oriented surface that differs from the first crystalline oriented surface.
摘要翻译：本文的实施方案提供了用于双平面互补金属氧化物半导体的器件，方法等。该器件包括在体硅衬底上的鳍式晶体管。鳍型晶体管包括外鳍区域和中心半导体鳍片区域，其中中心鳍片区域具有{110}晶体取向沟道表面。外鳍区域包括应力诱导杂质的应变中心半导体鳍片区域的应变。诱发杂质的应变接触体硅衬底，其中应变诱导杂质包括锗和/或碳。此外，鳍型晶体管在其顶面包括厚氧化物构件。翅片型晶体管还包括在第一晶体取向表面上的第一晶体管，其中该器件还包括与第一结晶定向表面不同的第二晶体取向表面上的第二晶体管。

8. 发明申请

US20080042205A1 LOW-COST HIGH-PERFORMANCE PLANAR BACK-GATE CMOS 有权
标题翻译：低成本高性能平面背栅CMOS
公开(公告)号：US20080042205A1
公开(公告)日：2008-02-21
申请号：US11877865
申请日：2007-10-24
申请人： Edward Nowak
发明人： Edward Nowak
IPC分类号： H01L21/8238
CPC分类号： H01L21/823828 , H01L21/743 , H01L21/84 , H01L29/665 , H01L29/66553 , H01L29/66621 , H01L29/6675 , H01L29/78636 , H01L29/78648 , Y10S438/914
摘要： A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-gate CMOS structure that is formed utilizing the method of the present invention. The method includes forming an opening in an upper surface of a substrate. Thereafter, a dopant region is formed in the substrate through the opening. In accordance with the inventive method, the dopant region defines a back-gate conductor of the inventive structure. Next, a front gate conductor having at least a portion thereof is formed within the opening.
摘要翻译：提供了一种使用不太长或昂贵的处理步骤来制造具有优异的短沟道特性和减小电容的高性能平面背栅CMOS结构的方法。还提供了利用本发明的方法形成的高性能平面背栅CMOS结构。该方法包括在基板的上表面形成开口。此后，通过开口在衬底中形成掺杂剂区域。根据本发明的方法，掺杂剂区域限定本发明结构的背栅导体。接下来，在开口内形成具有至少一部分的前门导体。

9. 发明申请

US20070293031A1 SPLIT POLY-SiGe/POLY-Si ALLOY GATE STACK 有权
标题翻译：分散多晶硅/多晶硅合金栅极堆叠
公开(公告)号：US20070293031A1
公开(公告)日：2007-12-20
申请号：US11847384
申请日：2007-08-30
申请人： Kevin Chan , Jia Chen , Shih-Fen Huang , Edward Nowak
发明人： Kevin Chan , Jia Chen , Shih-Fen Huang , Edward Nowak
IPC分类号： H01L21/3205
CPC分类号： H01L21/2807 , H01L21/28052 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L29/4916 , H01L29/4925 , H01L29/665
摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4 A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.
摘要翻译：在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。在快速降低的温度下在氧气环境中原位吹扫沉积室导致薄的SiO 2或Si x O x O O 3至4厚的界面层。薄的SiO 2或Si x Si 2 O 3界面层足够薄且不连续以提供很小的电阻到栅极电流仍具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许后续沉积的钴的硅化物。栅电极堆叠结构用于nFET和pFET两者。

10. 发明申请

US20070290250A1 MULTIPLE DIELECTRIC FINFET STRUCTURE AND METHOD 审中-公开
标题翻译：多电介质FinFET结构与方法
公开(公告)号：US20070290250A1
公开(公告)日：2007-12-20
申请号：US11845972
申请日：2007-08-28
申请人： William Clark , Edward Nowak
发明人： William Clark , Edward Nowak
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/66818
摘要： Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on opposite sides of the channel region. The thicker gate dielectrics can comprise multiple layers of dielectric and the thinner gate dielectrics can comprise less layers of dielectric. A cap comprising a different material than the gate dielectrics can be positioned over the fins.
摘要翻译：公开了一种鳍式场效应晶体管（FinFET）结构的方法和结构，其具有覆盖从衬底延伸的翅片的不同厚度的栅极电介质。这些翅片在通道区域的相对侧具有中心通道区域和源极和漏极区域。较厚的栅极电介质可以包括多层电介质，较薄的栅极电介质可以包含更少的电介质层。包括与栅极电介质不同的材料的盖可以位于鳍片上方。

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