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    • 7. 发明申请
    • DUAL-PLANE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR
    • 双平面补充金属氧化物半导体
    • US20080113476A1
    • 2008-05-15
    • US12014850
    • 2008-01-16
    • Brent AndersonEdward Nowak
    • Brent AndersonEdward Nowak
    • H01L21/8238
    • H01L21/823807H01L21/823828H01L29/7842H01L29/7848H01L29/785H01L29/78687
    • Embodiments herein present a device, method, etc. for a dual-plane complementary metal oxide semiconductor. The device comprises a fin-type transistor on a bulk silicon substrate. The fin-type transistor comprises outer fin regions and a center semiconductor fin region, wherein the center fin region has a {110} crystalline oriented channel surface. The outer fin regions comprise a strain inducing impurity that stresses the center semiconductor fin region. The strain inducing impurity contacts the bulk silicon substrate, wherein the strain inducing impurity comprises germanium and/or carbon. Further, the fin-type transistor comprises a thick oxide member on a top face thereof. The fin-type transistor also comprises a first transistor on a first crystalline oriented surface, wherein the device further comprises a second transistor on a second crystalline oriented surface that differs from the first crystalline oriented surface.
    • 本文的实施方案提供了用于双平面互补金属氧化物半导体的器件,方法等。 该器件包括在体硅衬底上的鳍式晶体管。 鳍型晶体管包括外鳍区域和中心半导体鳍片区域,其中中心鳍片区域具有{110}晶体取向沟道表面。 外鳍区域包括应力诱导杂质的应变中心半导体鳍片区域的应变。 诱发杂质的应变接触体硅衬底,其中应变诱导杂质包括锗和/或碳。 此外,鳍型晶体管在其顶面包括厚氧化物构件。 翅片型晶体管还包括在第一晶体取向表面上的第一晶体管,其中该器件还包括与第一结晶定向表面不同的第二晶体取向表面上的第二晶体管。
    • 9. 发明申请
    • SPLIT POLY-SiGe/POLY-Si ALLOY GATE STACK
    • 分散多晶硅/多晶硅合金栅极堆叠
    • US20070293031A1
    • 2007-12-20
    • US11847384
    • 2007-08-30
    • Kevin ChanJia ChenShih-Fen HuangEdward Nowak
    • Kevin ChanJia ChenShih-Fen HuangEdward Nowak
    • H01L21/3205
    • H01L21/2807H01L21/28052H01L21/28061H01L21/823835H01L21/823842H01L29/4916H01L29/4925H01L29/665
    • A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4 A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.
    • 在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。 硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积(RTCVD)沉积高达至少70%的[Ge]的均匀且连续的多晶硅层。 在快速降低的温度下在氧气环境中原位吹扫沉积室导致薄的SiO 2或Si x O x O O 3至4厚的界面层。 薄的SiO 2或Si x Si 2 O 3界面层足够薄且不连续以提供很小的电阻 到栅极电流仍具有足够的[O]以在热处理期间有效地阻挡Ge扩散,从而允许后续沉积的钴的硅化物。 栅电极堆叠结构用于nFET和pFET两者。