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1. 发明授权

US06323103B1 Method for fabricating transistors 有权
标题翻译：晶体管制造方法
公开(公告)号：US06323103B1
公开(公告)日：2001-11-27
申请号：US09175267
申请日：1998-10-20
申请人： Rajesh Rengarajan , Jochen Beintner , Ulrike Gruening , Hans-Oliver Joachim
发明人： Rajesh Rengarajan , Jochen Beintner , Ulrike Gruening , Hans-Oliver Joachim
IPC分类号： H01L218238
CPC分类号： H01L21/823878 , H01L21/762
摘要： A method is provided for fabricating a first and second MOSFET transistors in different electrically isolated active areas of a semiconductor body, each one of the transistors having a plurality of layers. A first gate oxide layer and a first poly-crystalline silicon layer are deposited over the semiconductor body over the active areas. Trenches are etched in said first gate oxide and poly-crystalline silicon layers and said semiconductor body to delineate the first and second active areas, thereby forming first delineated gate oxide layer and poly-crystalline silicon layers coextensive with the first active area. Material is deposited in said trenches to form the active area isolations, the active area isolations having a top surface above said semiconductor body. A masking layer is then formed over said first and second active areas and selective portions of it are removed to expose said second active area. The masking layer and the active area isolations together form a mask defining an opening coextensive with the second active area with the active area isolations defining said opening. Material through the opening to form a second gate oxide layer and a second poly-crystalline layer, such second layer and second poly-crystalline layer being coextensive with the second active area. The first transistor with the first delineated gate oxide and poly-crystalline layer as a pair of the plurality of layers of the first transistor and the second transistor with the second gate oxide layer and second poly-crystalline layer as a pair of the plurality of layers of the second transistor.
摘要翻译：提供了一种用于在半导体主体的不同电隔离有源区中制造第一和第二MOSFET晶体管的方法，每个晶体管具有多个层。第一栅极氧化物层和第一多晶硅层沉积在半导体主体上方的有源区域上。在所述第一栅极氧化物和多晶硅层和所述半导体本体中蚀刻沟槽以描绘第一和第二有源区，从而形成与第一有源区共同延伸的第一划定的栅极氧化物层和多晶硅层。材料沉积在所述沟槽中以形成有源区隔离，所述有源区隔离在所述半导体本体上方具有顶表面。然后在所述第一和第二有源区上形成掩模层，并且去除其选择性部分以暴露所述第二有源区。屏蔽层和有源区隔离一起形成掩模，其限定与第二有源区域共同延伸的开口，其中限定所述开口的有源区隔离。通过开口的材料形成第二栅氧化层和第二多晶层，这种第二层和第二多晶层与第二有源区共同延伸。第一晶体管，其具有第一划定的栅极氧化物和多晶层作为第一晶体管的多个层和第二晶体管的一对，其中第二栅极氧化物层和第二多晶层作为一对多个层的第二晶体管。

2. 发明授权

US06265742B1 Memory cell structure and fabrication 失效
标题翻译：存储单元结构和制造
公开(公告)号：US06265742B1
公开(公告)日：2001-07-24
申请号：US09317662
申请日：1999-05-24
申请人： Ulrike Gruening , Jochen Beintner , Hans-Oliver Joachim
发明人： Ulrike Gruening , Jochen Beintner , Hans-Oliver Joachim
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A pair of memory cells for use in a DRAM are formed in a monocrystalline bulk portion of a silicon wafer by first forming a pair of vertical trenches spaced apart by a bulk portion of the wafer. After a dielectric layer is formed over the walls of each trench, the trenches are each filled with polycrystalline silicon. By a pair of recess forming and recess filling steps there is formed at the top of each trench a silicon region that was grown epitaxially with the intermediate bulk portion. Each epitaxial region is made to serve as the body of a separate transistor having its drain in the lower polysilicon fill of a trench, and its source in the monocrystalline bulk intermediate between the two epitaxial regions. The lower polysilicon fill of each trench is also made to serve as the storage node of the capacitor of each cell, with the bulk serving as the other plate of the capacitor.
摘要翻译：通过首先形成由晶片的主体部分隔开的一对垂直沟槽，在硅晶片的单晶体部分中形成用于DRAM中的一对存储单元。在每个沟槽的壁之上形成电介质层之后，沟槽各自填充有多晶硅。通过一对凹陷形成和凹陷填充步骤，在每个沟槽的顶部形成有与中间体部分外延生长的硅区域。使每个外延区域用作在沟槽的下多晶硅填充物中具有其漏极的单独晶体管的主体，并且其源于在两个外延区域之间的单晶体体中间。每个沟槽的较低多晶硅填充物也用作每个电池的电容器的存储节点，其体积用作电容器的另一个板。

3. 发明授权

US6093614A Memory cell structure and fabrication 失效
标题翻译：存储单元结构和制造
公开(公告)号：US6093614A
公开(公告)日：2000-07-25
申请号：US34519
申请日：1998-03-04
申请人： Ulrike Gruening , Jochen Beintner , Hans-Oliver Joachim
发明人： Ulrike Gruening , Jochen Beintner , Hans-Oliver Joachim
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A pair of memory cells for use in a DRAM are formed in a monocrystalline bulk portion of a silicon wafer by first forming a pair of vertical trenches spaced apart by a bulk portion of the wafer. After a dielectric layer is formed over the walls of each trench, the trenches are each filled with polycrystalline silicon. By a pair of recess forming and recess filling steps there is formed at the top of each trench a silicon region that was grown epitaxially with the intermediate bulk portion. Each epitaxial region is made to serve as the body of a separate transistor having its drain in the lower polysilicon fill of a trench, and its source in the monocrystalline bulk intermediate between the two epitaxial regions. The lower polysilicon fill of each trench is also made to serve as the storage node of the capacitor of each cell, with the bulk serving as the other plate of the capacitor.
摘要翻译：通过首先形成由晶片的主体部分隔开的一对垂直沟槽，在硅晶片的单晶体部分中形成用于DRAM中的一对存储单元。在每个沟槽的壁之上形成电介质层之后，沟槽各自填充有多晶硅。通过一对凹陷形成和凹陷填充步骤，在每个沟槽的顶部形成有与中间体部分外延生长的硅区域。使每个外延区域用作在沟槽的下多晶硅填充物中具有其漏极的单独晶体管的主体，并且其源于在两个外延区域之间的单晶体体中间。每个沟槽的较低多晶硅填充物也用作每个电池的电容器的存储节点，其体积用作电容器的另一个板。

4. 发明申请

US20050047189A1 Reliable ferro fuse cell 有权
标题翻译：可靠的铁熔丝电池
公开(公告)号：US20050047189A1
公开(公告)日：2005-03-03
申请号：US10651753
申请日：2003-08-29
申请人： Roehr Thomas , Hans-Oliver Joachim , Norbert Rehm
发明人： Roehr Thomas , Hans-Oliver Joachim , Norbert Rehm
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： The present invention includes a ferro fuse cell comprising a ferroelectric storage capacitor electrically connected to a plate on one side and to a sense amplifier on the other side. A ferroelectric measurement capacitor is electrically connected between the ferroelectric storage capacitor and the sense amplifier.
摘要翻译：本发明包括一个铁熔体单元，其包括电连接到一侧的板和另一侧的读出放大器的铁电存储电容器。铁电测量电容器电连接在铁电存储电容器和读出放大器之间。

5. 发明授权

US06584009B1 Memory integrated circuit with improved reliability 有权
标题翻译：内存集成电路具有提高的可靠性
公开(公告)号：US06584009B1
公开(公告)日：2003-06-24
申请号：US10103360
申请日：2002-03-21
申请人： Thomas Roehr , Hans-Oliver Joachim
发明人： Thomas Roehr , Hans-Oliver Joachim
IPC分类号： G11C1112
CPC分类号： G11C11/22 , G11C8/08
摘要： A chained memory IC in which a dual voltage scheme is used for operating the wordlines is described. During standby mode, the wordlines are maintained at a first logic 1 voltage level. To prepare for a memory access, the non-selected wordlines are driven to a boosted voltage while the selected wordline is driven to ground. The first logic 1 voltage level is less than the boosted voltage. This reduces the stress on the gate oxide of the transistors, thus improving reliability of the memory IC.
摘要翻译：描述了其中使用双电压方案来操作字线的链接存储器IC。在待机模式期间，字线保持在第一逻辑1电压电平。为了准备存储器访问，未选择的字线被驱动到升压电压，同时所选择的字线被驱动到地。第一个逻辑1电压电平小于升压电压。这降低了晶体管栅极氧化物的应力，从而提高了存储器IC的可靠性。

6. 发明授权

US06236617B1 High performance CMOS word-line driver 有权
标题翻译：高性能CMOS字线驱动
公开(公告)号：US06236617B1
公开(公告)日：2001-05-22
申请号：US09458878
申请日：1999-12-10
申请人： Louis L. Hsu , Hans-Oliver Joachim , Matthew R. Wordeman , Hing Wong
发明人： Louis L. Hsu , Hans-Oliver Joachim , Matthew R. Wordeman , Hing Wong
IPC分类号： G11C800
CPC分类号： G11C8/08
摘要： A negative wordline DRAM array having n groups of m wordlines, in which one group is driven by a group decoder circuit (having a voltage swing between ground and a circuit high voltage (2 v)) and one driver circuit in each group is exposed to a boosted wordline high voltage (2.8 v) greater than the circuit high voltage, in which the wordline driver circuits have an output stage comprising a standard nfet in series with a high threshold voltage pfet, so that, during activation, the unselected driver circuits exposed to the boosted wordline high voltage have a very low leakage through the pfet, while the selected driver circuit has a high but tolerable leakage (2 &mgr;A) because Vqs on the nfet is nearly at the nfet threshold. The net active power from the entire array is less than that of a conventional configuration due to the reduced voltage swing, while the number of transistors exposed to high voltage stress is reduced from 9 to 1 and the number of buffer nfets required to reduce voltage drop across an active nfet is reduced from 8 to 1.
摘要翻译：具有n组m个字线的负字形DRAM阵列暴露于一组，其中一组由组解码器电路（具有地面之间的电压摆幅和电路高电压（2v））和每组中的一个驱动器电路驱动提升的字线高电压（2.8V）大于电路高电压，其中字线驱动器电路具有包括与高阈值电压pfet串联的标准nfet的输出级，使得在激活期间，未选择的驱动器电路暴露对于升压的字线高电压通过pfet具有非常低的泄漏，而所选择的驱动器电路具有高但可容许的泄漏（2μA），因为nfet上的Vqs几乎处于nfet阈值。由于降低的电压摆幅，整个阵列的净有功功率小于传统配置的功率，而暴露于高电压应力的晶体管的数量从9减少到1，并且减少电压降所需的缓冲器数量跨越一个活跃的nfet从8减少到1。

7. 发明授权

US06885597B2 Sensing test circuit 失效
标题翻译：感应测试电路
公开(公告)号：US06885597B2
公开(公告)日：2005-04-26
申请号：US10065011
申请日：2002-09-10
申请人： Thomas Roehr , Hans-Oliver Joachim , Michael Jacob , Joerg Wohlfahrt , Takashima Daisaburo
发明人： Thomas Roehr , Hans-Oliver Joachim , Michael Jacob , Joerg Wohlfahrt , Takashima Daisaburo
IPC分类号： G11C29/50 , G11C29/00
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/1204 , G11C2029/5004
摘要： A test circuit for testing differential read signals during a memory access is disclosed. The test circuit is coupled to a pair of bit lines. During a read access, a selected memory cell produces a differential read signal on the bit lines. When the test circuit is activated, the magnitude of the differential read signal is varied. This enables easy testing of read signal margins in, for example, memory ICs.
摘要翻译：公开了一种用于在存储器访问期间测试差分读取信号的测试电路。测试电路耦合到一对位线。在读访问期间，所选存储单元在位线上产生差分读信号。当测试电路被激活时，差分读取信号的幅度是变化的。这使得能够容易地测试例如存储器IC中的读取信号余量。

8. 发明申请

US20050063213A1 Signal margin test mode for FeRAM with ferroelectric reference capacitor 审中-公开
标题翻译：具有铁电参考电容的FeRAM的信号余量测试模式
公开(公告)号：US20050063213A1
公开(公告)日：2005-03-24
申请号：US10665402
申请日：2003-09-18
申请人： Michael Jacob , Thomas Roehr , Hans-Oliver Joachim
发明人： Michael Jacob , Thomas Roehr , Hans-Oliver Joachim
IPC分类号： G11C29/50 , G11C11/22
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5002 , G11C2029/5004
摘要： The present invention provides a semiconductor memory test mode configuration. A first capacitor stores digital data and connects a cell plate line to a first bit-line through a first select transistor. The first select transistor is activated through a connection to a word line. At least one reference capacitor provides a reference voltage to a reference bit-line. A sense amplifier is connected to the first and reference bit-lines and measures a differential read signal on the first and reference bit-lines. A charge path reduces the differential read signal to determine the signal margin of the semiconductor memory.
摘要翻译：本发明提供半导体存储器测试模式配置。第一电容器存储数字数据，并且通过第一选择晶体管将单元板线连接到第一位线。第一个选择晶体管通过与字线的连接来激活。至少一个参考电容器为参考位线提供参考电压。读出放大器连接到第一和参考位线，并测量第一和参考位线上的差分读取信号。充电路径减小差分读取信号以确定半导体存储器的信号余量。

9. 发明授权

US06707699B1 Historical information storage for integrated circuits 有权
标题翻译：集成电路的历史信息存储
公开(公告)号：US06707699B1
公开(公告)日：2004-03-16
申请号：US10065167
申请日：2002-09-24
申请人： Michael Klaus Jacob , Joerg Wilfried Wohlfahrt , Norbert Rehm , Hans-Oliver Joachim
发明人： Michael Klaus Jacob , Joerg Wilfried Wohlfahrt , Norbert Rehm , Hans-Oliver Joachim
IPC分类号： G11C1122
CPC分类号： G11C29/44 , G11C11/22 , G11C2029/1208 , G11C2029/4402 , G11C2029/5002
摘要： The present invention describes an information recorder which is integrated into an IC, such as ferroelectric RAM device. The recorder counts desired events, such as memory accesses or length of time powered up and stores such information in a latch. The information can be retrieved from the latch to assist in failure analysis and device characterization.
摘要翻译：本发明描述了集成到IC中的信息记录器，例如铁电RAM装置。记录器计算所需的事件，例如存储器访问或时间长度加电，并将这些信息存储在锁存器中。可以从锁存器检索信息，以帮助进行故障分析和设备表征。

10. 发明授权

US5926703A LDD device having a high concentration region under the channel 失效
标题翻译： LDD器件在通道下方具有高浓度区域
公开(公告)号：US5926703A
公开(公告)日：1999-07-20
申请号：US785277
申请日：1997-01-21
申请人： Yasuo Yamaguchi , Hans-Oliver Joachim , Yasuo Inoue
发明人： Yasuo Yamaguchi , Hans-Oliver Joachim , Yasuo Inoue
IPC分类号： H01L29/40 , H01L21/336 , H01L27/12 , H01L29/417 , H01L29/78 , H01L29/786 , H01L21/44
CPC分类号： H01L29/66757 , H01L27/1203 , H01L29/78606 , H01L29/78609 , H01L29/78621
摘要： It is an object to obtain a semiconductor device with the LDD structure having both operational stability and high speed and a manufacturing method thereof. A high concentration region (11) with boron of about 1.times.10.sup.18 /cm.sup.3 introduced therein is formed extending from under a channel formation region (4) to under a drain region (6) and a source region (6') in a silicon substrate (1). The high concentration region (11) is formed in the surface of the silicon substrate (1) under the channel formation region (4), and is formed at a predetermined depth from the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). A low concentration region (10) is formed in the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). The formation of the high concentration region only in the surface of the semiconductor substrate under the channel formation region surely suppresses an increase in the leakage current and an increase in the drain capacitance.
摘要翻译：本发明的目的是获得具有操作稳定性和高速度的LDD结构的半导体器件及其制造方法。导入其中引入了约1×10 18 / cm 3的硼的高浓度区域（11）形成在沟道形成区域（4）下方延伸到漏极区域（6）下方的硅衬底（1）中的源极区域（6'））。在硅衬底（1）的沟道形成区域（4）的表面上形成高浓度区域（11），并且形成在与硅衬底（1）的漏极区域 6）和源极区（6'）。在漏极区域（6）和源极区域（6'）的下方的硅衬底（1）的表面中形成低浓度区域（10）。仅在沟道形成区域的半导体衬底的表面形成高浓度区域确实地抑制了漏电流的增加和漏极电容的增加。

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