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61. 发明授权

US07284029B2 4-to-2 carry save adder using limited switching dynamic logic 失效
标题翻译：使用有限切换动态逻辑的4对2进位保存加法器
公开(公告)号：US07284029B2
公开(公告)日：2007-10-16
申请号：US10702989
申请日：2003-11-06
申请人： Wendy A. Belluomini , Ramyanshu Datta , Chandler T. McDowell , Robert K. Montoye , Hung C. Ngo
发明人： Wendy A. Belluomini , Ramyanshu Datta , Chandler T. McDowell , Robert K. Montoye , Hung C. Ngo
IPC分类号： G06F7/50
CPC分类号： G06F7/607
摘要： A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry save adder may further include a second LSDL circuit configured to output a carry bit. Both the first and second LSDL circuits use a carry generated in the current stage that was previously generated in the previous stage (next lower order bit position). Since the carry is generated in the current stage and not in the previous stage, the delay in outputting the sum and carry bits is reduced and hence the performance of carry save adders is improved. Further, since LSDL circuits were used in the carry save adder, power consumption was reduced while using a small amount of area.
摘要翻译：一个4对2进位保存加法器使用限制切换动态逻辑（LSDL）来减少功耗，同时减少输出和和传送位的延迟。 4对2进位存储加法器可以包括被配置为输出和位的第一LSDL电路。进位保存加法器还可以包括被配置为输出进位位的第二LSDL电路。第一LSDL电路和第二LSDL电路均使用先前在先前产生的当前阶段中生成的进位（下一个低位位置）。由于进位在当前阶段而不是在前一阶段中产生，所以减少输出和和进位的延迟，从而提高进位保存加法器的性能。此外，由于在进位保存加法器中使用LSDL电路，所以在使用少量的区域时功耗降低。

62. 发明授权

US06963629B2 Adaptive phase locked loop 有权
标题翻译：自适应锁相环
公开(公告)号：US06963629B2
公开(公告)日：2005-11-08
申请号：US09918809
申请日：2001-07-31
申请人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo
发明人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo
IPC分类号： H03D13/00 , H03L7/089 , H03L7/107 , H03D3/24 , H03L7/06
CPC分类号： H03L7/107 , H03D13/004 , H03L7/0898
摘要： A reference signal and a voltage controlled oscillator (VCO) output are compared for relative phase and frequency differences. A lead error signal is generated if the reference signal leads the VCO output and a lag error signal is generated if the reference signal lags the VCO output the lead and lag error may result from a combination for phase and frequency differences between the reference signal and the VCO output. A time window is used to sample the polarity of the lead and lag error signals by incrementing and decrementing a phase error signal. If the phase error signal reaches a threshold value within the time window, a Reset Delta pulse is generated and if the phase error signals does not reach the maximum delta value within the time window a Reset Total pulse is generated. A variable first gain signal is increased on each Reset Delta pulse and decreased on each Reset Total pulse and limited to a value between predetermined maximum and minimum values. The first gain signal is multiplied by a Pump current increment and added to a minimum Pump current to generate a variable Pump current. A variable second gain signal proportional to the time the reference signal leads and lags the VCO signal multiplies the Pump current. The amplified Pump current is summed with an integral of the amplified Pump current to generate a control signal. The control signal is applied to the VCO and determines the frequency of the VCO output.
摘要翻译：比较参考信号和压控振荡器（VCO）输出的相对相位和频率差。如果参考信号引导VCO输出，则产生引导误差信号，如果参考信号滞后于VCO输出引起滞后误差信号产生滞后误差，则滞后误差可能由参考信号和 VCO输出。时间窗口用于通过递增和递减相位误差信号来对引线和滞后误差信号的极性进行采样。如果相位误差信号在时间窗内达到阈值，则产生复位增量脉冲，如果相位误差信号在时间窗口内未达到最大增量值，则产生复位总脉冲。在每个复位增量脉冲上增加可变的第一增益信号，并在每个复位总脉冲上减小，并限制在预定的最大和最小值之间的值。第一个增益信号乘以泵电流增量，并加到最小泵电流以产生可变泵电流。与参考信号引导和滞后于VCO信号的时间成比例的可变第二增益信号与泵电流相乘。放大的泵电流与放大的泵电流的积分相加以产生控制信号。控制信号被施加到VCO并确定VCO输出的频率。

63. 发明授权

US5881274A Method and apparatus for performing add and rotate as a single instruction within a processor 失效
标题翻译：用于在处理器内作为单个指令执行加法和旋转的方法和装置
公开(公告)号：US5881274A
公开(公告)日：1999-03-09
申请号：US900261
申请日：1997-07-25
申请人： Hung C. Ngo , Joel A. Silberman , Sang H. Dhong
发明人： Hung C. Ngo , Joel A. Silberman , Sang H. Dhong
IPC分类号： G06F9/302 , G06F9/315 , G06F9/305
CPC分类号： G06F9/3001 , G06F9/30032
摘要： An apparatus for performing ADD and ROTATE as a single instruction within a processor is disclosed. In accordance with a preferred embodiment of the present invention, the apparatus comprises an adder and a rotator. The adder is utilized for adding a first number to a second number in a multiple stages to yield a carry-out and a sum output. During each of these stages, the adder produces a group generate value and a group propagate value. The rotator is utilized for rotating the group propagate value and the group generate value at each of the stages before the yielding of the carry-out and the sum output. As such, both ADD and ROTATE instructions can be completed within a single processor cycle.
摘要翻译：公开了一种用于在处理器内执行ADD和ROTATE作为单个指令的装置。根据本发明的优选实施例，该装置包括加法器和旋转器。加法器用于将多个第一数字加到多个第二数目中以产生一个进位输出和一个和输出。在每个阶段中，加法器产生组生成值和组传播值。旋转器用于旋转组传播值，并且在进位输出和总和输出的屈服之前的组中的每个级产生组生成值。因此，ADD和ROTATE指令都可以在单个处理器周期内完成。

64. 发明授权

US5627774A Parallel calculation of exponent and sticky bit during normalization 失效
标题翻译：在归一化期间并行计算指数和粘点
公开(公告)号：US5627774A
公开(公告)日：1997-05-06
申请号：US473308
申请日：1995-06-07
申请人： Eric M. Schwarz , Robert M. Bunce , Leon J. Sigal , Hung C. Ngo
发明人： Eric M. Schwarz , Robert M. Bunce , Leon J. Sigal , Hung C. Ngo
IPC分类号： G06F5/01 , G06F7/57 , G06F7/00 , G06F7/38
CPC分类号： G06F5/012 , G06F7/483 , G06F7/49952 , G06F7/49957
摘要： A system implementing a methodology for determining the exponent in parallel with determining the fractional shift during normalization according to partitioning the exponent into partial exponent groups according to the fractional shift data flow, determining all possible partial exponent values for each partial exponent group according to the fractional data flow, and providing the exponent by selectively combining possible partial exponents from each partial exponent group according to the fractional data flow. There is also provided a system implementing a methodology for generating the sticky bit during normalization. Sticky bit information is precalculated and multiplexed according to the fractional dataflow. In an embodiment of the invention, group sticky signals are calculated in tree form, each group sticky having a number of possible sticky bits corresponding to the shift increment amount of the multiplexing. The group sticky bits are further multiplexed according to subsequent shift amounts in the fractional dataflow to provide an output sticky bit at substantially the same time as when the final fractional shift amount is available, and thereby at substantially the same time as the normalized fraction.
摘要翻译：根据分数位移数据流，根据将指数分解成部分指数组，实现用于在归一化期间确定分数移位的方法来确定指数的方法，根据分数确定每个部分指数组的所有可能的部分指数值数据流，并且通过根据分数据流选择性地组合来自每个部分指数组的可能部分指数来提供指数。还提供了一种实现在归一化过程中产生粘性位的方法的系统。粘滞位信息根据分数据流进行预先计算和复用。在本发明的一个实施例中，以树形式计算组粘性信号，每组粘性具有与多路复用的移位增量量相对应的多个可能的粘性位。组粘性位根据分数据流中的随后的移位量进一步复用，以在与最终分数移位量可用时基本相同的时间提供输出粘性位，并且因此与归一化分数基本上相同。

65. 发明授权

US08217427B2 High density stable static random access memory 有权
标题翻译：高密度稳定的静态随机存取存储器
公开(公告)号：US08217427B2
公开(公告)日：2012-07-10
申请号：US11865780
申请日：2007-10-02
申请人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jente Benedict Kuang , Hung C. Ngo
发明人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jente Benedict Kuang , Hung C. Ngo
IPC分类号： H01L27/11
CPC分类号： H01L27/11 , H01L27/0207 , H01L27/1108 , H01L27/1203 , H01L29/78648 , Y10S257/905
摘要： A memory circuit includes a plurality of bit line structures, a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells is selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures, and each of the cells in turn includes a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor. The at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of the bit line structures, and the at least first p-type field effect transistor is formed with a relatively thin buried oxide layer.
摘要翻译：存储电路包括多个位线结构，多个字线结构与多个位线结构相交以形成多个单元位置; 以及位于多个单元位置的多个单元。每个单元在对应的一个字线结构的控制下选择性地耦合到位线结构中的相应一个，并且每个单元又包括具有至少第一n型场效应的逻辑存储元件晶体管和至少第一p型场效应晶体管。所述至少第一n型场效应晶体管形成有尺寸适于减小所述位线结构的电容的相对较厚的掩埋氧化物层，并且所述至少第一p型场效应晶体管形成有较薄的掩埋氧化物层。

66. 发明申请

US20090177870A1 Method and System for a Wiring-Efficient Permute Unit 失效
标题翻译：一种有效的宽带单元的方法和系统
公开(公告)号：US20090177870A1
公开(公告)日：2009-07-09
申请号：US11968692
申请日：2008-01-03
申请人： Bruce M. Fleischer , Hung C. Ngo , Jun Sawada
发明人： Bruce M. Fleischer , Hung C. Ngo , Jun Sawada
IPC分类号： G06F9/305 , G06F13/00
CPC分类号： G06F9/30032 , G06F7/762 , G06F7/766 , G06F9/30036 , G06F9/3824 , G06F9/3826
摘要： A method of providing wiring efficiency in a permute unit. Multiple selectors receive input data and shared control signals from multiple register files. The permute unit includes multiple multiplexors (MUXs) coupled to multiple logical AND gates. The multiple logical AND gates are coupled to multiple logical OR gates. The logical AND gates are physically separated from the logical OR gates. The logical AND gates receive input from one or more output data signals from the selectors. The logical OR gates combine the one or more output signals from the logical AND gates and provide output data from the permute unit.
摘要翻译：一种在置换单元中提供布线效率的方法。多个选择器从多个寄存器文件接收输入数据和共享控制信号。置换单元包括耦合到多个逻辑与门的多个多路复用器（MUX）。多个逻辑与门被耦合到多个逻辑或门。逻辑“与”门与逻辑或门物理分离。逻辑与门接收来自选择器的一个或多个输出数据信号的输入。逻辑或门组合来自逻辑与门的一个或多个输出信号，并提供来自置换单元的输出数据。

67. 发明申请

US20080265957A1 Self-Resetting Phase Frequency Detector with Multiple Ranges of Clock Difference 审中-公开
标题翻译：具有多个时钟差范围的自复位相位检波器
公开(公告)号：US20080265957A1
公开(公告)日：2008-10-30
申请号：US11739760
申请日：2007-04-25
申请人： Trong V. Luong , Hung C. Ngo , Jethro C. Law , Peter J. Klim
发明人： Trong V. Luong , Hung C. Ngo , Jethro C. Law , Peter J. Klim
IPC分类号： H03L7/06
CPC分类号： H03L7/089
摘要： A phase detector which provides a dynamic output signal and which automatically resets if a reference clock signal and a feedback clock signal align after an output pulse is generated. With the phase detector in accordance with the present invention, when there is a difference between the positive clock edges of the reference clock signal and the feedback clock signal, the phase detector generates output pulse. The output is used to correct the feedback clock signal. In the next cycle, if the feedback signal is corrected so that both the reference clock signal and feedback clock signal are aligned, then the output signals are reset to zero. The ability to reset advantageously prevents an unexpected correction that can occur in certain phase detector designs.
摘要翻译：相位检测器，其提供动态输出信号，并且如果在产生输出脉冲之后参考时钟信号和反馈时钟信号对准，则自动复位。利用根据本发明的相位检测器，当参考时钟信号的正时钟沿与反馈时钟信号之间存在差异时，相位检测器产生输出脉冲。输出用于校正反馈时钟信号。在下一个周期中，如果反馈信号被校正，使得参考时钟信号和反馈时钟信号都对准，则输出信号被复位为零。复位的能力有利地防止了在某些相位检测器设计中可能出现的意外的校正。

68. 发明授权

US06956793B2 Phase clock selector for generating a non-integer frequency division 失效
标题翻译：用于产生非整数分频的相位时钟选择器
公开(公告)号：US06956793B2
公开(公告)日：2005-10-18
申请号：US10718063
申请日：2003-11-20
申请人： Hung C. Ngo
发明人： Hung C. Ngo
IPC分类号： G04G3/02 , H03K23/66 , H03K23/68 , H03L7/099 , H03L7/197 , G04F5/00 , G04B18/00 , G06F1/02 , H03K21/00 , H03K23/00
CPC分类号： H03L7/1974 , G04G3/02 , H03K23/667 , H03K23/68 , H03L7/0996
摘要： A frequency divider circuit uses a base counter to frequency divide a clock signal with period T by an integer value N and employs a cyclic rotational select circuit to select among multiple equally phase shifted signals of a multiple phase clock to generate a fractional term P/k where P is variable from 0 to k−1. The counter counts an output clock that corresponds to the output of a multiplexer selecting from among the multiple clock phases. Depending on the desired fractional term, after N counts of the output clock phases of the multiple phase clock are selected glitch free by rotationally selecting a first phase, and skipping either 0, 1, 2 . . . up to k−1 sequential phases to generate fractional terms 0, 1/k, 2/k, 3/k . . . k−1/k, respectively, thus providing frequency division corresponding to N+P/k where P may be varied from 0 to k−1.
摘要翻译：分频器电路使用基本计数器对具有周期T的时钟信号进行频率分频整数N，并且采用循环旋转选择电路在多相等时相位信号中选择生成小数项P / k 其中P从0到k-1是可变的。计数器对与多个时钟相位中选择的多路复用器的输出相对应的输出时钟进行计数。根据期望的分数项，通过旋转选择第一相位，并跳过0,1,2，多次相位时钟的输出时钟相位的N个计数被无毛刺选择。。。直到k-1个顺序相位来产生分数项0,1 / k，2 / k，3 / k。。。 k-1 / k，从而提供对应于N + P / k的频分，其中P可以从0到k-1变化。

69. 发明授权

US06919739B2 Feedforward limited switch dynamic logic circuit 失效
标题翻译：前馈限位开关动态逻辑电路
公开(公告)号：US06919739B2
公开(公告)日：2005-07-19
申请号：US10733950
申请日：2003-12-11
申请人： Hung C. Ngo
发明人： Hung C. Ngo
IPC分类号： H03K3/012 , H03K3/356 , H03K19/096 , H03K19/00
CPC分类号： H03K3/356121 , H03K3/012 , H03K19/0963
摘要： The N channel field effect transistor (NFET) of the inverting output stage of a LSDL gate is split into a large NFET and a small NFET. The large NFET is coupled to a feedforward pulse so that it is turned ON only when the inverting output is a logic one. When the inverting output is a logic one, another inverting stage turns ON if the dynamic node evaluates to a logic zero. The dynamic node is inverted and coupled to the large NFET on the inverting output stage thus quickly pulling the inverting output to a logic zero. The small NFET is turned ON as a keeper device through the normal logic path. If the inverting data output is a logic zero the feedforward pulse is not generated. By making the largest NFET a pulsed device the other FETs are reduced in size resulting in leakage and switching power savings.
摘要翻译： LSDL栅极的反相输出级的N沟道场效应晶体管（NFET）分为大NFET和小NFET。大的NFET耦合到前馈脉冲，使得仅当反相输出为逻辑1时才将其导通。当反相输出为逻辑1时，如果动态节点评估为逻辑0，则另一个反相级将变为ON。动态节点被反相并耦合到反相输出级上的大NFET，从而快速地将反相输出拉至逻辑0。小型NFET通过正常逻辑路径作为保持器装置接通。如果反相数据输出为逻辑0，则不产生前馈脉冲。通过使最大的NFET是脉冲器件，其他FET的尺寸减小，从而导致泄漏和开关功率节省。

70. 发明授权

US06873188B2 Limited switch dynamic logic selector circuits 失效
标题翻译：有限开关动态逻辑选择电路
公开(公告)号：US06873188B2
公开(公告)日：2005-03-29
申请号：US10242236
申请日：2002-09-12
申请人： Wendy A. Belluomini , Robert K. Montoye , Hung C. Ngo
发明人： Wendy A. Belluomini , Robert K. Montoye , Hung C. Ngo
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： Selector circuits and systems for single and multilevel selection within one clock cycle having a static switching factor on the output of a dynamic logic circuit. A logic device for single and multilevel selection having a dynamic logic circuit portion and a static logic circuit portion is implemented. In this way, an output logic state is maintained so long as the value of the Boolean operation being performed by the logic device does not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock permits a concomitant decrease in the size of the precharge transistors thus ameliorating the area required by the logic element and obviating a need for keeper device.
摘要翻译：选择器电路和系统在一个时钟周期内进行单和多电平选择，在动态逻辑电路的输出上具有静态开关因子。实现了具有动态逻辑电路部分和静态逻辑电路部分的单级和多级选择的逻辑器件。这样，只要逻辑器件执行的布尔运算的值不变，就保持输出逻辑状态。此外，静态逻辑元件可以执行输出逻辑感应所需的反转，减轻提供双轨动态逻辑实现的需要。非对称时钟允许预充电晶体管的尺寸伴随减小，因此改善了逻辑元件所需的面积并且消除了对保持器装置的需要。

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