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61. 发明授权

US06656830B1 Dual damascene with silicon carbide middle etch stop layer/ARC 有权
标题翻译：双面镶嵌碳化硅中间蚀刻停止层/ ARC
公开(公告)号：US06656830B1
公开(公告)日：2003-12-02
申请号：US09777695
申请日：2001-02-07
申请人： Ramkumar Subramanian , Dawn M. Hopper , Fei Wang , Lynne A. Okada
发明人： Ramkumar Subramanian , Dawn M. Hopper , Fei Wang , Lynne A. Okada
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/76807
摘要： The dimensional accuracy of trench formation and, hence, metal line width, in damascene processing is improved by employing a silicon carbide middle etch stop layer/ARC. Embodiments include via first-trench last dual damascene techniques employing a silicon carbide middle etch stop layer/ARC having an extinction coefficient (k) of about −0.10 to about −0.60.
摘要翻译：通过采用碳化硅中间蚀刻停止层/ ARC，提高了镶嵌加工中沟槽形成的尺寸精度以及因此的金属线宽度。实施例包括使用具有约-0.10至约-0.60的消光系数（k）的碳化硅中蚀刻停止层/ ARC的第一沟槽最后双镶嵌技术。

62. 发明授权

US06632707B1 Method for forming an interconnect structure using a CVD organic BARC to mitigate via poisoning 有权
标题翻译：使用CVD有机BARC形成互连结构以减轻中毒的方法
公开(公告)号：US06632707B1
公开(公告)日：2003-10-14
申请号：US10058227
申请日：2002-01-29
申请人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , James K. Kai , Calvin T. Gabriel , Lu You
发明人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , James K. Kai , Calvin T. Gabriel , Lu You
IPC分类号： H01L2144
CPC分类号： H01L21/76808
摘要： A method for forming a metal interconnect structure in a semiconductor device with the elimination of via poisoning during trench mask formation employs a CVD organic BARC that isolates the low k dielectric film. The CVD organic BARC is deposited over the low k dielectric film and in the via hole. Once the trench mask has been formed on the CVD organic BARC, the CVD organic BARC may be removed in the same process as the photoresist of the trench mask layer. A properly formed trench will have been created since the via poisoning and resist scumming were substantially eliminated by the presence of the CVD organic BARC.
摘要翻译：在沟槽掩模形成期间消除通孔中毒的在半导体器件中形成金属互连结构的方法使用隔离低k绝缘膜的CVD有机BARC。 CVD有机BARC沉积在低k电介质膜和通孔中。一旦在CVD有机BARC上形成了沟槽掩模，就可以以与沟槽掩模层的光致抗蚀剂相同的工艺去除CVD有机BARC。由于CVD有机BARC的存在基本上消除了通孔中毒和抵抗浮渣，所以将形成一个正确形成的沟槽。

63. 发明授权

US06603206B2 Slot via filled dual damascene interconnect structure without middle etch stop layer 有权
标题翻译：通过填充的双镶嵌互连结构的槽，没有中间蚀刻停止层
公开(公告)号：US06603206B2
公开(公告)日：2003-08-05
申请号：US10105509
申请日：2002-03-26
申请人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
发明人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
IPC分类号： H01L23522
CPC分类号： H01L21/76835 , H01L21/76808 , H01L2221/1031 , Y10S977/827
摘要： An interconnect structure and method of forming the same in which a bottom anti-reflective coating/etch stop layer is deposited over a conductive layer. An inorganic low k dielectric material is deposited over the BARC/etch stop layer to form a first dielectric layer. The first dielectric layer is etched to form a slot via in the first dielectric layer. An organic low k dielectric material is deposited within the slot via and over the first dielectric layer to form a second dielectric layer over the slot via and the first dielectric layer. The re-filled via is simultaneously etched with the second dielectric layer in which a trench is formed. The trench extends in a direction that is normal to the length of the slot via. The entire width of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.
摘要翻译：一种互连结构及其形成方法，其中底部抗反射涂层/蚀刻停止层沉积在导电层上。无机低k介电材料沉积在BARC /蚀刻停止层上以形成第一介电层。蚀刻第一介电层以在第一介电层中形成槽通孔。有机低k电介质材料通过第一电介质层和第一介电层上方沉积在槽内，以在槽通孔和第一介电层上形成第二电介质层。再次填充的通孔与其中形成沟槽的第二电介质层同时蚀刻。沟槽沿与槽通孔的长度垂直的方向延伸。沟槽的整个宽度直接在通孔上方。重新打开的通孔和沟槽填充有导电材料。

64. 发明授权

US06528409B1 Interconnect structure formed in porous dielectric material with minimized degradation and electromigration 有权
标题翻译：在多孔介电材料中形成的互连结构具有最小化的降解和电迁移
公开(公告)号：US06528409B1
公开(公告)日：2003-03-04
申请号：US10134883
申请日：2002-04-29
申请人： Sergey Lopatin , Fei Wang , Diana Schonauer , Steven C. Avanzino
发明人： Sergey Lopatin , Fei Wang , Diana Schonauer , Steven C. Avanzino
IPC分类号： H01L214763
CPC分类号： H01L21/76828 , H01L21/288 , H01L21/76805 , H01L21/76814 , H01L21/7682 , H01L21/76829 , H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76849 , H01L21/76862 , H01L21/76865 , H01L21/76867 , H01L21/76874 , H01L2221/1047 , H01L2221/1089
摘要： For fabricating an interconnect structure within an interconnect opening formed within a porous dielectric material, the interconnect opening is initially formed within a low-K precursor material that is not completely cured. The interconnect opening is then filled with a conductive fill material being contained within the interconnect opening and with a top surface of the conductive fill material within the interconnect opening being exposed. A capping material is formed on the top surface of the conductive fill material, and the capping material is an amorphous alloy or is a microcrystalline alloy having stuffed grain boundaries. A thermal curing process is then performed for curing the low-K precursor material to become a porous low-K dielectric material. The capping material on the top surface of the conductive fill material is impervious to at least one of oxygen, carbon, hydrogen, chlorine, and porogen fragments that are generated as out-gassing volatile by-products from the low-K precursor material during the thermal curing process to preserve the integrity of the interconnect structure. In another aspect for fabricating an interconnect structure, an interconnect opening is formed within a porous dielectric material with opened pores at sidewalls of the interconnect opening. A diffusion barrier material is formed at a bottom wall of the interconnect opening. The diffusion barrier material is then sputtered away from the bottom wall of the interconnect opening and onto the sidewalls of the interconnect opening to substantially fill the opened pores at the sidewalls with the diffusion barrier material. The interconnect opening is then filled with a conductive fill material after the opened pores at the sidewalls of the interconnect opening are filled with the diffusion barrier material.
摘要翻译：为了在形成在多孔电介质材料内的互连开口内制造互连结构，互连开口最初形成在未完全固化的低K前体材料内。然后用互连开口内容纳的导电填充材料填充互连开口，并且暴露互连开口内的导电填充材料的顶表面。在导电填充材料的顶表面上形成封盖材料，封盖材料是非晶合金，或是具有填充晶界的微晶合金。然后进行热固化过程，以固化低K前体材料，成为多孔低K电介质材料。在导电填充材料的顶表面上的封盖材料对于氧，碳，氢，氯和致孔剂碎片中的至少一种是不渗透的，所述氧，碳，氢，氯和致孔剂碎片作为在低K前体材料期间产生的挥发性挥发性副产物而产生热固化工艺来保持互连结构的完整性。在用于制造互连结构的另一方面中，互连开口形成在具有在互连开口的侧壁处的开孔的多孔电介质材料内。扩散阻挡材料形成在互连开口的底壁处。然后将扩散阻挡材料从互连开口的底壁溅射到互连开口的侧壁上，以基本上用扩散阻挡材料填充侧壁处的开孔。然后在互连开口的侧壁处的开放孔填充有扩散阻挡材料之后，用导电填充材料填充互连开口。

65. 发明授权

US06524947B1 Slotted trench dual inlaid structure and method of forming thereof 有权
标题翻译：开槽沟双重镶嵌结构及其形成方法
公开(公告)号：US06524947B1
公开(公告)日：2003-02-25
申请号：US09774800
申请日：2001-02-01
申请人： Ramkumar Subramanian , Todd P. Lukanc , Fei Wang
发明人： Ramkumar Subramanian , Todd P. Lukanc , Fei Wang
IPC分类号： H01L214763
CPC分类号： H01L21/76811 , Y10S977/888
摘要： A method of manufacturing a semiconductor structure, including etching an opening in a hard mask layer including a trench pattern width a first portion having a first width and a second portion being an oversized trench portion having a second width greater than a width of the first portion, the second portion being formed over a predetermined via location. Also including are steps of depositing a resist and patterning a via pattern in the predetermined via location, etching a via corresponding to the via pattern through the resist and at least partially through a dielectric layer, and etching an oversized trench portion corresponding to a second portion opening in the hard mask.
摘要翻译：一种制造半导体结构的方法，包括蚀刻包括沟槽图案宽度的硬掩模层中的开口，具有第一宽度的第一部分和第二部分是具有大于第一部分的宽度的第二宽度的超大沟槽部分，第二部分形成在预定的通孔位置上。还包括沉积抗蚀剂并将通孔图案图案化在预定通孔位置的步骤，通过抗蚀剂蚀刻对应于通孔图案的通孔并且至少部分地通过电介质层，以及蚀刻对应于第二部分的超大沟槽部分打开硬面膜。

66. 发明授权

US06521524B1 Via filled dual damascene structure with middle stop layer and method for making the same 有权
标题翻译：通过填充中间停止层的双镶嵌结构和制作相同的方法
公开(公告)号：US06521524B1
公开(公告)日：2003-02-18
申请号：US09778070
申请日：2001-02-07
申请人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
发明人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76808 , H01L2221/1031
摘要： An interconnect structure and method of forming the same in which an inorganic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to form a via in the first dielectric layer. An organic low k dielectric material is deposited within the via and over the etch stop layer to form a second dielectric layer over the via and the etch stop layer. The re-filled via is simultaneously etched with the second dielectric layer in which a trench is formed. A portion of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.
摘要翻译：一种互连结构及其形成方法，其中无机低k电介质材料沉积在导电层上以形成第一介电层。在第一电介质层上形成蚀刻停止层。蚀刻停止层和第一介电层被蚀刻以在第一介电层中形成通孔。有机低k介电材料沉积在通孔内和蚀刻停止层上方，以在通孔和蚀刻停止层上方形成第二电介质层。再次填充的通孔与其中形成沟槽的第二电介质层同时蚀刻。沟槽的一部分直接在通孔的上方。重新打开的通孔和沟槽填充有导电材料。

67. 发明授权

US06475915B1 Ono etch using CL2/HE chemistry 失效
标题翻译：使用CL2 / HE化学法进行小野蚀刻
公开(公告)号：US06475915B1
公开(公告)日：2002-11-05
申请号：US09420687
申请日：1999-10-19
申请人： Fei Wang
发明人： Fei Wang
IPC分类号： H01L21302
CPC分类号： H01L21/31116 , H01L21/76213 , H01L21/823481
摘要： An etch process utilizing Cl2/He chemistry for use in a silicon integrated circuit manufacturing process. The etch is a highly nitride selective, anisotropic etch. The process according to an aspect of the invention comprises the steps of etching through a top silicon dioxide layer of an ONO layer with a C12/He plasma etch at a first power, and subsequently etching the underlying nitride layer at a substantially lower second power.
摘要翻译：利用Cl2 / He化学在硅集成电路制造工艺中使用的蚀刻工艺。蚀刻是高度氮化物选择性的各向异性蚀刻。根据本发明的一个方面的方法包括以第一功率用C12 / He等离子体蚀刻蚀刻通过ONO层的顶部二氧化硅层的步骤，然后以基本上较低的第二功率蚀刻下面的氮化物层。

68. 发明授权

US06440640B1 Thin resist with transition metal hard mask for via etch application 有权
标题翻译：具有过渡金属硬掩模的薄抗蚀剂，用于通孔蚀刻应用
公开(公告)号：US06440640B1
公开(公告)日：2002-08-27
申请号：US09703092
申请日：2000-10-31
申请人： Chih Yuh Yang , Christopher F. Lyons , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Scott A. Bell
发明人： Chih Yuh Yang , Christopher F. Lyons , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Scott A. Bell
IPC分类号： G03C500
CPC分类号： H01L21/76816 , H01L21/0276 , H01L21/0332 , H01L21/0338 , H01L21/32139
摘要： A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a transition metal layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the transition metal layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the transition metal layer. The first etch step includes an etch chemistry that is selective to the transition metal layer over the ultra-thin photoresist layer and the dielectric layer. The transition metal layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.
摘要翻译：提供一种形成通孔结构的方法。在该方法中，在覆盖第一金属层的抗反射涂层（ARC）层上形成电介质层; 并且在介电层上形成过渡金属层。在过渡金属层上形成超薄光致抗蚀剂层，并用短波长辐射对超薄光致抗蚀剂层进行构图，以形成通孔图案。在第一蚀刻步骤期间，将图案化超薄光致抗蚀剂层用作掩模，以将通孔图案转印到过渡金属层。第一蚀刻步骤包括对超薄光致抗蚀剂层和电介质层上的过渡金属层有选择性的蚀刻化学品。在第二蚀刻步骤期间，过渡金属层用作硬掩模，以通过蚀刻介电层的部分形成与通孔图案相对应的接触孔。

69. 发明授权

US06436766B1 Process for fabricating high density memory cells using a polysilicon hard mask 有权
标题翻译：使用多晶硅硬掩模制造高密度存储单元的方法
公开(公告)号：US06436766B1
公开(公告)日：2002-08-20
申请号：US09430493
申请日：1999-10-29
申请人： Bharath Rangarajan , David K. Foote , Fei Wang , Dawn M. Hopper , Stephen K. Park , Jack Thomas , Mark Chang , Mark Ramsbey
发明人： Bharath Rangarajan , David K. Foote , Fei Wang , Dawn M. Hopper , Stephen K. Park , Jack Thomas , Mark Chang , Mark Ramsbey
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is preferably made from polysilicon or silicon. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then removed, preferably using a plasma etch process.
摘要翻译：一种用于在二位EEPROM器件中制造存储单元的方法，包括形成覆盖在半导体衬底上的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。硬掩模优选由多晶硅或硅制成。该工艺还包括用硼掺杂导致在半导体衬底中形成p型区域的半导体衬底，并且用诸如砷的n型掺杂剂掺杂半导体衬底，从而在半导体衬底中形成n型区域。然后对暴露的ONO层进行蚀刻以暴露半导体衬底的一部分，并且在半导体衬底上形成位线氧化物区域。然后去除硬掩模，优选使用等离子体蚀刻工艺。

70. 发明授权

US06400030B1 Self-aligning vias for semiconductors 有权
标题翻译：半导体自对准通孔
公开(公告)号：US06400030B1
公开(公告)日：2002-06-04
申请号：US09583817
申请日：2000-05-30
申请人： Fei Wang , Robin Cheung , Mark S. Chang , Richard J. Huang , Angela T. Hui
发明人： Fei Wang , Robin Cheung , Mark S. Chang , Richard J. Huang , Angela T. Hui
IPC分类号： H01L2348
CPC分类号： H01L21/76897 , H01L21/76802
摘要： An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via nitride layer, and a via resist are sequentially deposited on the first channel and the first oxide layer. The via resist is photolithographically developed with rectangular cross-section vias greater than the width of the channels and the via nitride layer is etched to the rectangular cross-section. A second channel oxide layer and a second channel resist are sequentially deposited on the via nitride layer and the exposed via oxide layer. The second channel resist is photolithographically developed with the second channels and an anisotropic oxide etch etches the second channels and rectangular box vias down to the stop nitride layer. The stop nitride layer is nitride etched in the rectangular via configuration and conductive material is damascened into the second channels and the via to be chemical-mechanical polished to form the interconnections between two levels of channels.
摘要翻译：具有半导体器件的集成电路通过镶嵌在器件上方的第一氧化物层中的第一导电沟道连接。在第一沟道和第一氧化物层上顺序地沉积有终止氮化物层，通孔氧化物层，通路氮化物层和通路保护层。通孔抗蚀剂被光刻显影，具有大于通道宽度的矩形横截面通孔，并且通孔氮化物层被蚀刻到矩形横截面。第二沟道氧化物层和第二沟道抗蚀剂依次沉积在通孔氮化物层和暴露的通孔氧化物层上。第二通道抗蚀剂用第二通道光刻显影，并且各向异性氧化物蚀刻将第二通道和矩形盒通孔蚀刻到固定氮化物层。阻挡氮化物层以矩形通孔结构进行氮化蚀刻，并且导电材料被镶嵌到第二通道中，并且通孔被化学机械抛光以形成两个通道级之间的互连。

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