专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20090155976A1 ATOMIC LAYER DEPOSITION OF DY-DOPED HFO2 FILMS AS GATE DIELECTRICS 有权
标题翻译：作为栅极电介质的DY-DOPED HFO2膜的原子层沉积
公开(公告)号：US20090155976A1
公开(公告)日：2009-06-18
申请号：US12390920
申请日：2009-02-23
申请人： Kie Y. Ahn , Leonard Forbes
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L21/82 , H01L21/30 , H01L21/8239
CPC分类号： H01L21/02181 , C23C16/405 , C23C16/45529 , H01L21/022 , H01L21/0228 , H01L21/28194 , H01L21/3141 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/78
摘要： The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium oxide (HfO2) doped with dysprosium (Dy) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing hafnium oxide using atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing dysprosium oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. A dielectric layer of dysprosium doped hafnium oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memories, or as a dielectric in NROM devices, because the high dielectric constant (high-k) of the film provides the functionality of a thinner silicon dioxide film, and because the reduced leakage current of the dielectric layer when the percentage of dysprosium doping is optimized improves memory function.
摘要翻译：使用原子层沉积（ALD）形成掺杂有镝（Dy）的氧化铪（HfO 2）的电介质层和制造这种组合栅极和电介质层的方法产生用于各种电子器件的可靠结构。形成电介质结构包括使用前体化学品将原子层沉积物沉积到衬底表面上，然后使用前体化学品将氧化镝沉积到衬底上，并重复形成薄的层压结构。镝掺杂氧化铪的电介质层可以用作MOSFET的栅极绝缘体，作为DRAM中的电容器电介质，作为闪存中的隧道栅极绝缘体，或者作为NROM器件中的电介质，因为高介电常数（高k）的薄膜提供更薄的二氧化硅膜的功能，并且由于优化了镝掺杂的百分比时介电层的漏电流减小，从而提高记忆功能。

62. 发明授权

US07544596B2 Atomic layer deposition of GdScO3 films as gate dielectrics 有权
标题翻译： GdScOsub3薄膜的原子层沉积作为栅极电介质
公开(公告)号：US07544596B2
公开(公告)日：2009-06-09
申请号：US11215507
申请日：2005-08-30
申请人： Kie Y. Ahn , Leonard Forbes
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/02192 , C23C16/40 , C23C16/45529 , C23C16/4554 , C23C16/45553 , H01L21/022 , H01L21/0228 , H01L21/28194 , H01L21/28273 , H01L21/28282 , H01L21/3142 , H01L21/31604 , H01L28/40 , H01L29/513 , H01L29/517 , H01L29/788 , H01L29/792
摘要： The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of gadolinium oxide (Gd2O3) and scandium oxide (Sc2O3) acting as a single dielectric layer with a formula of GdScO3, and a method of fabricating such a dielectric layer, is described that produces a reliable structure with a high dielectric constant (high k) for use in a variety of electronic devices. The dielectric structure is formed by depositing gadolinium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing scandium oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. Such a dielectric may be used as gate insulator of a MOSFET, a capacitor dielectric in a DRAM, as tunnel gate insulators in flash memories, or as a NROM dielectric, because the high dielectric constant (high k) of the film provides the functionality of a much thinner silicon dioxide film.
摘要翻译：使用原子层沉积（ALD）形成氧化钆（Gd 2 O 3）和氧化钪（Sc 2 O 3）的纳米层间电介质，其作为具有下式的GdScO 3的单个电介质层以及制造这种电介质层的方法其产生用于各种电子器件的具有高介电常数（高k）的可靠结构。通过使用前体化学品，通过原子层沉积将氧化钆沉积到衬底表面上，然后使用前体化学品将氧化钪沉积到衬底上并重复形成薄层压结构，形成电介质结构。这种电介质可以用作MOSFET的栅绝缘体，DRAM中的电容器电介质，作为闪存中的隧道栅绝缘体，或者作为NROM电介质，因为膜的高介电常数（高k）提供了更薄的二氧化硅膜。

63. 发明授权

US07528440B2 Vertical gain cell 有权
标题翻译：垂直增益单元
公开(公告)号：US07528440B2
公开(公告)日：2009-05-05
申请号：US11689896
申请日：2007-03-22
申请人： Leonard Forbes
发明人： Leonard Forbes
IPC分类号： H01L29/94
CPC分类号： H01L27/108 , H01L27/0705 , H01L27/10802 , H01L27/10841 , H01L29/7841
摘要： A vertical cell is realized. The cell includes a first vertical metal oxide semiconductor (MOS) transistor having a body between a drain region and a source region and a second vertical MOS transistor including at least a portion of the body of the first vertical MOS transistor.
摘要翻译：实现了垂直单元。电池包括具有在漏极区域和源极区域之间的主体的第一垂直金属氧化物半导体（MOS）晶体管和包括第一垂直MOS晶体管的主体的至少一部分的第二垂直MOS晶体管。

64. 发明申请

US20090108363A1 STRAINED SEMICONDUCTOR, DEVICES AND SYSTEMS AND METHODS OF FORMATION 有权
标题翻译：应变半导体，器件和系统及其形成方法
公开(公告)号：US20090108363A1
公开(公告)日：2009-04-30
申请号：US12346281
申请日：2008-12-30
申请人： Leonard Forbes , Paul A. Farrar
发明人： Leonard Forbes , Paul A. Farrar
IPC分类号： H01L27/088 , H01L29/06
CPC分类号： H01L29/7846 , H01L21/26506 , H01L21/76232 , H01L29/6659 , H01L29/7833
摘要： In various method embodiments, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region. The device region has a channel region, and the isolation regions have volumes. The volumes of the isolation regions are adjusted to provide the channel region with a desired strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from a crystalline region to an amorphous region to expand the volumes of the isolation regions and provide the channel region with a desired compressive strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from an amorphous region to a crystalline region to contract the volumes of the isolation regions to provide the channel region with a desired tensile strain. Other aspects and embodiments are provided herein.
摘要翻译：在各种方法实施例中，器件区域被限定在半导体衬底中，并且隔离区域被限定为与器件区域相邻。器件区域具有通道区域，隔离区域具有体积。调整隔离区的体积以提供具有所需应变的通道区。在各种实施例中，调节隔离区域的体积包括将隔离区域从结晶区域转换为非晶区域以扩大隔离区域的体积并且为通道区域提供期望的压缩应变。在各种实施例中，调节隔离区域的体积包括将隔离区域从非晶区域转换为结晶区域以收缩隔离区域的体积，以提供具有期望拉伸应变的通道区域。本文提供了其它方面和实施例。

65. 发明授权

US07517783B2 Molybdenum-doped indium oxide structures and methods 有权
标题翻译：钼掺杂氧化铟结构及方法
公开(公告)号：US07517783B2
公开(公告)日：2009-04-14
申请号：US11706944
申请日：2007-02-13
申请人： Kie Y. Ahn , Leonard Forbes
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L21/44 , H01L31/18 , H01L23/52
CPC分类号： H01L31/1884 , H01L27/14643 , H01L27/14685 , H01L31/022466 , Y02E10/50
摘要： Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain indium and monolayers that contain molybdenum are deposited onto a substrate and subsequently processed to form molybdenum-doped indium oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.
摘要翻译：显示形成透明导电氧化物的方法和通过这些方法形成的器件。含有铟的单层和含有钼的单层沉积到基板上，随后进行处理以形成掺杂钼的氧化铟。所得到的透明导电氧化物包括诸如无定形或纳米晶体微结构的特性。包括用这些方法形成的透明导电氧化物的器件具有比衬底形貌更好的阶梯覆盖和更坚固的膜机械性能。

66. 发明申请

US20090072303A9 NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS 有权
标题翻译： NROM存储单元，存储阵列，相关设备和方法
公开(公告)号：US20090072303A9
公开(公告)日：2009-03-19
申请号：US11346049
申请日：2006-02-02
申请人： Kirk Prall , Leonard Forbes
发明人： Kirk Prall , Leonard Forbes
IPC分类号： H01L29/94
CPC分类号： H01L29/7926 , G11C11/5692 , G11C16/0466 , G11C16/0475 , H01L27/11556 , H01L27/11582 , H01L29/7889 , H01L29/7923
摘要： An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.
摘要翻译：配置为存储每个F2的至少一个位的存储器单元的阵列包括基本上垂直的结构，提供间隔距离等于阵列的最小间距的一半的距离的电子存储器功能。提供电子存储器功能的结构被配置为存储每个门多于一个位。阵列还包括到存储器单元的电接触，包括基本垂直的结构。电池可以被编程为具有与栅极绝缘体相邻的多个电荷水平中的一个，其邻近于第一源极/漏极区域，使得沟道区域具有第一电压阈值区域（Vt1）和第二电压阈值区域（Vt2）并且使得编程单元以降低的漏极源电流工作。

67. 发明授权

US07501329B2 Wafer gettering using relaxed silicon germanium epitaxial proximity layers 失效
标题翻译：使用松弛硅锗外延接近层的晶圆吸气
公开(公告)号：US07501329B2
公开(公告)日：2009-03-10
申请号：US10443339
申请日：2003-05-21
申请人： Leonard Forbes
发明人： Leonard Forbes
IPC分类号： H01L21/322
CPC分类号： H01L21/3221 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02658 , H01L21/26506 , H01L29/1054 , Y10S438/933
摘要： One aspect of this disclosure relates to a method for creating proximity gettering sites in a semiconductor wafer. In various embodiments of this method, a relaxed silicon germanium region is formed to be proximate to a device region on the semiconductor wafer. The relaxed silicon germanium region generates defects to getter impurities from the device region. In various embodiments, an ultra high vacuum chemical vapor deposition (UHV CVD) process is performed to epitaxially form the relaxed silicon germanium gettering region. In various embodiments, forming the relaxed silicon germanium gettering region includes implanting germanium ions into a silicon substrate with a desired dose and energy to form a silicon region containing germanium ions and heat treating the substrate to regrow a crystalline silicon layer over a resulting silicon germanium layer using a solid phase epitaxial (SPE) process. Other aspects are provided herein.
摘要翻译：本公开的一个方面涉及一种用于在半导体晶片中创建邻近吸杂位点的方法。在该方法的各种实施例中，形成松弛的硅锗区域以接近半导体晶片上的器件区域。松弛的硅锗区域产生缺陷以从器件区域吸收杂质。在各种实施例中，执行超高真空化学气相沉积（UHV CVD）工艺以外延形成松弛的硅锗吸气区。在各种实施例中，形成松弛的硅锗吸气区域包括以期望的剂量和能量将锗离子注入到硅衬底中，以形成含有锗离子的硅区域并热处理衬底，以在所得的硅锗层上再结晶硅层使用固相外延（SPE）工艺。本文提供了其他方面。

68. 发明授权

US07498247B2 Atomic layer deposition of Hf3N4/HfO2 films as gate dielectrics 有权
标题翻译： Hf3N4 / HfO2薄膜的原子层沉积作为栅极电介质
公开(公告)号：US07498247B2
公开(公告)日：2009-03-03
申请号：US11063717
申请日：2005-02-23
申请人： Kie Y. Ahn , Leonard Forbes
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L21/3205 , H01L21/314 , H01L21/316 , H01L21/318
CPC分类号： H01L21/0228 , C23C16/34 , C23C16/405 , C23C16/45529 , H01L21/02181 , H01L21/022 , H01L21/28194 , H01L21/28202 , H01L21/3141 , H01L21/3143 , H01L21/318 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78
摘要： The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium nitride (Hf3N4) and hafnium oxide (HfO2) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing hafnium oxide using precursor chemicals, followed by depositing hafnium nitride using precursor chemicals, and repeating to form the laminate structure. Alternatively, the hafnium nitride may be deposited first followed by the hafnium nitride. Such a dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric in a DRAM, or a tunnel gate insulator in flash memories, because the high dielectric constant (high-k) of the film provides the functionality of a thinner silicon dioxide film, and because of the reduced leakage current when compared to an electrically equivalent thickness of silicon dioxide.
摘要翻译：使用原子层沉积（ALD）形成氮化铪（Hf 3 N 4）和氧化铪（HfO 2）的介电层以及制造这种组合栅极和电介质层的方法产生用于各种电子器件的可靠结构。形成电介质结构包括使用前体化学品沉积氧化铪，然后使用前体化学品沉积铪氮化物，并重复形成层压结构。或者，首先可以沉积氮化铪，然后氮化铪。这样的电介质层可以用作MOSFET的栅极绝缘体，DRAM中的电容器电介质或闪存中的隧道栅极绝缘体，因为膜的高介电常数（高k）提供了更薄的功能并且与电二氧化硅的电等效厚度相比，由于漏电流减小。

69. 发明授权

US07491608B2 Vertical transistor with horizontal gate layers 有权
标题翻译：具有水平栅极层的垂直晶体管
公开(公告)号：US07491608B2
公开(公告)日：2009-02-17
申请号：US11496342
申请日：2006-07-31
申请人： Leonard Forbes
发明人： Leonard Forbes
IPC分类号： H01L21/336
CPC分类号： G11C16/0408 , G11C16/0416 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42336 , H01L29/66825 , H01L29/7881 , H01L29/7885
摘要： Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable read only memory (EEPROM) or a logic array in a high density field programmable logic array (FPLA). The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will provide an indication of the stored data at this location in the memory array within the EEPROM or will act as the absence of a transistor at this location in the logic array within the FPLA. The memory array or the logic array includes densely packed cells, each cell having a semiconductor pillar providing shared source and drain regions for two vertical body transistors that have control gates overlaying floating gates distributed on opposing sides of the semiconductor pillar. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data or to represent a logic function, an area of only 2F2 is needed per respective bit of data or bit of logic, where F is the minimum lithographic feature size.
摘要翻译：具有相邻水平栅极层的垂直体晶体管用于在高密度闪存电可擦除可编程只读存储器（EEPROM）或高密度现场可编程逻辑阵列（FPLA）中的逻辑阵列上形成存储器阵列。晶体管是具有电隔离（浮置）栅极的场效应晶体管（FET），其控制源极区域和漏极区域之间的导电。如果特定的浮动栅极被存储的电子充电，则晶体管将不会导通，并且将在EEPROM内的存储器阵列的该位置处提供所存储的数据的指示，或将作为在该位置处的晶体管的不存在 FPLA内的逻辑阵列。存储器阵列或逻辑阵列包括密集堆叠的单元，每个单元具有半导体柱，为两个垂直体晶体管提供共享的源极和漏极区域，其具有覆盖分布在半导体柱的相对侧上的浮动栅极的控制栅极。提供了体半导体和绝缘体上硅实施例。如果使用浮动栅极晶体管来存储单个数据位或表示逻辑功能，则每个相应的数据位或逻辑位只需要2F2的区域，其中F是最小光刻特征尺寸。

70. 发明授权

US07489545B2 Memory utilizing oxide-nitride nanolaminates 有权
标题翻译：记忆利用氧化物氮化物的Nanolaminates
公开(公告)号：US07489545B2
公开(公告)日：2009-02-10
申请号：US11492749
申请日：2006-07-25
申请人： Leonard Forbes , Kie Y. Ahn
发明人： Leonard Forbes , Kie Y. Ahn
IPC分类号： G11C16/04
CPC分类号： H01L27/11568 , G11C11/5671 , G11C16/0416 , H01L27/115 , H01L29/792
摘要： Structures, systems and methods for transistors utilizing oxide-nitride nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide-nitride nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers.
摘要翻译：提供了使用氧化物氮化物纳米层压材料的晶体管的结构，系统和方法。一个晶体管实施例包括第一源极/漏极区域，第二源极/漏极区域和它们之间的沟道区域。栅极通过栅极绝缘体与沟道区分离。栅极绝缘体包括氧化物 - 氮化物纳米级层，以在由氧化物 - 氮化物纳米级层的不同电子亲和力形成的势阱中捕获电荷。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式