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    • 61. 发明申请
    • METHOD OF IDENTIFYING A COUNTERFEIT BILL USING A PORTABLE TERMINAL
    • 使用便携式终端识别违反条例的方法
    • US20130034290A1
    • 2013-02-07
    • US13564347
    • 2012-08-01
    • Dong-Hyuk LEEJung-Kee LEESeong-Taek HWANGDo-Hyeon KIM
    • Dong-Hyuk LEEJung-Kee LEESeong-Taek HWANGDo-Hyeon KIM
    • G06K9/62
    • G07D7/2025G06F17/30244G06K9/2018G07D7/12G07D7/202
    • A method and a portable terminal for identifying a counterfeit bill. The method includes receiving, by the portable terminal, an image of a bill photographed using visible rays and an image of the bill photographed using infrared rays; determining a denomination of the bill by comparing the image photographed using the visible rays with a denomination database; obtaining correction information for making the image photographed using the visible rays correspond to a corresponding bill image in the denomination database; forming a corrected image by correcting the image photographed using the infrared rays using the correction information; binary-coding the corrected image; and determining whether the bill is counterfeit by comparing the binary-coded corrected image with an image of the corresponding bill pre-stored in a genuine bill database.
    • 一种用于识别伪钞的方法和便携式终端。 该方法包括:由便携式终端接收使用可见光拍摄的纸币的图像和使用红外线拍摄的纸币的图像; 通过将使用可见光拍摄的图像与面额数据库进行比较来确定纸币的面额; 获取用于使使用可见光拍摄的图像的校正信息对应于面额数据库中的对应的纸币图像; 通过使用校正信息校正使用红外线拍摄的图像来形成校正图像; 二进制编码校正图像; 以及通过将所述二进制编码的校正图像与预先存储在真实账单数据库中的对应账单的图像进行比较来确定所述账单是否是伪造的。
    • 68. 发明授权
    • Semiconductor memory device having refresh circuit and word line activating method therefor
    • 具有刷新电路和字线激活方法的半导体存储器件
    • US07929369B2
    • 2011-04-19
    • US12453164
    • 2009-04-30
    • Dong-Hyuk LeeChi-Sung Oh
    • Dong-Hyuk LeeChi-Sung Oh
    • G11C7/00
    • G11C11/406G11C11/40618G11C11/4085
    • A semiconductor memory device includes a memory cell array having at least one memory bank. The memory bank being divided into memory blocks such that the memory blocks have a block position including at least one edge memory block at an edge of the memory bank and at least one non-edge memory block. Each memory block includes a plurality of memory cells. Each memory cell associated with at least one bit line and at least one word line. The semiconductor memory device includes a refresh execution circuit configured to activate a less than or equal number of word lines one at a time during a refresh operation for the memory cells in the edge memory block as activated one at a time during a refresh operation for the memory cells in the non-edge memory block.
    • 半导体存储器件包括具有至少一个存储体的存储单元阵列。 存储体被分成存储块,使得存储块具有块位置,该块位置包括在存储体的边缘处的至少一个边缘存储器块和至少一个非边缘存储器块。 每个存储块包括多个存储单元。 每个存储器单元与至少一个位线和至少一个字线相关联。 所述半导体存储器件包括刷新执行电路,所述刷新执行电路被配置为在所述边缘存储器块中的存储器单元的刷新操作期间一次一个地激活小于或等于数量的字线, 非边缘存储器块中的存储单元。
    • 70. 发明授权
    • Multiprocessor system and method thereof
    • 多处理器系统及其方法
    • US07870326B2
    • 2011-01-11
    • US11819601
    • 2007-06-28
    • Yun-Hee ShinHan-Gu SohnYoung-Min LeeHo-Cheol LeeSoo-Young KimDong-Hyuk LeeChang-Ho Lee
    • Yun-Hee ShinHan-Gu SohnYoung-Min LeeHo-Cheol LeeSoo-Young KimDong-Hyuk LeeChang-Ho Lee
    • G06F12/00
    • G06F12/02
    • A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.
    • 提供了一种多处理器系统及其方法。 示例性多处理器系统可以包括第一和第二处理器,具有存储单元阵列的动态随机存取存储器,所述存储单元阵列包括通过第一端口耦合到第一处理器的第一存储器组,耦合到第二存储器组的第二存储器组和第四存储器组 处理器通过第二端口和通过第一和第二端口与第一和第二处理器共享并连接的第三存储器组,以及用于分配存储体地址以选择单独地选择第一和第二存储体的存储体地址分配单元,如同样的 通过第一和第二端口的存储器地址,使得第一和第二存储器组的起始地址在引导中变得相等,并且通过第一和第二端口分配存储体地址以选择第三存储体作为不同的存储体地址, 通过第二个端口,银行地址选择第四个存储器,作为与银行地址相同的银行地址,选择第三个存储器 银行通过第一个港口。