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    • 2. 发明申请
    • FLEXIBLE NETWORK SECURITY SYSTEM AND METHOD FOR PERMITTING TRUSTED PROCESS
    • 灵活的网络安全系统和允许受理过程的方法
    • US20130283366A1
    • 2013-10-24
    • US13924504
    • 2013-06-21
    • Dong-Hyuk LEE
    • Dong-Hyuk LEE
    • H04L29/06
    • H04L63/0236
    • Disclosed herein is a flexible network security system and method for permitting a trusted process. The system includes a port monitoring unit for extracting information about a server port being used through a network communication program, an internal permitted program storage for extracting information about a program for which communication is permitted by the firewall, and registering the extracted information, an internal permitted by the firewall, and registering the extracted information, an internal permitted port storage, if the port monitoring unit extracts the information about the server port being used using the program registered in the internal permitted program storage, registering the extracted information about the server port; and a device for making the firewall flexible, determining whether a destination port of a packet of inbound traffic has been registered in the internal permitted port storage, and if the destination port has not been registered, transmitting the corresponding packet to the firewall, and if the destination port has been registered, allowing the corresponding packet to bypass the firewall.
    • 这里公开了一种用于允许可信过程的灵活的网络安全系统和方法。 该系统包括用于提取关于通过网络通信程序使用的服务器端口的信息的端口监视单元,用于提取关于防火墙允许通信的程序的信息的内部许可程序存储器,以及登记提取的信息的内部 如果端口监视单元使用在内部许可程序存储器中注册的程序提取关于正在使用的服务器端口的信息,则登记所提取的信息,以及注册提取的信息,内部许可端口存储,登记提取的关于服务器端口的信息 ; 以及用于使防火墙灵活的装置,确定入境业务的分组的目的地端口是否已经登记在内部允许端口存储器中,并且如果目的地端口尚未注册,则将相应的分组发送到防火墙,以及如果 目的端口已经注册,允许相应的数据包绕过防火墙。
    • 4. 发明授权
    • Flexible network security system and method for permitting trusted process
    • 灵活的网络安全系统和允许信任过程的方法
    • US08544078B2
    • 2013-09-24
    • US10582127
    • 2004-12-27
    • Dong-Hyuk Lee
    • Dong-Hyuk Lee
    • G06F9/00G06F15/16G06F17/00
    • H04L63/0236
    • A flexible network security system and method is provided for permitting a trusted process. The system includes a port monitoring unit for extracting information about a server port being used through a network communication program, an internal permitted program storage for extracting information about a program for which communication is permitted by the firewall and registering the extracted information, an internal permitted port storage registering the extracted information if the network communication program is registered in the internal permitted program storage; and a device for making the firewall flexible, determining whether a destination port of a packet of inbound traffic has been registered in the internal permitted port storage, and if the destination port has not been registered, transmitting the corresponding packet to the firewall, and if the destination port has been registered, allowing the corresponding packet to bypass the firewall.
    • 提供了一种灵活的网络安全系统和方法,用于允许受信任的进程。 该系统包括用于提取关于通过网络通信程序使用的服务器端口的信息的端口监视单元,用于提取关于防火墙允许通信的程序的信息并登记所提取的信息的内部许可程序存储器,内部允许 如果网络通信程序被登记在内部许可程序存储器中,则端口存储器登记提取的信息; 以及用于使防火墙灵活的装置,确定入境业务的分组的目的地端口是否已经登记在内部允许端口存储器中,并且如果目的地端口尚未注册,则将相应的分组发送到防火墙,以及如果 目的端口已经注册,允许相应的数据包绕过防火墙。
    • 5. 发明授权
    • Memory device and memory system comprising same
    • 包含其的存储器件和存储器系统
    • US08473694B2
    • 2013-06-25
    • US12885728
    • 2010-09-20
    • Dong-Hyuk LeeJung-Bae LeeKi-Won Park
    • Dong-Hyuk LeeJung-Bae LeeKi-Won Park
    • G06F12/00
    • G11C29/08G11C11/401
    • A memory device comprises a memory cell array comprising a plurality of memory blocks each comprising a plurality of memory cells and a control setting circuit. The control setting circuit divides the memory blocks into at least first and second groups based on whether each of the memory blocks comprises at least one substandard memory cell, and sets individually control parameters of the first and second groups. The substandard memory cells are identified based on test results of the memory cells with respect to at least one of the control parameters. Each memory block in the first group comprises at least one substandard memory cell, and each memory block in the second group comprises no substandard memory cell.
    • 存储器装置包括存储单元阵列,其包括多个存储块,每个存储块包括多个存储单元和控制设置电路。 控制设置电路基于每个存储器块是否包括至少一个不合标准的存储器单元,将存储器块分成至少第一组和第二组,并且分别设置第一组和第二组的控制参数。 基于存储器单元相对于至少一个控制参数的测试结果来识别不合格存储器单元。 第一组中的每个存储器块包括至少一个不合标准存储器单元,并且第二组中的每个存储器块都不包括不合格存储器单元。
    • 7. 发明授权
    • Semiconductor memory device in which a method of controlling a BIT line sense amplifier is improved
    • 提高了控制BIT线读出放大器的方法的半导体存储器件
    • US08120980B2
    • 2012-02-21
    • US12686561
    • 2010-01-13
    • Chi-Sung OhJung-Bae LeeDong-Hyuk Lee
    • Chi-Sung OhJung-Bae LeeDong-Hyuk Lee
    • G11C7/02
    • G11C7/065G11C5/025G11C7/08G11C11/4091
    • A semiconductor memory device includes a sense amplifier, a sense amplifier driving signal driver, and a controller. The sense amplifier is configured to sense and amplify a signal of a bit line and a signal of a complementary bit line in response to a sense amplifier driving signal. The sense amplifier driving signal driver includes a first driving signal driver configured to drive via a transmission line the sense amplifier driving signal in response to a first sense amplifier control signal, and a second driving signal driver configured to drive via the transmission line the sense amplifier driving signal in response to a second sense amplifier control signal. The controller activates the first sense amplifier control signal in response to an active command, and toggles the second sense amplifier control signal while the first sense amplifier control signal is activated.
    • 半导体存储器件包括读出放大器,读出放大器驱动信号驱动器和控制器。 读出放大器被配置为响应于读出放大器驱动信号来检测和放大位线的信号和互补位线的信号。 读出放大器驱动信号驱动器包括:第一驱动信号驱动器,被配置为响应于第一读出放大器控制信号经由传输线驱动读出放大器驱动信号;以及第二驱动信号驱动器,被配置为通过传输线驱动读出放大器 响应于第二读出放大器控制信号的驱动信号。 控制器响应于有效命令激活第一读出放大器控制信号,并且在第一读出放大器控制信号被激活时切换第二读出放大器控制信号。
    • 10. 发明申请
    • MEMORY DEVICE AND MEMORY SYSTEM COMPRISING SAME
    • 存储器件和包含其的存储器系统
    • US20110072205A1
    • 2011-03-24
    • US12885728
    • 2010-09-20
    • Dong-Hyuk LEEJung-Bae LEEKi-Won PARK
    • Dong-Hyuk LEEJung-Bae LEEKi-Won PARK
    • G06F12/06
    • G11C29/08G11C11/401
    • A memory device comprises a memory cell array comprising a plurality of memory blocks each comprising a plurality of memory cells and a control setting circuit. The control setting circuit divides the memory blocks into at least first and second groups based on whether each of the memory blocks comprises at least one substandard memory cell, and sets individually control parameters of the first and second groups. The substandard memory cells are identified based on test results of the memory cells with respect to at least one of the control parameters. Each memory block in the first group comprises at least one substandard memory cell, and each memory block in the second group comprises no substandard memory cell.
    • 存储器装置包括存储单元阵列,其包括多个存储块,每个存储块包括多个存储单元和控制设置电路。 控制设置电路基于每个存储器块是否包括至少一个不合标准的存储器单元,将存储器块分成至少第一组和第二组,并且分别设置第一组和第二组的控制参数。 基于存储器单元相对于至少一个控制参数的测试结果来识别不合格存储器单元。 第一组中的每个存储器块包括至少一个不合标准存储器单元,并且第二组中的每个存储器块都不包括不合格存储器单元。