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1. 发明授权

US08209527B2 Memory system and memory management method including the same 有权
标题翻译：内存系统和内存管理方法包括相同
公开(公告)号：US08209527B2
公开(公告)日：2012-06-26
申请号：US12430722
申请日：2009-04-27
申请人： Jeon-Taek Im , Young-Min Lee , Han-Gu Sohn , Jin-Hyoung Kwon , Sung-Jae Byun , Yun-Tae Lee , Gyoo-Cheol Hwang
发明人： Jeon-Taek Im , Young-Min Lee , Han-Gu Sohn , Jin-Hyoung Kwon , Sung-Jae Byun , Yun-Tae Lee , Gyoo-Cheol Hwang
IPC分类号： G06F15/177
CPC分类号： G06F12/0607 , G06F9/4405 , G06F9/445 , G06F12/0638 , G06F15/177 , G06F2212/2022 , G11C8/16
摘要： A booting method of a digital processing having a first processor and a second processor is provided. An interface between the first processor and the outside is stopped. A second processor program code is transmitted to a second memory from a first memory. A second stage loader (SSL) for the first processor is transmitted to a buffer of the second processor from the first memory. A first processor program code is transmitted to the second memory from the first memory under the control of the second processor and an interface between the first processor and the outside is resumed. The first processor program code is downloaded fast into the second memory to decrease booting time of the digital processing system.
摘要翻译：提供了具有第一处理器和第二处理器的数字处理的启动方法。第一处理器和外部之间的接口被停止。第二处理器程序代码从第一存储器发送到第二存储器。用于第一处理器的第二级装载器（SSL）从第一存储器发送到第二处理器的缓冲器。第一处理器程序代码在第二处理器的控制下从第一存储器发送到第二存储器，并且恢复第一处理器和外部之间的接口。第一处理器程序代码被快速下载到第二个存储器中以减少数字处理系统的引导时间。

2. 发明授权

US08122188B2 Method of controlling refresh operation in multi-port DRAM and a memory system using the method 有权
标题翻译：控制多端口DRAM中刷新操作的方法和使用该方法的存储系统
公开(公告)号：US08122188B2
公开(公告)日：2012-02-21
申请号：US11459895
申请日：2006-07-25
申请人： Han-Gu Sohn , Sei-Jin Kim
发明人： Han-Gu Sohn , Sei-Jin Kim
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/1636 , G11C7/1075 , G11C8/12 , G11C8/16 , G11C11/406 , G11C11/40603 , G11C11/40611 , G11C11/40618 , Y02D10/14
摘要： A multi-port memory system includes a shared memory bank, and a refresh controller coupled to the shared memory bank, and configured to selectively apply refresh commands from multiple processors to the shared memory bank.
摘要翻译：多端口存储器系统包括共享存储器组和耦合到共享存储器组的刷新控制器，并被配置为选择性地将来自多个处理器的刷新命令应用于共享存储体。

3. 发明授权

US08032695B2 Multi-path accessible semiconductor memory device with prevention of pre-charge skip 失效
标题翻译：具有防止预充电跳跃的多路径可访问半导体存储器件
公开(公告)号：US08032695B2
公开(公告)日：2011-10-04
申请号：US12151946
申请日：2008-05-09
申请人： Jin-Hyoung Kwon , Han-Gu Sohn , Dong-Woo Lee
发明人： Jin-Hyoung Kwon , Han-Gu Sohn , Dong-Woo Lee
IPC分类号： G06F12/16 , G06F12/00
CPC分类号： G06F13/1663 , G11C7/1075 , G11C11/4094
摘要： A multiprocessor system includes first and second processors and a multi-path accessible semiconductor memory device including a shared memory area and a pseudo operation execution unit. The shared memory area is accessible by the first and second processors according to a page open policy. The pseudo operation execution unit responds to a virtual active command from one of the first and second processors to close a last-opened page. The virtual active command is generated with a row address not corresponding to any row of the shared memory area. For example, bit-lines of a last accessed row are pre-charged for closing the last-opened page.
摘要翻译：多处理器系统包括第一和第二处理器以及包括共享存储器区域和伪操作执行单元的多路径可访问半导体存储器件。根据页面打开策略，共享存储器区域可由第一和第二处理器访问。伪操作执行单元响应来自第一和第二处理器之一的虚拟活动命令以关闭最后打开的页面。生成虚拟活动命令，其中行地址不对应于共享存储器区域的任何行。例如，最后访问的行的位线是预先关闭最后打开的页面的。

4. 发明申请

US20100153637A1 Arbitration for memory device with commands 有权
公开(公告)号：US20100153637A1
公开(公告)日：2010-06-17
申请号：US12658911
申请日：2010-02-17
申请人： Young-Min Lee , Sung-Jae Byun , Han-Gu Sohn , Gyoo-Cheol Hwang
发明人： Young-Min Lee , Sung-Jae Byun , Han-Gu Sohn , Gyoo-Cheol Hwang
IPC分类号： G06F12/00 , G06F13/14
CPC分类号： G11C8/16 , G11C7/1075 , G11C11/406 , G11C11/40603 , G11C11/40611
摘要： A plurality of masters arbitrate for access to a shared memory device, such as a SDRAM (synchronous dynamic random access memory), amongst themselves using software and arbitration interfaces. The masters generate additional commands upon arbitration, such as MRS and PALL commands, for prevention of collision of commands, refresh starvation, and/or a missing pre-charge operation in the shared memory device.

5. 发明申请

US20090089545A1 MULTI PROCESSOR SYSTEM HAVING MULTIPORT SEMICONDUCTOR MEMORY WITH PROCESSOR WAKE-UP FUNCTION 失效
标题翻译：具有处理器唤醒功能的多功能半导体存储器的多处理器系统
公开(公告)号：US20090089545A1
公开(公告)日：2009-04-02
申请号：US12235816
申请日：2008-09-23
申请人： Jin-Hyoung KWON , Han-Gu SOHN , Kwang-Myeong JANG
发明人： Jin-Hyoung KWON , Han-Gu SOHN , Kwang-Myeong JANG
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F15/167
摘要： A multiport semiconductor memory device having a processor wake-up function and multiprocessor system employing the same is provided. The multiprocessor system includes: a first processor configured to perform a first predetermined task; a second processor configured to perform a second predetermined task; and a multiport semiconductor memory device coupled to the first processor and the second processor, the multiport semiconductor memory device including: a memory cell array having at least one shared memory area; a first port coupled to the at least one shared memory area; a second port coupled to the at least one shared memory area; and a wake-up signal generator, the first processor being coupled to the at least one shared memory area via the first port, the second processor being coupled to the at least one shared memory area via the second port, the wake-up signal generator being coupled to the first processor and the second processor.
摘要翻译：提供具有处理器唤醒功能的多端口半导体存储器件和采用该多端口半导体存储器件的多处理器系统。多处理器系统包括：第一处理器，被配置为执行第一预定任务; 配置为执行第二预定任务的第二处理器; 以及耦合到所述第一处理器和所述第二处理器的多端口半导体存储器件，所述多端口半导体存储器件包括：具有至少一个共享存储区域的存储单元阵列; 耦合到所述至少一个共享存储器区域的第一端口; 耦合到所述至少一个共享存储区域的第二端口; 以及唤醒信号发生器，所述第一处理器经由所述第一端口耦合到所述至少一个共享存储区域，所述第二处理器经由所述第二端口耦合到所述至少一个共享存储区域，所述唤醒信号发生器耦合到第一处理器和第二处理器。

6. 发明授权

US07480776B2 Circuits and methods for providing variable data I/O width for semiconductor memory devices 有权
标题翻译：用于为半导体存储器件提供可变数据I / O宽度的电路和方法
公开(公告)号：US07480776B2
公开(公告)日：2009-01-20
申请号：US10732868
申请日：2003-12-10
申请人： Han-gu Sohn , Hai-jeong Sohn , Sei-jin Kim , Woo-seop Jeong
发明人： Han-gu Sohn , Hai-jeong Sohn , Sei-jin Kim , Woo-seop Jeong
IPC分类号： G06F12/00
CPC分类号： G11C7/1057 , G06F12/04 , G11C7/10 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： Circuits and methods for controlling data I/O operations in semiconductor memory devices to provide variable data I/O widths for read, write and active memory operations. Circuits and methods for selectively controlling a data width of a data I/O buffer “on the fly” to enable variable data I/O widths during memory access operations.
摘要翻译：用于控制半导体存储器件中数据I / O操作的电路和方法，为读，写和有效存储器操作提供可变数据I / O宽度。用于选择性地控制数据I / O缓冲器的数据宽度的电路和方法，以便在存储器访问操作期间实现可变数据I / O宽度。

7. 发明申请

US20090019237A1 MULTIPATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE HAVING CONTINUOUS ADDRESS MAP AND METHOD OF PROVIDING THE SAME 审中-公开
标题翻译：具有连续地址映射的多路可及半导体存储器件及其提供方法
公开(公告)号：US20090019237A1
公开(公告)日：2009-01-15
申请号：US12139622
申请日：2008-06-16
申请人： Jin-Hyoung Kwon , Han-Gu Sohn
发明人： Jin-Hyoung Kwon , Han-Gu Sohn
IPC分类号： G06F12/02
CPC分类号： G06F12/06 , G06F15/167
摘要： A semiconductor memory device for use in a multiprocessor system includes at least two shared memory areas and a row decoder. The at least two shared memory areas are accessible in common by multiple processors of the multiprocessor system through different ports, and assigned based on predetermined memory capacity to a portion of a memory cell array. The row decoder is configured to form a continuous address map for remaining memory portions of the at least two shared memory areas to be dedicated to one port. Each remaining memory portion does not include a corresponding data transfer portion within each shared memory area.
摘要翻译：一种用于多处理器系统的半导体存储器件包括至少两个共享存储区域和行解码器。所述至少两个共享存储器区域可由多处理器系统的多个处理器通过不同端口共同访问，并且基于预定的存储器容量被分配给存储器单元阵列的一部分。行解码器被配置为形成用于要专用于一个端口的至少两个共享存储器区域的剩余存储器部分的连续地址映射。每个剩余存储器部分不包括每个共享存储器区域内的对应的数据传送部分。

8. 发明申请

US20080291727A1 Semiconductor memory system having volatile memory and non-volatile memory that share bus, and method of controlling operation of non-volatile memory 有权
标题翻译：具有共享总线的易失性存储器和非易失性存储器的半导体存储器系统以及控制非易失性存储器的操作的方法
公开(公告)号：US20080291727A1
公开(公告)日：2008-11-27
申请号：US12078422
申请日：2008-03-31
申请人： Hui-kwon Seo , Han-gu Sohn , Sei-jin Kim
发明人： Hui-kwon Seo , Han-gu Sohn , Sei-jin Kim
IPC分类号： G11C16/04 , G11C7/00
CPC分类号： G06F13/4234 , G06F13/1694
摘要： Example embodiments relate to a semiconductor memory system which may include a volatile memory and a non-volatile memory that share a common bus, and a method for controlling the operation of the non-volatile memory. The semiconductor memory system may include a non-volatile memory and a memory controller. The non-volatile memory may include a buffer memory that temporarily stores data to be read from or to be written to a memory cell array, and an internal controller. The memory controller may transmits a mode signal to the non-volatile memory in response to a control signal, the control signal corresponds to either a read mode or a write mode to be applied to the non-volatile memory. In response to the mode signal, the internal controller may control the data to be read to be stored in the buffer memory, if the read mode is to be applied, and the internal controller may control the buffer memory to stand-by until a write command is received, if the write mode is to be applied.
摘要翻译：示例性实施例涉及可包括易失性存储器和共享公共总线的非易失性存储器的半导体存储器系统，以及用于控制非易失性存储器的操作的方法。半导体存储器系统可以包括非易失性存储器和存储器控制器。非易失性存储器可以包括临时存储要从或将要写入存储单元阵列的数据的缓冲存储器和内部控制器。存储器控制器可以响应于控制信号将模式信号发送到非易失性存储器，该控制信号对应于要施加到非易失性存储器的读取模式或写入模式。响应于模式信号，如果要应用读取模式，则内部控制器可以控制要读取的数据被存储在缓冲存储器中，并且内部控制器可以控制缓冲存储器待机直到写入如果要应用写入模式，则接收命令。

9. 发明申请

US20060146630A1 Non volatile semiconductor memory device having a multi-bit cell array 有权
标题翻译：具有多位单元阵列的非易失性半导体存储器件
公开(公告)号：US20060146630A1
公开(公告)日：2006-07-06
申请号：US11317429
申请日：2005-12-23
申请人： Han-Gu Sohn , Sei-Jin Kim
发明人： Han-Gu Sohn , Sei-Jin Kim
IPC分类号： G11C7/00 , G11C11/406
CPC分类号： G11C11/406 , G11C2211/4061
摘要： A semiconductor device is provided. The semiconductor device includes a storage part storing an address for weak cells in a nonvolatile state; and a dynamic semiconductor memory device including: a memory cell array having normal cells and the weak cells to be refreshed; and a refresh control part performing a refresh operation for the weak cells, wherein a refresh period for the weak cells is shorter than a refresh period for the normal cells when the address applied in a refresh operation mode coincides with the address stored in the storage part.
摘要翻译：提供一种半导体器件。半导体器件包括：存储非易失性状态的弱电池的地址的存储部; 以及动态半导体存储器件，包括：具有正常单元的存储单元阵列和要刷新的弱单元; 以及对所述弱小区执行刷新操作的刷新控制部分，其中当刷新操作模式中应用的地址与存储在存储部分中的地址一致时，所述弱小区的刷新周期短于正常小区的刷新周期。

10. 发明申请

US20050169061A1 Multi-port memory device for buffering between hosts and non-volatile memory devices 有权
标题翻译：用于在主机和非易失性存储器件之间进行缓冲的多端口存储器件
公开(公告)号：US20050169061A1
公开(公告)日：2005-08-04
申请号：US11046407
申请日：2005-01-28
申请人： Han-gu Sohn , Sei-jin Kim
发明人： Han-gu Sohn , Sei-jin Kim
IPC分类号： G06F12/00 , G06F12/02 , G11C7/00 , G11C7/10 , G11C8/10 , G11C8/16 , G11C11/4093
CPC分类号： G11C7/1075 , G11C8/10 , G11C8/16 , G11C2207/2245
摘要： A multi-port volatile memory device includes a first port configured for data transfer to/from an external host system and the device. A volatile main memory core is configured to store data received thereat and read requested stored data thereform. A volatile sub memory core is configured to store data received thereat and read requested stored data therefrom. A main interface circuit is coupled to the first port and configured to provide data to/from the volatile main memory core and the first port in a master mode and configured to provide data to/from the volatile sub memory core and the first port in a slave mode. A second port is configured for data transfer to/from an external non-volatile memory device and the device. A sub interface circuit is coupled to the second port and configured to provide data to/from the volatile sub memory core and the second port in the slave mode.
摘要翻译：多端口易失性存储器设备包括被配置为用于向/从外部主机系统传送数据的第一端口和该设备。易失性主存储器核心被配置为存储在其上接收的数据并且读取请求的存储数据。易失性子存储器内核被配置为存储从其接收的数据并从其读取请求的存储数据。主接口电路耦合到第一端口并且被配置为以主模式向易失性主存储器核心和第一端口提供数据，并且被配置为向/从易失性子存储器核心和第一端口提供数据从模式。第二端口被配置用于从外部非易失性存储器设备和设备传送数据。子接口电路耦合到第二端口并且被配置为在从模式中向/从易失性子存储器内核和第二端口提供数据。

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