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1. 发明授权

US09903901B2 Leakage current detection device and nonvolatile memory device having the same 有权
公开(公告)号：US09903901B2
公开(公告)日：2018-02-27
申请号：US14681137
申请日：2015-04-08
申请人： Byung-Gil Jeon , Doo-Gon Kim
发明人： Byung-Gil Jeon , Doo-Gon Kim
IPC分类号： G01R31/02 , G11C29/02 , G11C29/50 , G11C11/16 , G11C13/00
CPC分类号： G01R31/025 , G11C11/1673 , G11C13/00 , G11C29/023 , G11C29/025 , G11C29/026 , G11C29/50008 , G11C2029/5006
摘要： A leakage current detection device includes a test detection circuit, a reference detection circuit, a comparator, and a latch circuit. The test detection circuit is coupled between a test node and a test line, provides a voltage to the test node to charge the test line, floats the test node and the test line, and decreases a voltage of the test node based on leakage current of the test line. The reference detection circuit is coupled between a reference node and a reference line, provides the voltage to the reference node to charge the reference line, floats the reference node and the reference line, and decreases a voltage of the reference node based on self-discharge of the reference line. The comparator outputs a comparison signal by comparing voltages of the test node and the reference node. The latch circuit latches the comparison signal to output a test result signal.

2. 发明授权

US08315105B2 Method of erasing in non-volatile memory device 有权
标题翻译：在非易失性存储器件中擦除的方法
公开(公告)号：US08315105B2
公开(公告)日：2012-11-20
申请号：US13153285
申请日：2011-06-03
申请人： Doo-Gon Kim , Ki-Tae Park , Yeong-Taek Lee
发明人： Doo-Gon Kim , Ki-Tae Park , Yeong-Taek Lee
IPC分类号： G11C16/06
CPC分类号： G11C16/14
摘要： An erasing method of post-programming in a nonvolatile memory device. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are greater than or equal to a second voltage. The first voltage is different from the second voltage.
摘要翻译：一种在非易失性存储器件中进行后编程的擦除方法。该方法包括后编程虚拟存储器单元; 验证所述伪存储单元的阈值电压是否大于或等于第一电压; 后编程正常记忆单元; 以及验证所述正常存储单元的阈值电压是否大于或等于第二电压。第一电压与第二电压不同。

3. 发明授权

US07940578B2 Flash memory device having row decoders sharing single high voltage level shifter, system including the same, and associated methods 有权
标题翻译：具有共享单个高电压电平移位器的行解码器的闪存器件，包括其的系统以及相关联的方法
公开(公告)号：US07940578B2
公开(公告)日：2011-05-10
申请号：US12320003
申请日：2009-01-14
申请人： Myoung-gon Kang , Yeong-taek Lee , Ki-tae Park , Doo-gon Kim
发明人： Myoung-gon Kang , Yeong-taek Lee , Ki-tae Park , Doo-gon Kim
IPC分类号： G11C5/14
CPC分类号： G11C16/3418 , G11C7/02 , G11C8/10 , G11C16/0483 , G11C16/3427 , G11C17/16 , G11C29/52
摘要： A flash memory device includes first and second memory cell array blocks and a row decoder coupled to the first memory cell array block and the second memory cell array block. The row decoder includes a block decoder, a single high voltage level shifter that is coupled to both the first and second memory cell array blocks, the single high voltage level shifter configured to provide a block wordline signal of a high voltage to the first and second memory array blocks in response to a block selection signal received from the block decoder, a first pass transistor unit, and a second pass transistor unit.
摘要翻译：闪速存储器件包括第一和第二存储单元阵列块以及耦合到第一存储单元阵列块和第二存储单元阵列块的行解码器。行解码器包括块解码器，耦合到第一和第二存储单元阵列块的单个高电压电平移位器，该单个高电压电平移位器被配置为向第一和第二存储单元阵列块提供高电压的块字线信号存储器阵列块，响应于从块解码器接收的块选择信号，第一传输晶体管单元和第二传输晶体管单元。

4. 发明授权

US07773427B2 Non-volatile memory device and method of operating 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US07773427B2
公开(公告)日：2010-08-10
申请号：US12141737
申请日：2008-06-18
申请人： Ki-Tae Park , Doo-Gon Kim , Yeong-Taek Lee
发明人： Ki-Tae Park , Doo-Gon Kim , Yeong-Taek Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/3418
摘要： A non volatile memory device and method of operating including providing a verification voltage to a gate of a selected memory cell within multiple memory cells and providing a first pass voltage to a gate of a non-selected memory cell within the memory cells during a program verification operation; and providing a read voltage to the gate of the selected memory cell and providing a second pass voltage to the gate of the non-selected memory cell during a read operation. The second pass voltage is greater than the first pass voltage.
摘要翻译：一种非易失性存储器件和操作方法，包括向多个存储器单元内的所选存储单元的栅极提供验证电压，并且在程序验证期间向存储器单元内的未选择存储单元的栅极提供第一通过电压操作; 以及向所选择的存储单元的栅极提供读取电压，并且在读取操作期间向未选择的存储单元的栅极提供第二通过电压。第二通过电压大于第一通过电压。

5. 发明授权

US07649775B2 Flash memory device applying erase voltage 有权
标题翻译：闪存器件施加擦除电压
公开(公告)号：US07649775B2
公开(公告)日：2010-01-19
申请号：US11970634
申请日：2008-01-08
申请人： Doo-Gon Kim , Ki-Tae Park
发明人： Doo-Gon Kim , Ki-Tae Park
IPC分类号： G11C16/00
CPC分类号： G11C16/3418
摘要： A flash memory device includes; a plurality of layers, each one including memory cells arranged in a matrix of rows and columns, a layer decoder configured to select one of the plurality of layers to thereby define a selected layer and an unselected layer, a voltage generator configured to generate an erase voltage at a level higher than ground voltage, and an internal voltage, and a row select circuit configured to apply the erase voltage to the selected layer, and apply at least one of the erase voltage and the internal voltage to the unselected layer during an erase operation.
摘要翻译：闪存装置包括：多个层，每个层包括排列成行和列的矩阵的存储单元;层解码器，被配置为选择所述多个层中的一个，从而限定所选择的层和未选择层;电压发生器，被配置为产生擦除电压高于接地电压，内部电压以及行选择电路，配置为向所选层施加擦除电压，并且在擦除期间将擦除电压和内部电压中的至少一个施加到未选择层操作。

6. 发明授权

US07633785B2 Semiconductor memory device and method of generating chip enable signal thereof 有权
标题翻译：半导体存储器件及其制造芯片使能信号的方法
公开(公告)号：US07633785B2
公开(公告)日：2009-12-15
申请号：US11775245
申请日：2007-07-10
申请人： Doo-Gon Kim , Youn-Cheul Kim
发明人： Doo-Gon Kim , Youn-Cheul Kim
IPC分类号： G11C5/02
CPC分类号： H03K19/20 , G11C7/1045 , G11C7/20 , G11C7/22
摘要： Provided are a semiconductor memory device and a method of generating a chip enable signal thereof. The device includes a plurality of memory chips and an interface chip that are stacked. Each of the memory chips includes a control signal setting unit, which sets input signals applied to first and second input nodes as less significant 2-bit control signals of n-bit control signals, performs a logic AND operation on the less significant 2-bit control signals to generate AND operated signals, performs a logic XOR operation on each of the AND operated signals and each bit signal of more significant n−2-bit input signals applied to third to n-th input nodes to set the n−2-bit control signals, outputs the signal applied to the second input node through a first output node, inverts the signal applied to the first input node to output the inverted signal through a second output node, and outputs the more significant n−2-bit input signals through third through n-th output nodes, respectively. The first through n-th output nodes of one of two adjacent memory chips are respectively connected to the first through n-th input nodes of the other of the two adjacent memory chips.
摘要翻译：提供一种半导体存储器件及其产生芯片使能信号的方法。该装置包括堆叠的多个存储器芯片和接口芯片。每个存储器芯片包括控制信号设置单元，其将施加到第一和第二输入节点的输入信号设置为较低有效的n位控制信号的2位控制信号，对较不重要的2位执行逻辑与运算控制信号以产生与操作信号，对每个AND运算信号和施加到第三至第n输入节点的更有效的n-2位输入信号的每个比特信号执行逻辑异或运算，以设置n-2- 通过第一输出节点输出施加到第二输入节点的信号，将施加到第一输入节点的信号反相，通过第二输出节点输出反相信号，并输出更重要的n-2位输入分别通过第三到第n个输出节点发出信号。两个相邻存储器芯片中的一个的第一至第n输出节点分别连接到两个相邻存储器芯片中另一个的第一至第n输入节点。

7. 发明授权

US07609571B2 Semiconductor memory device having a control unit receiving a sensing block selection address signal and related method 有权
标题翻译：具有接收感测块选择地址信号的控制单元和相关方法的半导体存储器件
公开(公告)号：US07609571B2
公开(公告)日：2009-10-27
申请号：US11830905
申请日：2007-07-31
申请人： Doo-Gon Kim
发明人： Doo-Gon Kim
IPC分类号： G11C7/02
CPC分类号： G11C7/065 , G11C7/08
摘要： Embodiments of the invention include a semiconductor memory device and a method for operating the semiconductor memory device. The invention includes a semiconductor memory device comprising a memory cell array block including a plurality of first memory cells connected to a plurality of first bit lines and a plurality of second memory cells connected to a plurality of second bit lines. The semiconductor memory device further includes a first sensing block disposed on a first side of the memory cell array block, a second sensing block disposed on a second side of the memory cell array block, and a control unit receiving a sensing block selection address signal, wherein, when the sensing block selection address signal specifies the first sensing block, the control unit enables the first sensing block and disables the second sensing block.
摘要翻译：本发明的实施例包括半导体存储器件和用于操作半导体存储器件的方法。本发明包括一种半导体存储器件，其包括存储单元阵列块，该存储单元阵列块包括连接到多个第一位线的多个第一存储器单元和连接到多个第二位线的多个第二存储器单元。半导体存储器件还包括设置在存储单元阵列块的第一侧上的第一感测块，设置在存储单元阵列块的第二侧上的第二感测块，以及接收感测块选择地址信号的控制单元，其中，当所述感测块选择地址信号指定所述第一感测块时，所述控制单元使能所述第一感测块并禁用所述第二感测块。

8. 发明申请

US20090180339A1 SEMICONDUCTOR MEMORY DEVICE WITH THREE-DIMENSIONAL ARRAY AND REPAIR METHOD THEREOF 有权
标题翻译：具有三维阵列的半导体存储器件及其修复方法
公开(公告)号：US20090180339A1
公开(公告)日：2009-07-16
申请号：US12336827
申请日：2008-12-17
申请人： Doo-Gon KIM , Ki-Tae PARK
发明人： Doo-Gon KIM , Ki-Tae PARK
IPC分类号： G11C29/00 , G11C17/16
CPC分类号： G11C29/808
摘要： A nonvolatile memory device includes a three-dimensional (3D) cell array, a column selection circuit and a fuse block. The 3D cell array includes multiple cell arrays located in corresponding stacked substrate layers, the cell arrays sharing a bit line. The column selection circuit selects a memory unit included in the 3D cell array. The fuse block controls the column selection circuit to repair defective columns with one of multiple redundant bit lines located in the 3D cell array.
摘要翻译：非易失性存储器件包括三维（3D）单元阵列，列选择电路和熔丝块。 3D单元阵列包括位于对应的堆叠衬底层中的多个单元阵列，单元阵列共享位线。列选择电路选择包括在3D单元阵列中的存储单元。熔丝块控制列选择电路，以修复位于3D单元阵列中的多个冗余位线之一的有缺陷的列。

9. 发明申请

US20080101114A1 FLOATING BODY SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：浮动体半导体存储器件及其操作方法
公开(公告)号：US20080101114A1
公开(公告)日：2008-05-01
申请号：US11781331
申请日：2007-07-23
申请人： Doo-Gon KIM , Duk-Ha PARK , Myoung-Gon KANG
发明人： Doo-Gon KIM , Duk-Ha PARK , Myoung-Gon KANG
IPC分类号： G11C11/34
CPC分类号： G11C11/4091 , G11C11/4094 , G11C2211/4016
摘要： A semiconductor memory device includes a memory cell array having first and second blocks, respectively including first and second memory cells with floating bodies. The first memory cell is connected between a first bit line and a source line, and the second memory cell is connected between a second bit line and the source line. A sense amplifier equalizes the sense bit line and the inverted sense bit line to be an equalization voltage during an equalization operation, pre-charges the sense bit line and the inverted sense bit line to first and second pre-charge voltages during a pre-charge operation, and amplifies a voltage difference between the sense bit line and the inverted sense bit line during read and write operations. The first pre-charge voltage is higher than the equalization voltage and the second pre-charge voltage is higher than the equalization voltage and lower than the first pre-charge voltage.
摘要翻译：半导体存储器件包括具有第一和第二块的存储单元阵列，分别包括具有浮体的第一和第二存储单元。第一存储单元连接在第一位线和源极线之间，第二存储单元连接在第二位线和源极线之间。在均衡操作期间，感测放大器将感测位线和反相感测位线均衡为均衡电压，在预充电期间将感测位线和反相检测位线预充电到第一和第二预充电电压并且在读取和写入操作期间放大感测位线和反相读取位线之间的电压差。第一预充电电压高于均衡电压，第二预充电电压高于均衡电压并低于第一预充电电压。

10. 发明授权

US08208335B2 Semiconductor memory device and system including the same 有权
标题翻译：半导体存储器件及其系统
公开(公告)号：US08208335B2
公开(公告)日：2012-06-26
申请号：US12821515
申请日：2010-06-23
申请人： Dong-Hyuk Lee , Jung-Bae Lee , Doo-Gon Kim , Cheol Kim
发明人： Dong-Hyuk Lee , Jung-Bae Lee , Doo-Gon Kim , Cheol Kim
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/401 , G11C11/406 , G11C11/40618 , G11C11/40622 , G11C29/24 , G11C29/50016 , G11C2211/4061
摘要： A semiconductor memory device includes a cell array unit having a plurality of banks each having a plurality of blocks, and a refresh controller configured to set at least one of the blocks as a test block, perform a refresh operation on the blocks except for the test block in a self-refresh operation period, determine a refresh period of the test block, and then set another one of the blocks as the test block.
摘要翻译：半导体存储器件包括具有多个块的单元阵列单元，每个单元具有多个块，以及刷新控制器，被配置为将至少一个块设置为测试块，对除了测试之外的块执行刷新操作在自刷新操作期间块，确定测试块的刷新周期，然后将另一个块设置为测试块。

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