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51. 发明申请

US20080246041A1 METHOD OF FABRICATING SOI nMOSFET AND THE STRUCTURE THEREOF 审中-公开
标题翻译：制造SOI nMOSFET的方法及其结构
公开(公告)号：US20080246041A1
公开(公告)日：2008-10-09
申请号：US11696846
申请日：2007-04-05
申请人： Yaocheng Liu , Huilong Zhu
发明人： Yaocheng Liu , Huilong Zhu
IPC分类号： H01L29/12 , H01L21/336
CPC分类号： H01L21/26506 , H01L29/165 , H01L29/66628 , H01L29/66772 , H01L29/78618 , H01L29/78681
摘要： A method of fabricating a silicon-on-insulator (SOI) N-channel metal oxide semiconductor field effect transistor (nMOSFET), where the transistor has a structure incorporating a gate disposed above a body of the SOI substrate. The body comprises of a first surface and a second surface. The second surface interfaces between the body and the insulator of the SOI. Between the first surface and second surface is defined a channel region separating a source region and a drain region. Each of the source region and drain region includes a third surface under which is embedded crystalline silicon-carbon (Si:C), which extends from the second surface to the third surface.
摘要翻译：一种制造绝缘体上硅（SOI）N沟道金属氧化物半导体场效应晶体管（nMOSFET）的方法，其中晶体管具有结合设置在SOI衬底本体上方的栅极的结构。主体包括第一表面和第二表面。第二表面在SOI的绝缘体和绝缘体之间接合。在第一表面和第二表面之间限定了分离源极区域和漏极区域的沟道区域。源极区域和漏极区域中的每一个包括第三表面，在第三表面上嵌入从第二表面延伸到第三表面的结晶硅 - 碳（Si：C）。

52. 发明申请

US20080237709A1 AFTER GATE FABRICATION OF FIELD EFFECT TRANSISTOR HAVING TENSILE AND COMPRESSIVE REGIONS 失效
标题翻译：在具有拉伸和压缩区域的场效应晶体管的栅格制造之后
公开(公告)号：US20080237709A1
公开(公告)日：2008-10-02
申请号：US11693786
申请日：2007-03-30
申请人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
发明人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
IPC分类号： H01L29/78 , H01L21/84
CPC分类号： H01L29/66628 , H01L21/84 , H01L29/1083 , H01L29/66772 , H01L29/7842 , H01L29/7843 , H01L29/7848 , H01L29/7849 , H01L29/78654
摘要： A field effect transistor (“FET”) is formed to include a stress in a channel region of an active semiconductor region of an SOI substrate. A gate is formed to overlie the active semiconductor region, after which a sacrificial stressed layer is formed which overlies the gate and the active semiconductor region. Then, the SOI substrate is heated to cause a flowable dielectric material in a buried dielectric layer of the SOI substrate to soften and reflow. As a result of the reflowing, the sacrificial stressed layer induces stress in a channel region of the active semiconductor region underlying the gate. A source region and a drain region are formed in the active semiconductor region, desirably after removing the sacrificial stressed layer.
摘要翻译：形成场效应晶体管（“FET”）以在SOI衬底的有源半导体区域的沟道区域中包含应力。形成栅极覆盖有源半导体区域，之后形成覆盖在栅极和有源半导体区域上的牺牲应力层。然后，加热SOI衬底，使SOI衬底的埋入介质层中的可流动介电材料软化和回流。作为回流的结果，牺牲应力层在栅极下方的有源半导体区域的沟道区域中引起应力。源极区域和漏极区域形成在有源半导体区域中，理想地在除去牺牲应力层之后。

53. 发明申请

US20080169508A1 STRESSED SOI FET HAVING DOPED GLASS BOX LAYER 有权
标题翻译：具有DOPED GLASS BOX LAYER的应力SOI FET
公开(公告)号：US20080169508A1
公开(公告)日：2008-07-17
申请号：US11622056
申请日：2007-01-11
申请人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
发明人： Dureseti Chidambarrao , William K. Henson , Yaocheng Liu
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/78696 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/7849
摘要： A method is provided for fabricating a semiconductor-on-insulator (“SOI”) substrate including (i) an SOI layer of monocrystalline silicon separated from (ii) a bulk semiconductor layer by (ii) a buried oxide (“BOX”) layer, the BOX layer including a layer of doped silicate glass. In such method, a sacrificial stressed layer is deposited to overlie the SOI layer and trenches are etched through the sacrificial stressed layer and into the SOI layer. The SOI substrate is heated with the sacrificial stressed layer sufficiently to cause the glass layer to soften, thereby causing the sacrificial stressed layer to apply stress to the SOI layer to form a stressed SOI layer. A dielectric material can then be deposited in the trenches to form isolation regions contacting peripheral edges of the stressed SOI layer, the isolation regions extending from a major surface of the stressed SOI layer towards the BOX layer. The sacrificial stressed layer can then be removed to expose the stressed SOI layer.
摘要翻译：提供了一种用于制造绝缘体上半导体（“SOI”）衬底的方法，其包括（i）通过（ii）掩埋氧化物（“BOX”）层从（ii）体半导体层分离的单晶硅的SOI层 BOX层包括一层掺杂的硅酸盐玻璃。在这种方法中，沉积牺牲应力层以覆盖SOI层，并且通过牺牲应力层蚀刻沟槽并进入SOI层。用牺牲应力层对SOI衬底进行充分加热，使玻璃层软化，从而使牺牲应力层向SOI层施加应力以形成受应力的SOI层。然后可以将电介质材料沉积在沟槽中以形成接触应力SOI层的外围边缘的隔离区域，隔离区域从受应力的SOI层的主表面延伸到BOX层。然后可以去除牺牲应力层以暴露受应力的SOI层。

54. 发明申请

US20080164491A1 STRUCTURE AND METHOD FOR MOBILITY ENHANCED MOSFETS WITH UNALLOYED SILICIDE 有权
标题翻译：具有硅酸盐的移动增强MOSFET的结构和方法
公开(公告)号：US20080164491A1
公开(公告)日：2008-07-10
申请号：US11619809
申请日：2007-01-04
申请人： Yaocheng Liu , Dureseti Chidambarrao , Oleg Gluschenkov , Judson R. Holt , Renee T. Mo , Kern Rim
发明人： Yaocheng Liu , Dureseti Chidambarrao , Oleg Gluschenkov , Judson R. Holt , Renee T. Mo , Kern Rim
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823864 , H01L21/76886 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L27/3279 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
摘要翻译：虽然嵌入式硅锗合金和硅碳合金提供了许多有用的应用，特别是为了通过应力工程增强MOSFET的迁移率，在这些表面上形成合金化硅化物降低了器件性能。本发明提供了在放置在半导体衬底上的这种硅合金表面上提供非合金硅化物的结构和方法。这使得能够在具有嵌入式SiGe的迁移率增强的PFET和在同一半导体衬底上具有嵌入的Si：C的迁移率增强的NFET形成低电阻触点。此外，本发明提供了在栅极电介质的电平之上的厚外延硅合金，特别是厚的外延Si：C合金的方法，以增加晶体管器件上的沟道上的应力。

55. 发明申请

US20080128806A1 LOW DEFECT SI:C LAYER WITH RETROGRADE CARBON PROFILE 有权
标题翻译：低缺陷SI：C层，带有RETROGRADE碳配置文件
公开(公告)号：US20080128806A1
公开(公告)日：2008-06-05
申请号：US11565793
申请日：2006-12-01
申请人： Yaocheng Liu , Subramanian S. Iyer , Jinghong Li
发明人： Yaocheng Liu , Subramanian S. Iyer , Jinghong Li
IPC分类号： H01L29/06 , H01L21/336 , H01L21/225 , H01L29/08
CPC分类号： H01L29/1054 , H01L21/2022 , H01L21/26506 , H01L29/32 , H01L29/7848 , H01L29/78618 , H01L29/78654 , H01L29/78696
摘要： Formation of carbon-substituted single crystal silicon layer is prone to generation of large number of defects especially at high carbon concentration. The present invention provides structures and methods for providing low defect carbon-substituted single crystal silicon layer even for high concentration of carbon in the silicon. According to the present invention, the active retrograde profile in the carbon implantation reduces the defect density in the carbon-substituted single crystal silicon layer obtained after a solid phase epitaxy. This enables the formation of semiconductor structures with compressive stress and low defect density. When applied to semiconductor transistors, the present invention enables N-type field effect transistors with enhanced electron mobility through the tensile stress that is present into the channel.
摘要翻译：碳取代的单晶硅层的形成容易产生大量的缺陷，特别是在高碳浓度下。本发明提供即使对于硅中的高浓度碳来提供低缺陷碳取代的单晶硅层的结构和方法。根据本发明，碳注入中的主动逆行曲线减少了在固相外延后获得的碳取代单晶硅层中的缺陷密度。这使得能够形成具有压缩应力和低缺陷密度的半导体结构。当应用于半导体晶体管时，本发明能够通过存在于沟道中的拉伸应力使具有增强的电子迁移率的N型场效应晶体管成为可能。

56. 发明申请

US20080050863A1 SEMICONDUCTOR STRUCTURE INCLUDING MULTIPLE STRESSED LAYERS 审中-公开
标题翻译：半导体结构，包括多个应力层
公开(公告)号：US20080050863A1
公开(公告)日：2008-02-28
申请号：US11467721
申请日：2006-08-28
申请人： William K. Henson , Dureseti Chidambarrao , Yaocheng Liu
发明人： William K. Henson , Dureseti Chidambarrao , Yaocheng Liu
IPC分类号： H01L21/84
CPC分类号： H01L29/045 , H01L21/28097 , H01L29/4975 , H01L29/66545 , H01L29/66772 , H01L29/7843 , H01L29/78654
摘要： A semiconductor structure and methods for fabricating the semiconductor structure include a gate electrode located over a channel region within a semiconductor substrate and a spacer layer adjacent the gate electrode. The spacer layer extends vertically above the gate electrode. The semiconductor structure also includes a first stressed layer having a first stress located over the gate electrode and a second stressed layer having a second stress different than the first stress located over the first stressed layer. At least a portion of the first stressed layer is laterally contained by the spacer layer. At least a portion of the second stressed layer is not laterally contained by the spacer layer.
摘要翻译：半导体结构和制造半导体结构的方法包括位于半导体衬底内的沟道区上方的栅电极和与栅电极相邻的间隔层。间隔层在栅电极上方垂直延伸。半导体结构还包括具有位于栅极上的第一应力的第一应力层和具有不同于位于第一应力层上方的第一应力的第二应力的第二应力层。第一应力层的至少一部分由间隔层横向容纳。第二应力层的至少一部分不被间隔层横向包含。

57. 发明申请

US20070235759A1 CMOS process with Si gates for nFETs and SiGe gates for pFETs 审中-公开
标题翻译：用于nFET的Si栅极的CMOS工艺和用于pFET的SiGe栅极
公开(公告)号：US20070235759A1
公开(公告)日：2007-10-11
申请号：US11401672
申请日：2006-04-11
申请人： William Henson , Yaocheng Liu , Alexander Reznicek , Kern Rim , Devendra Sadana
发明人： William Henson , Yaocheng Liu , Alexander Reznicek , Kern Rim , Devendra Sadana
IPC分类号： H01L31/00
CPC分类号： H01L21/2807 , H01L21/823842
摘要： An integration scheme for providing Si gates for nFET devices and SiGe gates for pFET devices on the same semiconductor substrate is provided. The integration scheme includes first providing a material stack comprising, from bottom to top, a gate dielectric, a Si film, and a hard mask on a surface of a semiconductor substrate that includes at least one nFET device region and at least one pFET device region. Next, the hard mask is selectively removed from the material stack in the at least one pFET device region thereby exposing the Si film. The exposed Si film is then converted into a SiGe film and thereafter at least one nFET device is formed in the least one nFET device region and at least one pFET device is formed in the at least one pFET device region. In accordance with the present invention, the least one nFET device includes a Si gate and the at least one pFET includes a SiGe gate.
摘要翻译：提供了用于在同一半导体衬底上为pFET器件提供nFET器件的Si栅极和SiGe栅极的集成方案。该集成方案包括首先提供材料堆叠，其从底部到顶部包括在半导体衬底的表面上的栅极电介质，Si膜和硬掩模，其包括至少一个nFET器件区域和至少一个pFET器件区域。接下来，将硬掩模从至少一个pFET器件区域中的材料堆叠中选择性地去除，从而暴露Si膜。暴露的Si膜然后被转换成SiGe膜，此后在至少一个nFET器件区域中形成至少一个nFET器件，并且在至少一个pFET器件区域中形成至少一个pFET器件。根据本发明，至少一个nFET器件包括Si栅极，并且至少一个pFET包括SiGe栅极。

58. 发明申请

US20070087507A1 Crystalline-type device and approach therefor 有权
标题翻译：结晶型装置及其方法
公开(公告)号：US20070087507A1
公开(公告)日：2007-04-19
申请号：US10590223
申请日：2004-03-17
申请人： Yaocheng Liu , Michael Deal , James Plummer
发明人： Yaocheng Liu , Michael Deal , James Plummer
IPC分类号： H01L21/336 , H01L29/94 , H01L29/76 , H01L31/00
CPC分类号： H01L29/78684 , H01L29/66742 , H01L29/785
摘要： Single-crystalline growth is realized using a liquid-phase crystallization approach involving the inhibition of defects typically associated with liquid-phase crystalline growth of lattice mismatched materials. According to one example embodiment, a semiconductor device structure includes a substantially single-crystal region. A liquid-phase material is crystallized to form the single-crystal region using an approach involving defect inhibition for the promotion of single-crystalline growth. In some instances, this defect inhibition involves the reduction and/or elimination of defects using a relatively small physical opening via which a crystalline growth front propagates. In other instances, this defect inhibition involves causing a change in crystallization front direction relative to a crystallization seed location. The relatively small physical opening and/or the change in crystalline front direction may be implemented, for example, using a material that is relatively unreactive with the liquid-phase material to contain the crystalline growth.
摘要翻译：使用液相结晶方法实现单晶生长，其涉及通常与晶格失配材料的液相晶体生长相关的缺陷的抑制。根据一个示例性实施例，半导体器件结构包括基本单晶区域。使用涉及促进单晶生长的缺陷抑制的方法将液相材料结晶以形成单晶区域。在一些情况下，该缺陷抑制包括使用晶体生长前沿传播的相对小的物理开口来减少和/或消除缺陷。在其他情况下，该缺陷抑制涉及相对于结晶种子位置导致结晶前沿方向的变化。可以例如使用与液相材料相对不反应以含有结晶生长的材料来实现相对小的物理开口和/或晶体前沿的变化。

59. 发明授权

US06991868B2 Fuel cell assembly 失效
标题翻译：燃料电池组件
公开(公告)号：US06991868B2
公开(公告)日：2006-01-31
申请号：US10275591
申请日：2001-05-08
申请人： Sang-Joon John Lee , Jun Sasahara , Nariaki Kuriyama , Tadahiro Kubota , Toshifumi Suzuki , Friedrich B. Prinz , Suk Won Cha , Amy Chang-Chien , Yaocheng Liu , Ryan O'Hayre
发明人： Sang-Joon John Lee , Jun Sasahara , Nariaki Kuriyama , Tadahiro Kubota , Toshifumi Suzuki , Friedrich B. Prinz , Suk Won Cha , Amy Chang-Chien , Yaocheng Liu , Ryan O'Hayre
IPC分类号： H01M2/14 , H01M2/08 , H01M2/00 , H01M8/10
CPC分类号： H01M8/242 , H01M8/0204 , H01M8/0271 , H01M8/04007 , H01M8/04067 , H01M8/04225 , H01M8/04268 , H01M8/2483 , H01M2008/1095 , Y02P70/56
摘要： In a fuel cell assembly comprising a plurality of cell each including an electrolyte layer (2), a pair of diffusion electrode layers (3, 4) interposing the electrolyte layer between them, and a pair of flow distribution plates (5) for defining passages (11) for fuel and oxidant fluids that contact the diffusion electrode layers, the fuel cells are arranged on a common plane. Therefore, the vertical dimension of the fuel cell assembly can be minimized, and a fuel cell assembly of favorable electric properties can be achieved. Each flow distribution plate is typically formed with communication passages for communicating fluid passages defined on each side of the electrolyte layer at a prescribed pattern. The communication passages and through holes communicate the fluid passages in such a manner that adjacent fuels cells have opposite polarities.
摘要翻译：在包括多个电池的燃料电池组件中，每个电池单元包括电解质层（2），在电极层之间插入电解质层的一对扩散电极层（3,4）和用于限定通道的一对分流板（5）（11），用于与所述扩散电极层接触的燃料和氧化剂流体，所述燃料电池被布置在共同的平面上。因此，能够使燃料电池组件的垂直尺寸最小化，能够实现良好的电气特性的燃料电池组件。每个流量分配板通常形成有连通通道，用于以规定的模式连通限定在电解质层的每一侧上的流体通道。连通通道和通孔以相邻燃料电池具有相反极性的方式连通流体通道。

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