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51. 发明授权

US08367493B1 Void free interlayer dielectric 有权
标题翻译：无空隙层间电介质
公开(公告)号：US08367493B1
公开(公告)日：2013-02-05
申请号：US11109719
申请日：2005-04-20
申请人： Minh Van Ngo , Hirokazu Tokuno , Angela T. Hui , Wenmei Li , Hsiao-Han Thio
发明人： Minh Van Ngo , Hirokazu Tokuno , Angela T. Hui , Wenmei Li , Hsiao-Han Thio
IPC分类号： H01L21/8238
CPC分类号： H01L23/291 , H01L21/823425 , H01L21/823475 , H01L27/11521 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.
摘要翻译：一种制造非易失性存储器件的方法包括形成多个存储单元。该方法还包括在存储器单元上沉积第一介电层，其中第一介电层是具有基本均匀厚度的共形层。该方法还包括在第一介电层上沉积第二电介质层。第一和第二电介质层一起形成没有空隙的层间电介质。

52. 发明授权

US08283718B2 Integrated circuit system with metal and semi-conducting gate 有权
标题翻译：具有金属和半导体栅极的集成电路系统
公开(公告)号：US08283718B2
公开(公告)日：2012-10-09
申请号：US11611856
申请日：2006-12-16
申请人： Angela T. Hui , Mark S. Chang , Kuo-Tung Chang , Scott A. Bell
发明人： Angela T. Hui , Mark S. Chang , Kuo-Tung Chang , Scott A. Bell
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.
摘要翻译：提供了一种用于形成集成电路系统的方法，包括在衬底上形成半导电层，形成间隔层叠层，其间隔填充物与半导体层相邻，间隙填料上形成层间电介质，形成过渡层该层在半导体层上具有凹陷并且与间隔物堆叠相邻，并且在凹部中形成金属层。

53. 发明申请

US20120032308A1 GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPROACH TO TARGET CD FOR SELECTED TRANSISTORS 有权
标题翻译：使用蚀刻或干蚀刻方法对选定的晶体管的目标光盘进行栅格扫描过程
公开(公告)号：US20120032308A1
公开(公告)日：2012-02-09
申请号：US13278343
申请日：2011-10-21
申请人： Bradley M. Davis , Jihwan Choi , Angela T. Hui
发明人： Bradley M. Davis , Jihwan Choi , Angela T. Hui
IPC分类号： H01L21/306 , H01L29/06
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/28132 , H01L21/823456
摘要： Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.
摘要翻译：公开了用于在半导体器件中靶向所选晶体管的CD的方法和装置。通过在硬掩模层中形成具有不同量的与其相关联的间隔物材料的硬掩模线来完成不同的CD。对应于所选择的晶体管的硬掩模线被被涂覆在硬掩模层上的抗蚀剂覆盖或未覆盖。然后，从硬掩模线选择性地去除间隔物材料以改变硬掩模线和相关联的侧壁间隔物的宽度。然后通过硬掩模线中的空间蚀刻栅极层以形成具有不同宽度的栅极线和目标CD。

54. 发明申请

US20110195578A1 PLANAR CELL ON CUT USING IN-SITU POLYMER DEPOSITION AND ETCH 有权
标题翻译：使用现场聚合物沉积和蚀刻的切片的平面细胞
公开(公告)号：US20110195578A1
公开(公告)日：2011-08-11
申请号：US12703586
申请日：2010-02-10
申请人： Angela T. Hui , Gang Xue
发明人： Angela T. Hui , Gang Xue
IPC分类号： H01L21/3065
CPC分类号： H01L27/11568 , H01L27/11565
摘要： A method and manufacture for charge storage layer separation is provided. A layer, such as a polymer layer, is deposited on top of an ONO layer so that the polymer layer is planarized, or approximately planarized. The ONO includes at least a first region and a second region, where the first region is higher than the second region. For example, the first region may be the portion of the ONO that is over the source/drain region, and the second region may be the portion of the ONO that is over the shallow trench. Etching is performed on the polymer layer to expose the first region of the ONO layer, leaving the second region of the ONO unexposed. The etching continues to occur to etch the exposed ONO at the first region so that the ONO layer is etched away in the first region and the second region remains unexposed.
摘要翻译：提供了一种电荷存储层分离的方法和制造方法。诸如聚合物层的层沉积在ONO层的顶部上，使得聚合物层被平坦化或近似平坦化。 ONO包括至少第一区域和第二区域，其中第一区域高于第二区域。例如，第一区域可以是在源极/漏极区域上的ONO的部分，并且第二区域可以是在浅沟槽上的ONO的部分。在聚合物层上进行蚀刻以暴露ONO层的第一区域，留下ONO的第二区域未曝光。蚀刻继续发生以蚀刻在第一区域处的暴露的ONO，使得ONO层在第一区域被蚀刻掉，并且第二区域保持未曝光。

55. 发明申请

US20080150042A1 INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM 有权
标题翻译：具有存储器系统的集成电路系统
公开(公告)号：US20080150042A1
公开(公告)日：2008-06-26
申请号：US11958254
申请日：2007-12-17
申请人： Simon Siu-Sing Chan , Hidehiko Shiraiwa , Kuo-Tung Chang , Angela T. Hui
发明人： Simon Siu-Sing Chan , Hidehiko Shiraiwa , Kuo-Tung Chang , Angela T. Hui
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11521
摘要： A method for forming an integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a barrier metal layer over the spacer, and forming a metal plug over the outer doped region and the barrier metal layer.
摘要翻译：提供了一种用于形成集成电路系统的方法，包括形成具有衬底的间隔物的存储部分，在衬底中形成存储部分的外部掺杂区域，在间隔物上形成阻挡金属层，并形成金属插塞外部掺杂区域和阻挡金属层。

56. 发明授权

US07115440B1 SO2 treatment of oxidized CuO for copper sulfide formation of memory element growth 有权
标题翻译： SO2处理氧化CuO对硫化铜形成记忆元素生长
公开(公告)号：US07115440B1
公开(公告)日：2006-10-03
申请号：US10957247
申请日：2004-10-01
申请人： Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , James J. Xie , Angela T. Hui
发明人： Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , James J. Xie , Angela T. Hui
IPC分类号： H01L21/00
CPC分类号： H01L51/0575 , B82Y10/00 , G11C13/0014 , G11C13/0016 , G11C2213/77 , H01L27/285 , H01L51/105
摘要： Disclosed are methods of making memory cells and semiconductor devices containing the memory cells. The methods involve oxidizing a portion of a copper containing electrode to form a copper oxide layer; contacting the copper oxide layer with at least one of a sulfur containing gas or plasma to form a CuS layer; forming an organic semiconductor over the CuS layer; and forming an electrode over the organic semiconductor. Such devices containing the memory cells are characterized by light weight and robust reliability.
摘要翻译：公开了制造存储单元和包含存储单元的半导体器件的方法。所述方法包括氧化一部分含铜电极以形成氧化铜层; 使所述氧化铜层与含硫气体或等离子体中的至少一种接触以形成CuS层; 在CuS层上形成有机半导体; 并在有机半导体上形成电极。包含存储器单元的这种器件的特征在于重量轻和鲁棒的可靠性。

57. 发明授权

US06593632B1 Interconnect methodology employing a low dielectric constant etch stop layer 有权
标题翻译：采用低介电常数蚀刻停止层的互连方法
公开(公告)号：US06593632B1
公开(公告)日：2003-07-15
申请号：US09375500
申请日：1999-08-17
申请人： Steven C. Avanzino , Minh Van Ngo , Angela T. Hui , Chun Jiang , Hamid Partovi
发明人： Steven C. Avanzino , Minh Van Ngo , Angela T. Hui , Chun Jiang , Hamid Partovi
IPC分类号： H01L2976
CPC分类号： H01L21/76895 , H01L21/3148 , H01L21/76834 , H01L23/535 , H01L2924/0002 , H01L2924/00
摘要： The capacitance between the gate of a transistor and local interconnect is reduced employing SiC as an etch stop layer. Embodiments include depositing a SiC etch stop layer having a thickness of about 500-1000 Å and a dielectric constant of less than about 3.2, thereby providing a composite dielectric constant between the gate and local interconnect of between about 3.7 to about 4.7. The SiC etch stop layer can be deposited by PECVD or HDP techniques.
摘要翻译：使用SiC作为蚀刻停止层，减小晶体管的栅极和局部互连之间的电容。实施例包括沉积具有约500-1000的厚度和小于约3.2的介电常数的SiC蚀刻停止层，从而在栅极和局部互连之间提供约3.7至约4.7的复合介电常数。 SiC蚀刻停止层可以通过PECVD或HDP技术沉积。

58. 发明授权

US06501555B1 Optical technique to detect etch process termination 有权
标题翻译：检测蚀刻工艺终止的光学技术
公开(公告)号：US06501555B1
公开(公告)日：2002-12-31
申请号：US09773954
申请日：2001-02-01
申请人： Kouros Ghandehari , Bhanwar Singh , Angela T. Hui
发明人： Kouros Ghandehari , Bhanwar Singh , Angela T. Hui
IPC分类号： G01B1128
CPC分类号： H01L22/26 , H01L22/12
摘要： The disclosure describes an exemplary method of detecting a process end point during etching in the fabrication of an integrated circuit. This method can include receiving a reference signal indicative of an intensity of a light source, collecting a reflection signal reflected off a surface of an integrated circuit wafer, and comparing the reference signal and the reflection signal to locate absorption bands, the absorption band being indicative of a process end point.
摘要翻译：本公开描述了在集成电路的制造中在蚀刻期间检测处理终点的示例性方法。该方法可以包括接收指示光源强度的参考信号，收集从集成电路晶片的表面反射的反射信号，以及比较参考信号和反射信号以定位吸收带，吸收带指示的过程终点。

59. 发明授权

US06479411B1 Method for forming high quality multiple thickness oxide using high temperature descum 失效
标题翻译：使用高温除垢法形成高品质多层氧化物的方法
公开(公告)号：US06479411B1
公开(公告)日：2002-11-12
申请号：US09532347
申请日：2000-03-21
申请人： Angela T. Hui , Jusuke Ogura
发明人： Angela T. Hui , Jusuke Ogura
IPC分类号： H01L21311
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/31111 , H01L21/31116 , H01L21/31138 , H01L21/31662 , Y10S438/906 , Y10S438/942 , Y10S438/948
摘要： A method for forming high quality multiple thickness oxide layers having different thicknesses by eliminating descum induced defects. The method includes forming an oxide layer, masking the oxide layer with a photoresist layer, and developing the photoresist layer to expose at least one region of the oxide layer. The substrate is then heated and descummed to remove any residue resulting from developing the photoresist. Alternatively, the photoresist layer may be cured prior to heating and descumming the substrate. The oxide layer is then etched, and the remaining photoresist is stripped before another layer of oxide is grown on the substrate.
摘要翻译：一种用于通过消除除去所引起的缺陷来形成具有不同厚度的高质量多层氧化物层的方法。该方法包括形成氧化物层，用光致抗蚀剂层掩蔽氧化物层，以及显影光致抗蚀剂层以暴露氧化物层的至少一个区域。然后将基材加热除去以除去由显影光致抗蚀剂产生的残留物。或者，光致抗蚀剂层可以在加热和除去基板之前固化。然后蚀刻氧化物层，并且在衬底上生长另一层氧化物之前剥离剩余的光致抗蚀剂。

60. 发明授权

US06461973B1 Method for forming high quality multiple thickness oxide layers by reducing descum induced defects 失效
公开(公告)号：US06461973B1
公开(公告)日：2002-10-08
申请号：US09535256
申请日：2000-03-23
申请人： Angela T. Hui , Jusuke Ogura
发明人： Angela T. Hui , Jusuke Ogura
IPC分类号： H01L21302
CPC分类号： H01L21/0206 , H01L21/28273 , H01L21/31116 , H01L21/31138 , H01L21/31662 , H01L21/823462
摘要： A method for forming high quality oxide layers having different thicknesses by eliminating descum induced defects is disclosed. A semiconductor substrate is subjected to reactive ion etching. The semiconductor substrate includes a wafer, an oxide layer on the wafer, a developed photoresist mask on the oxide layer. The oxide layer is then etched, and the remaining photoresist is stripped before another layer of oxide is grown on the substrate.

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