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51. 发明授权

US06191028B1 Method of patterning dielectric 失效
标题翻译：电介质图案方法
公开(公告)号：US06191028B1
公开(公告)日：2001-02-20
申请号：US09059751
申请日：1998-04-14
申请人： Yimin Huang , Tri-Rung Yew
发明人： Yimin Huang , Tri-Rung Yew
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/76804 , H01L21/7681 , H01L21/76811
摘要： A method of patterning a dielectric layer. On a substrate having a metal wiring layer formed thereon, a dielectric layer and a masking layer are formed. A cap insulation layer is formed on the masking layer before patterning the dielectric layer. In addition, a dual damasecence process is used for patterning the dielectric layer.
摘要翻译：图案化介电层的方法。在其上形成有金属布线层的基板上，形成介电层和掩模层。在图案化电介质层之前，在掩模层上形成帽绝缘层。此外，使用双重破坏过程来对介电层进行图案化。

52. 发明授权

US6146941A Method for fabricating a capacitor in a semiconductor device 失效
标题翻译：在半导体器件中制造电容器的方法
公开(公告)号：US6146941A
公开(公告)日：2000-11-14
申请号：US128221
申请日：1998-08-03
申请人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
发明人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242 , H01L21/8244 , H01L21/20 , H01L21/44 , H01L21/4763
CPC分类号： H01L27/10852 , H01L28/82
摘要： A fabricating method of a capacitor includes two gates and a commonly used source/drain region formed on a substrate. Then, a process of sell align contact has been applied to make a pitted self align contact window (PSACW) to partly expose the commonly used source/drain region. Then an glue/barrier layer and a lower electrode of the capacitor are formed over the PSACW. Then a dielectric thin film with a material having high dielectric constant is formed over the lower electrode. Then, an upper electrode is formed over the dielectric thin film to complete a capacitor, which has a structure of metal insulator metal with a shape like the PSACW.
摘要翻译：电容器的制造方法包括形成在基板上的两个栅极和常用的源极/漏极区域。然后，已经应用了销售对齐接触的过程，以形成凹陷的自对准接触窗口（PSACW）以部分地暴露常用的源极/漏极区域。然后在PSACW上形成电容器的胶/阻挡层和下电极。然后在下部电极上形成具有高介电常数的材料的电介质薄膜。然后，在电介质薄膜的上方形成上部电极，形成电容器，该电容器具有像PSACW的形状的金属绝缘体金属的结构。

53. 发明授权

US6133086A Fabrication method of a tantalum pentoxide dielectric layer for a DRAM capacitor 失效
标题翻译：用于DRAM电容器的五氧化二钽介电层的制造方法
公开(公告)号：US6133086A
公开(公告)日：2000-10-17
申请号：US339154
申请日：1999-06-24
申请人： Kuo-Tai Huang , Tri-Rung Yew
发明人： Kuo-Tai Huang , Tri-Rung Yew
IPC分类号： H01L21/02 , H01L21/316 , H01L21/8242 , H01L21/20 , H01L21/31 , H01L21/469 , H01L27/108
CPC分类号： H01L21/31637 , H01L21/31604 , H01L28/40
摘要： A method of fabricating a dielectric layer for a dynamic random access memory capacitor is described in which a tantalum pentoxide layer is deposited on the polysilicon storage electrode, followed by a two-step treatment on the tantalum pentoxide layer. The first treatment step includes a remote oxygen plasma or an ultraviolet-ozone treatment, followed by a spike annealing second treatment step.
摘要翻译：描述了制造用于动态随机存取存储器电容器的介电层的方法，其中在多晶硅存储电极上沉积五氧化二钽层，然后在五氧化二钽层上进行两步处理。第一处理步骤包括远程氧等离子体或紫外 - 臭氧处理，随后是尖峰退火第二处理步骤。

54. 发明授权

US6077769A Method of fabricating a daul damascene structure 失效
标题翻译：制造daul镶嵌结构的方法
公开(公告)号：US6077769A
公开(公告)日：2000-06-20
申请号：US72311
申请日：1998-05-04
申请人： Yimin Huang , Tony Lin , Tri-Rung Yew
发明人： Yimin Huang , Tony Lin , Tri-Rung Yew
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76811
摘要： A method is provided for fabricating a dual damascene structure on a substrate with a first dielectric layer, an etching stop layer, a second dielectric layer, and a hard mask layer formed on it. The first step is to define the hard mask layer in order to form the first hole, which corresponds to the position of the conductive layer exposing the second dielectric layer. Then, an etching process, including an etching step with medium SiO.sub.2 /SiN etching selectivity and an over-etching step with high SiO.sub.2 /SiN etching selectivity, is performed to form the second hole and the third hole. Finally, a glue/barrier layer and a metal layer are filled into the second hole and the third hole, thus accomplishing a dual damascene structure.
摘要翻译：提供了一种用于在衬底上制造双镶嵌结构的方法，其上形成有第一介电层，蚀刻停止层，第二介电层和硬掩模层。第一步是定义硬掩模层以形成第一孔，其对应于暴露第二电介质层的导电层的位置。然后，进行包括具有中等SiO 2 / SiN蚀刻选择性的蚀刻步骤和具有高SiO 2 / SiN蚀刻选择性的过蚀刻步骤的蚀刻工艺，以形成第二孔和第三孔。最后，将胶/阻挡层和金属层填充到第二孔和第三孔中，从而实现双镶嵌结构。

55. 发明授权

US6010931A Planarization technique for DRAM cell capacitor electrode 失效
标题翻译： DRAM单元电容器电极的平面化技术
公开(公告)号：US6010931A
公开(公告)日：2000-01-04
申请号：US864299
申请日：1997-05-28
申请人： Shih-Wei Sun , Tri-Rung Yew
发明人： Shih-Wei Sun , Tri-Rung Yew
IPC分类号： H01L21/3205 , H01L21/306 , H01L21/336 , H01L21/8242 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10852
摘要： A method of forming a DRAM includes forming a transfer FET on a substrate, the FET having a gate on a gate oxide layer above the substrate and a first and second source/drain region in the substrate on either side of a channel region under the gate. The first and second source/drain regions are typically exposed or nearly exposed in a spacer etch process. A silicon nitride etch stop layer is deposited over the entire structure and then a thick layer of oxide is deposited on the device. Chemical mechanical polishing is performed to provide a planar surface on the thick oxide layer. An opening is formed through the thick layer of oxide above the first source/drain region, stopping at the etch stop layer. The etch stop layer is removed within the opening in the thick layer of oxide and the underlying thin oxide layer is etched. A capacitor electrode can then be formed in contact with the exposed portion of the first source/drain region. A similar self-aligned method can be used to form the bit line contact for the device using the etch stop layer as a stop for the bit line contact etch. Practice of the method provides a manufacturing method having improved reliability and ease of use, particularly when practiced for DRAM capacitors that incorporate high dielectric constant dielectrics. The materials preferred for use within such DRAM capacitors have smaller process margins and so particularly benefit from the improved structure and process.
摘要翻译：形成DRAM的方法包括在衬底上形成转移FET，所述FET在衬底上方的栅极氧化物层上具有栅极，并且在栅极之下的沟道区域的任一侧上的衬底中的第一和第二源极/漏极区域。第一和第二源极/漏极区域通常在间隔物蚀刻工艺中暴露或接近露出。在整个结构上沉积氮化硅蚀刻停止层，然后在器件上沉积厚层氧化物。进行化学机械抛光以在厚氧化物层上提供平坦表面。在第一源极/漏极区域上方的厚的氧化物层形成开口，在蚀刻停止层处停止。蚀刻停止层在氧化物的厚层的开口内去除，并且下面的薄氧化物层被蚀刻。然后可以形成与第一源极/漏极区域的暴露部分接触的电容器电极。可以使用类似的自对准方法来形成使用蚀刻停止层作为位线接触蚀刻停止的器件的位线接触。该方法的实践提供了具有改进的可靠性和易用性的制造方法，特别是当实施用于包含高介电常数电介质的DRAM电容器时。优选用于这种DRAM电容器的材料具有较小的工艺裕度，因此特别受益于改进的结构和工艺。

56. 发明授权

US6001733A Method of forming a dual damascene with dummy metal lines 有权
标题翻译：用虚拟金属线形成双镶嵌的方法
公开(公告)号：US6001733A
公开(公告)日：1999-12-14
申请号：US164856
申请日：1998-10-01
申请人： Yimin Huang , Ming-Sheng Yang , Tri-Rung Yew
发明人： Yimin Huang , Ming-Sheng Yang , Tri-Rung Yew
IPC分类号： H01L21/3205 , H01L21/321 , H01L21/768 , H01L23/52 , H01L21/44
CPC分类号： H01L21/76843 , H01L21/3212 , H01L21/76808 , H01L21/76813 , H01L21/7684 , H01L2221/1031
摘要： A method for forming dual damascene is provided. First, a first inter-metal dielectric layer and a stop layer is formed on a substrate, and then a first photoresist pattern including a via hole and a dummy metal line is patterned and the stop layer is etched for forming via hole. Next, a second inter-metal dielectric layer is deposited and then a second photoresist pattern is patterned for forming metal line trench by etching. Afterwards, a glue layer and a metal layer are blanketed and the dual damascene structure is formed by chemical mechanical polishing.
摘要翻译：提供了一种形成双镶嵌的方法。首先，在基板上形成第一金属间介电层和停止层，然后对包括通孔和虚拟金属线的第一光致抗蚀剂图案进行图案化，并且对停止层进行蚀刻以形成通孔。接下来，沉积第二金属间介电层，然后对第二光致抗蚀剂图案进行图案化以通过蚀刻形成金属线沟槽。然后，胶合层和金属层被覆盖，并通过化学机械抛光形成双镶嵌结构。

57. 发明授权

US08593052B1 Microelectrode array and method for modifying carbon nanotube electrode interface of the same array 有权
标题翻译：微电极阵列和相同阵列碳纳米管电极界面的修饰方法
公开(公告)号：US08593052B1
公开(公告)日：2013-11-26
申请号：US12638429
申请日：2009-12-15
申请人： Shiang-Jie Yen , Huan-Chieh Su , Tri-Rung Yew , Yen-Chung Chang , Wei-Lun Hsu , Shih-Rung Yeh
发明人： Shiang-Jie Yen , Huan-Chieh Su , Tri-Rung Yew , Yen-Chung Chang , Wei-Lun Hsu , Shih-Rung Yeh
IPC分类号： H01J1/63 , H01J63/04 , H01J17/49
CPC分类号： C01B31/0273 , A61N1/0502 , A61N1/0551 , B82Y15/00 , B82Y30/00 , B82Y40/00 , C01B32/174
摘要： The present invention discloses a method for modifying a carbon nanotube electrode interface, which modifies carbon nanotubes used as a neuron-electrode interface by performing three stages of modifications and comprises the steps of: carboxylating carbon nanotubes to provide carboxyl functional groups and improve the hydrophilicity of the carbon nanotubes; acyl-chlorinating the carboxylated carbon nanotubes to replace the hydroxyl functional groups of the carboxyl functional groups with chlorine atoms; and aminating the acyl-chlorinated carbon nanotubes to replace the chlorine atoms with a derivative having amine functional groups at the terminal thereof. The modified carbon nanotubes used as the neuron-electrode interface has lower impedance and higher adherence to nerve cells. Thus is improved the quality of neural signal measurement. The present invention also discloses a microelectrode array, wherein the neuron-electrode interface uses carbon nanotubes modified according to the method of the present invention.
摘要翻译：本发明公开了一种修饰碳纳米管电极界面的方法，其通过进行三个阶段的修饰来改变用作神经元 - 电极界面的碳纳米管，并且包括以下步骤：使碳纳米管羧化以提供羧基官能团并提高其亲水性碳纳米管; 酰化氯化羧化碳纳米管以用氯原子代替羧基官能团的羟基官能团; 并将酰基氯化碳纳米管胺化以在其末端具有胺官能团的衍生物代替氯原子。用作神经元 - 电极界面的改性碳纳米管具有较低的阻抗和较高的对神经细胞的依从性。因此提高了神经信号测量的质量。本发明还公开了一种微电极阵列，其中神经电极界面使用根据本发明的方法改性的碳纳米管。

58. 发明授权

US08283469B2 Perylene diimide derivative and organic semiconductor element using the same material 有权
标题翻译：苝二酰亚胺衍生物和使用相同材料的有机半导体元件
公开(公告)号：US08283469B2
公开(公告)日：2012-10-09
申请号：US12730542
申请日：2010-03-24
申请人： Szu-Ying Chen , Heng-Wen Ting , Tri-Rung Yew , Jeng-Hua Wei
发明人： Szu-Ying Chen , Heng-Wen Ting , Tri-Rung Yew , Jeng-Hua Wei
IPC分类号： C07D471/02 , H01L29/12
CPC分类号： C07D471/04 , H01L51/0053 , H01L51/0541
摘要： The present invention discloses a soluble and air-stable perylene diimide (PDI) derivative to function as an N-type organic semiconductor material. In the PDI derivative of the present invention, the core thereof is substituted by electron withdrawing groups, and the side chains thereof are substituted by benzene functional groups, whereby are promoted the solubility and air-stability of the molecule. The PDI derivative of the present invention can be used to fabricate an organic semiconductor element via a soluble process at a low temperature and under an atmospheric environment.
摘要翻译：本发明公开了用作N型有机半导体材料的可溶性和空气稳定的苝二酰亚胺（PDI）衍生物。在本发明的PDI衍生物中，其核心被吸电子基团取代，其侧链被苯官能团取代，从而促进了分子的溶解度和空气稳定性。本发明的PDI衍生物可用于在低温和大气环境下通过可溶性方法制造有机半导体元件。

59. 发明申请

US20120152335A1 FULL-SPECTRUM ABSORPTION SOLAR CELL 审中-公开
标题翻译：全光谱吸收太阳能电池
公开(公告)号：US20120152335A1
公开(公告)日：2012-06-21
申请号：US12973101
申请日：2010-12-20
申请人： Hui-Ying SHIU , Tri-Rung Yew
发明人： Hui-Ying SHIU , Tri-Rung Yew
IPC分类号： H01L31/0256
CPC分类号： H01L31/18 , H01L31/032 , H01L31/0321 , H01L31/0336 , H01L31/072 , Y02E10/50
摘要： A full-spectrum absorption solar cell adopts cobalt-doped tin dioxide as an N-type material. Thereby, a solar cell of the present invention can be fabricated by a spray method in a hot pressing fabrication process. The present invention does not need to fabricate a solar cell in a vacuum or furnace system and thus can solve the high cost problem of the conventional technology. The N-type cobalt-doped layer can absorb full spectrum of sunlight. The N-type cobalt-doped layer can be used to fabricate a solar cell with a low-temperature fabrication process. Thus, the present invention does not need to adopt a high-temperature resistant substrate (such as silicon chip or glass) used in the conventional high-temperature fabrication process but can adopt a substrate made of plastic. And, the conversion efficiency of the invention can achieve 1.2%, it is a significant improvement over the oxide-based nanostructures heterojunction solar cells in the world.
摘要翻译：全光谱吸收太阳能电池采用钴掺杂二氧化锡作为N型材料。因此，本发明的太阳能电池可以通过喷涂法在热压制造工艺中制造。本发明不需要在真空或炉系中制造太阳能电池，因此可以解决传统技术的高成本问题。 N型钴掺杂层可吸收全光谱。 N型钴掺杂层可用于制造具有低温制造工艺的太阳能电池。因此，本发明不需要采用常规高温制造工艺中使用的耐高温基板（例如硅芯片或玻璃），而是可以采用由塑料制成的基板。而且，本发明的转换效率可以达到1.2％，相对于世界上基于氧化物的纳米结构异质结太阳能电池来说，这是一个显着的改进。

60. 发明申请

US20120135598A1 METHOD FOR FABRICATING INTERCONNECTIONS WITH CARBON NANOTUBES 有权
标题翻译：用碳纳米管制备互连的方法
公开(公告)号：US20120135598A1
公开(公告)日：2012-05-31
申请号：US13094388
申请日：2011-04-26
申请人： Hsin-wei WU , Chung-Min Tsai , Tri-Rung Yew
发明人： Hsin-wei WU , Chung-Min Tsai , Tri-Rung Yew
IPC分类号： H01L21/768
CPC分类号： H01L23/53276 , H01L21/76849 , H01L21/76876 , H01L21/76879 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating interconnections with carbon nanotubes of the present invention comprises the following steps: forming a dual-layer that contains a catalytic layer and an upper covering layer on the periphery of a hole connecting with a substrate; and growing carbon nanotubes on the catalytic layer with the upper covering layer covering the carbon nanotubes. The present invention grows the carbon nanotubes between the catalytic layer and the upper covering layer. The upper covering layer protects the catalytic layer from being oxidized and thus enhances the growth of the carbon nanotubes. The carbon nanotubes are respectively connected with the lower substrate and an upper conductive wire via the catalytic layer and the upper covering layer, which results in a lower contact resistance. Moreover, the upper covering layer also functions as a metal-diffusion barrier layer to prevent metal from spreading to other materials via diffusion or other approaches.
摘要翻译：本发明的制造与碳纳米管的互连的方法包括以下步骤：在与基板连接的孔的周围形成包含催化剂层和上覆盖层的双层; 并在上覆盖层覆盖碳纳米管的催化层上生长碳纳米管。本发明在催化层和上覆盖层之间生长碳纳米管。上覆盖层保护催化层不被氧化，从而增强碳纳米管的生长。碳纳米管分别通过催化层和上覆盖层与下基板和上导电线连接，导致较低的接触电阻。此外，上覆盖层还用作金属扩散阻挡层，以防止金属通过扩散或其它方法扩散到其它材料。

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