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1. 发明授权

US07378740B2 Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit 有权
标题翻译：用于集成电路中多级互连的布线结构的双镶嵌结构
公开(公告)号：US07378740B2
公开(公告)日：2008-05-27
申请号：US11196038
申请日：2005-08-02
申请人： Tri-Rung Yew , Yimin Huang , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Yimin Huang , Water Lur , Shih-Wei Sun
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/7681 , H01L21/76832 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.
摘要翻译：提供了一种改进的双镶嵌结构，用于集成电路中多级互连的布线结构。在这种双镶嵌结构中，使用低K（低介电常数）介电材料来形成IC器件中的金属互连之间的二电层和蚀刻停止层。利用该特征，双镶嵌结构可以防止在其中发生高的寄生电容，否则会对通过金属互连传输的信号造成较大的RC延迟，从而降低IC器件的性能。利用双镶嵌结构，可以减少这种寄生电容，从而确保IC器件的性能。

2. 发明授权

US06680248B2 Method of forming dual damascene structure 有权
标题翻译：形成双镶嵌结构的方法
公开(公告)号：US06680248B2
公开(公告)日：2004-01-20
申请号：US09991131
申请日：2001-11-20
申请人： Yimin Huang , Tri-Rung Yew
发明人： Yimin Huang , Tri-Rung Yew
IPC分类号： H01L214763
CPC分类号： H01L21/76829 , H01L21/76807
摘要： A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first dielectric layer, the anti-reflection layer and the second dielectric layer are patterned to form a first opening that exposes the conductive layer. Thereafter, the second dielectric layer is patterned to form a trench (or second opening) in a position above the first conductive layer. The trench and the first opening together form an opening of the dual damascene structure. Finally, a second conductive material is deposited into the opening and the trench to form conductive lines and the dual damascene structures.
摘要翻译：形成双镶嵌结构的方法包括以下步骤：提供其上形成有第一导电层的衬底，然后在衬底上顺序形成第一电介质层，抗反射层和第二电介质层。接下来，对第一电介质层，抗反射层和第二电介质层进行图案化以形成暴露导电层的第一开口。此后，第二介电层被图案化以在第一导电层上方的位置形成沟槽（或第二开口）。沟槽和第一开口一起形成双镶嵌结构的开口。最后，将第二导电材料沉积到开口和沟槽中以形成导电线和双镶嵌结构。

3. 发明授权

US06352918B1 Method of forming inter-metal interconnection 有权
标题翻译：形成金属间互连的方法
公开(公告)号：US06352918B1
公开(公告)日：2002-03-05
申请号：US09199877
申请日：1998-11-24
申请人： Yimin Huang , Chih-Chien Liu , Tri-Rung Yew
发明人： Yimin Huang , Chih-Chien Liu , Tri-Rung Yew
IPC分类号： H01L21311
CPC分类号： H01L21/76802
摘要： A method of forming an inter-metal interconnection is provided. A substrate is provided. A dielectric layer with a metal plug therein is formed on the substrate. An IMD layer is formed on the dielectric layer. An insulating layer and a PE-oxide layer are formed on the IMD layer. A photolithography and etching process is performed to form a trench in the IMD layer and to expose the metal plug in the dielectric layer. A metal is filled into the trench to electrically connect to the metal plug.
摘要翻译：提供了形成金属间互连的方法。提供基板。在基板上形成有金属塞的电介质层。在电介质层上形成IMD层。在IMD层上形成绝缘层和PE-氧化物层。进行光刻和蚀刻工艺以在IMD层中形成沟槽并露出介电层中的金属插塞。将金属填充到沟槽中以电连接到金属插头。

4. 发明授权

US6069066A Method of forming bonding pad 有权
标题翻译：形成焊盘的方法
公开(公告)号：US6069066A
公开(公告)日：2000-05-30
申请号：US208025
申请日：1998-12-09
申请人： Yimin Huang , Tri-Rung Yew
发明人： Yimin Huang , Tri-Rung Yew
IPC分类号： H01L21/60 , H01L23/485 , H01L21/44
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L2224/0401 , H01L2224/05546 , H01L2224/05647 , H01L2224/13099 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14
摘要： A method of forming a bonding pad is provided. A substrate is provided and a multi-metal layer is formed on the substrate. An inter-metal dielectric layer with a trench is formed on the multi-metal layer. A conformal barrier layer is formed on the inter-metal dielectric layer. A first metal layer is formed on the barrier layer to fill a part of the trench. A second metal layer is formed on the first metal layer to fill the trench. A part of the first metal layer and a part of the second metal layer flowing out the trench are removed to expose the inter-metal dielectric layer. A cap layer is formed on the inter-metal dielectric layer. A passivation layer is formed on the cap layer. A part of the passivation and a part of the cap layer are removed to form a bonding pad window by a defined masking layer.
摘要翻译：提供一种形成接合焊盘的方法。设置基板，在基板上形成多金属层。在多金属层上形成具有沟槽的金属间介电层。在金属间电介质层上形成保形阻挡层。在阻挡层上形成第一金属层以填充沟槽的一部分。在第一金属层上形成第二金属层以填充沟槽。去除第一金属层的一部分和流出沟槽的第二金属层的一部分，以露出金属间介电层。在金属间介电层上形成盖层。在盖层上形成钝化层。通过限定的掩模层去除钝化部分和覆盖层的一部分以形成焊盘窗口。

5. 发明授权

US06027994A Method to fabricate a dual metal-damascene structure in a substrate 失效
标题翻译：在基材中制造双金属镶嵌结构的方法
公开(公告)号：US06027994A
公开(公告)日：2000-02-22
申请号：US102083
申请日：1998-06-22
申请人： Yimin Huang , Tri-Rung Yew
发明人： Yimin Huang , Tri-Rung Yew
IPC分类号： H01L21/768 , H01L23/522 , H01L21/4763
CPC分类号： H01L21/76808 , H01L23/5226 , H01L2221/1031 , H01L2924/0002
摘要： A method to fabricate a dual damascene structure in a substrate is disclosed in the present invention. A first silicon oxide layer is deposited over the substrate and a silicon nitride layer is formed on the first silicon oxide layer. The first silicon oxide layer and the silicon nitride layer are etched in order to form a via hole on the substrate. Afterwards, a second silicon oxide layer is deposited to refill into the via hole and to cover the silicon nitride layer. A dry etching process is performed to remove the second silicon oxide layer in the via hole and to form a metal trench in the second silicon oxide layer on the silicon nitride layer and a metal trench in the second silicon oxide layer above the via hole. After the formation of the metal trenches, a portion of the second silicon oxide layer is remained on the sidewalls and the bottom of the via hole. A dry etching process is performed to remove the remaining portion of the second silicon oxide layer. At last, metal material is deposited to refill into the via hole and the metal trench, it is followed by the metal CMP processs to remove the excess metal over the silicon oxide. The dual metal-damascene structure on the substrate is complete.
摘要翻译：在本发明中公开了一种在衬底中制造双镶嵌结构的方法。在衬底上沉积第一氧化硅层，在第一氧化硅层上形成氮化硅层。蚀刻第一氧化硅层和氮化硅层以在基板上形成通孔。然后，沉积第二氧化硅层以重新填充到通孔中并覆盖氮化硅层。进行干蚀刻处理以去除通孔中的第二氧化硅层，并且在氮化硅层上的第二氧化硅层中形成金属沟槽，在通孔上方的第二氧化硅层中形成金属沟槽。在形成金属沟槽之后，第二氧化硅层的一部分残留在通孔的侧壁和底部。执行干蚀刻处理以去除第二氧化硅层的剩余部分。最后，沉积金属材料以再填充到通孔和金属沟槽中，之后是金属CMP工艺以除去氧化硅上的多余金属。基板上的双金属镶嵌结构完整。

6. 发明授权

US06191028B1 Method of patterning dielectric 失效
标题翻译：电介质图案方法
公开(公告)号：US06191028B1
公开(公告)日：2001-02-20
申请号：US09059751
申请日：1998-04-14
申请人： Yimin Huang , Tri-Rung Yew
发明人： Yimin Huang , Tri-Rung Yew
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/76804 , H01L21/7681 , H01L21/76811
摘要： A method of patterning a dielectric layer. On a substrate having a metal wiring layer formed thereon, a dielectric layer and a masking layer are formed. A cap insulation layer is formed on the masking layer before patterning the dielectric layer. In addition, a dual damasecence process is used for patterning the dielectric layer.
摘要翻译：图案化介电层的方法。在其上形成有金属布线层的基板上，形成介电层和掩模层。在图案化电介质层之前，在掩模层上形成帽绝缘层。此外，使用双重破坏过程来对介电层进行图案化。

7. 发明授权

US6077769A Method of fabricating a daul damascene structure 失效
标题翻译：制造daul镶嵌结构的方法
公开(公告)号：US6077769A
公开(公告)日：2000-06-20
申请号：US72311
申请日：1998-05-04
申请人： Yimin Huang , Tony Lin , Tri-Rung Yew
发明人： Yimin Huang , Tony Lin , Tri-Rung Yew
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76811
摘要： A method is provided for fabricating a dual damascene structure on a substrate with a first dielectric layer, an etching stop layer, a second dielectric layer, and a hard mask layer formed on it. The first step is to define the hard mask layer in order to form the first hole, which corresponds to the position of the conductive layer exposing the second dielectric layer. Then, an etching process, including an etching step with medium SiO.sub.2 /SiN etching selectivity and an over-etching step with high SiO.sub.2 /SiN etching selectivity, is performed to form the second hole and the third hole. Finally, a glue/barrier layer and a metal layer are filled into the second hole and the third hole, thus accomplishing a dual damascene structure.
摘要翻译：提供了一种用于在衬底上制造双镶嵌结构的方法，其上形成有第一介电层，蚀刻停止层，第二介电层和硬掩模层。第一步是定义硬掩模层以形成第一孔，其对应于暴露第二电介质层的导电层的位置。然后，进行包括具有中等SiO 2 / SiN蚀刻选择性的蚀刻步骤和具有高SiO 2 / SiN蚀刻选择性的过蚀刻步骤的蚀刻工艺，以形成第二孔和第三孔。最后，将胶/阻挡层和金属层填充到第二孔和第三孔中，从而实现双镶嵌结构。

8. 发明授权

US6025264A Fabricating method of a barrier layer 失效
标题翻译：阻挡层的制造方法
公开(公告)号：US6025264A
公开(公告)日：2000-02-15
申请号：US52608
申请日：1998-03-31
申请人： Tri-Rung Yew , Water Lur , Shih-Wei Sun , Yimin Huang
发明人： Tri-Rung Yew , Water Lur , Shih-Wei Sun , Yimin Huang
IPC分类号： H01L21/28 , H01L21/336 , H01L21/768 , H01L23/522 , H01L29/78
CPC分类号： H01L21/76843 , H01L23/5226 , H01L2924/0002
摘要： A method for forming a barrier layer comprising the steps of first providing a semiconductor substrate that has a conductive layer already formed thereon. Then, a dielectric layer such as an organic low-k dielectric layer is deposited over the conductive layer and the semiconductor substrate. Next, an opening in formed in the dielectric layer exposing the conductive layer. Thereafter, a first barrier layer is deposited into the opening and the surrounding area. The first barrier layer can be a silicon-contained layer or a doped silicon (doped-Si) layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method, a low-pressure chemical vapor deposition (LPCVD) method, an electron beam evaporation method or a sputtering method. Finally, a second barrier layer is formed over the first barrier layer. The second barrier layer can be a titanium/titanium nitride (Ti/TiN) layer, a tungsten nitride (WN) layer, a tantalum (Ta) layer or a tantalum nitride (TaN) layer.
摘要翻译：一种用于形成阻挡层的方法，包括以下步骤：首先提供其上已经形成有导电层的半导体衬底。然后，在导电层和半导体衬底上沉积诸如有机低k电介质层的电介质层。接下来，形成在暴露导电层的电介质层中的开口。此后，第一阻挡层沉积到开口和周围区域中。第一阻挡层可以是通过等离子体增强化学气相沉积（PECVD）法，低压化学气相沉积法（LPCVD）法，电子束蒸发法或溅射法。最后，在第一阻挡层上形成第二阻挡层。第二阻挡层可以是钛/氮化钛（Ti / TiN）层，氮化钨（WN）层，钽（Ta）层或氮化钽（TaN）层。

9. 发明授权

US6001733A Method of forming a dual damascene with dummy metal lines 有权
标题翻译：用虚拟金属线形成双镶嵌的方法
公开(公告)号：US6001733A
公开(公告)日：1999-12-14
申请号：US164856
申请日：1998-10-01
申请人： Yimin Huang , Ming-Sheng Yang , Tri-Rung Yew
发明人： Yimin Huang , Ming-Sheng Yang , Tri-Rung Yew
IPC分类号： H01L21/3205 , H01L21/321 , H01L21/768 , H01L23/52 , H01L21/44
CPC分类号： H01L21/76843 , H01L21/3212 , H01L21/76808 , H01L21/76813 , H01L21/7684 , H01L2221/1031
摘要： A method for forming dual damascene is provided. First, a first inter-metal dielectric layer and a stop layer is formed on a substrate, and then a first photoresist pattern including a via hole and a dummy metal line is patterned and the stop layer is etched for forming via hole. Next, a second inter-metal dielectric layer is deposited and then a second photoresist pattern is patterned for forming metal line trench by etching. Afterwards, a glue layer and a metal layer are blanketed and the dual damascene structure is formed by chemical mechanical polishing.
摘要翻译：提供了一种形成双镶嵌的方法。首先，在基板上形成第一金属间介电层和停止层，然后对包括通孔和虚拟金属线的第一光致抗蚀剂图案进行图案化，并且对停止层进行蚀刻以形成通孔。接下来，沉积第二金属间介电层，然后对第二光致抗蚀剂图案进行图案化以通过蚀刻形成金属线沟槽。然后，胶合层和金属层被覆盖，并通过化学机械抛光形成双镶嵌结构。

10. 发明授权

US06987057B2 Method making bonding pad 有权
标题翻译：方法制作焊盘
公开(公告)号：US06987057B2
公开(公告)日：2006-01-17
申请号：US10229443
申请日：2002-08-27
申请人： Ellis Lee , Yimin Huang , Tri-Rung Yew
发明人： Ellis Lee , Yimin Huang , Tri-Rung Yew
IPC分类号： H01L21/44
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L24/45 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05624 , H01L2224/13099 , H01L2224/45144 , H01L2224/48624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/04941 , H01L2924/04953 , H01L2924/0496 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： An bonding pad structure has a passivation layer over a copper layer having a pad window to expose a portion of the copper layer, a barrier layer conformal to a profile of the pad window, and an aluminum pad located in the pad window. The metal layer can be an aluminum, aluminum alloy or aluminum dominated layer for providing a better adhesion property between the copper layer and the bonding wire.
摘要翻译：焊盘结构在铜层上具有钝化层，该钝化层具有用于暴露铜层的一部分的焊盘窗口，与焊盘窗口的轮廓一致的阻挡层和位于焊盘窗口中的铝焊盘。金属层可以是铝，铝合金或铝主导层，用于在铜层和接合线之间提供更好的粘合性能。

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