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51. 发明授权

US06908837B2 Method of manufacturing a semiconductor integrated circuit device including a gate electrode having a salicide layer thereon 有权
标题翻译：一种半导体集成电路器件的制造方法，其包括在其上具有自对准硅层的栅电极
公开(公告)号：US06908837B2
公开(公告)日：2005-06-21
申请号：US10251849
申请日：2002-09-23
申请人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
发明人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
IPC分类号： H01L27/04 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L21/8247 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/78 , H01L21/44
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823835 , H01L21/823857 , H01L21/823864 , H01L27/105 , H01L27/10814 , H01L27/10894 , H01L27/11546 , H01L29/1083 , H01L29/665 , H01L29/7833 , H01L29/7835 , Y10S438/981
摘要： A method of manufacturing a semiconductor integrated circuit device includes the steps of depositing a first insulating film over a first conductive layer, patterning the first insulating film by using a resist film as a mask to form a cap film, and removing the resist film. After which, a gate electrode of a MISFET is formed by etching the first conductive layer using the cap film as a mask. A second insulating film is deposited over the gate electrode and the cap film and a side wall spacer formed on side surfaces of the gate electrode by etching the second insulating film. After which, a salicide layer is selectively formed on the gate electrode. The cap film is removed by over-etching the first insulating film to etch the cap film.
摘要翻译：一种制造半导体集成电路器件的方法包括以下步骤：在第一导电层上沉积第一绝缘膜，通过使用抗蚀剂膜作为掩模来图案化第一绝缘膜以形成盖膜，并除去抗蚀剂膜。之后，通过使用盖膜作为掩模蚀刻第一导电层来形成MISFET的栅电极。通过蚀刻第二绝缘膜，在栅电极和盖膜上沉积第二绝缘膜和形成在栅电极的侧表面上的侧壁间隔物。之后，在栅电极上选择性地形成自对准硅层。通过对第一绝缘膜进行过蚀刻来去除帽膜以蚀刻帽膜。

52. 发明申请

US20050082622A1 Semiconductor integrated circuit device and process for manufacturing the same 有权
公开(公告)号：US20050082622A1
公开(公告)日：2005-04-21
申请号：US10971073
申请日：2004-10-25
申请人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
发明人： Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
IPC分类号： G11C11/412 , H01L21/768 , H01L21/8244 , H01L27/11 , H01L21/84 , H01L29/94
CPC分类号： H01L27/11 , G11C11/412 , G11C11/4125 , H01L21/76895 , H01L27/0203 , H01L27/0207 , H01L27/1104 , Y10S257/904
摘要： A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

53. 发明申请

US20050017296A1 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050017296A1
公开(公告)日：2005-01-27
申请号：US10921327
申请日：2004-08-19
申请人： Yutaka Hoshino , Shuji Ikeda , Isao Yoshida , Shiro Kamohara , Megumi Kawakami , Tomoyuki Miyake , Masatoshi Morikawa
发明人： Yutaka Hoshino , Shuji Ikeda , Isao Yoshida , Shiro Kamohara , Megumi Kawakami , Tomoyuki Miyake , Masatoshi Morikawa
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8234 , H01L23/482 , H01L23/532 , H01L27/04 , H01L27/088 , H01L29/417 , H01L29/80
CPC分类号： H01L29/66659 , H01L21/823475 , H01L21/823871 , H01L23/4827 , H01L23/53219 , H01L23/53295 , H01L27/0255 , H01L27/088 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/086 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/4175 , H01L29/41758 , H01L29/42368 , H01L29/4238 , H01L29/4916 , H01L29/7835 , H01L29/861 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).
摘要翻译：在具有漏极偏移区域的高频放大MOSFET中，通过在源极区域10，漏极区域9和浸出层9上引出电极的导体插头13（P1）来减小尺寸并降低导通电阻。连接有第一层布线11a，11d（M1）的第3层（4），另外，背面的第二层布线12a〜12d在导体插塞13（P1）上连接到第一层布线11s，11d（M1 ）。

54. 发明授权

US06713353B1 Method of manufacturing a semiconductor integrated circuit device 有权
公开(公告)号：US06713353B1
公开(公告)日：2004-03-30
申请号：US09536756
申请日：2000-03-28
申请人： Takayuki Kanda , Atsushi Hiraiwa , Norio Suzuki , Satoshi Sakai , Shuji Ikeda , Yasuko Yoshida , Shinichi Horibe
发明人： Takayuki Kanda , Atsushi Hiraiwa , Norio Suzuki , Satoshi Sakai , Shuji Ikeda , Yasuko Yoshida , Shinichi Horibe
IPC分类号： H01L218234
CPC分类号： H01L21/823878 , H01L21/823857
摘要： A protection film is formed on a silicon oxide film 6 formed on the surface of a semiconductor substrate, a silicon oxide film is removed from a region where a thin gate-insulating film is to be formed by using, as a mask, a photoresist pattern that covers a region where a thick gate-insulating film is to be formed, and, then, the photoresist pattern is removed followed by washing. Then, the semiconductor substrate is heat-oxidized or a film is deposited thereon to form gate-insulating films having different thicknesses.

55. 发明授权

US06703667B2 Semiconductor integrated circuit device with connections formed using a conductor embedded in a contact hole 有权
公开(公告)号：US06703667B2
公开(公告)日：2004-03-09
申请号：US10303024
申请日：2002-11-25
申请人： Koichiro Ishibashi , Shuji Ikeda , Harumi Wakimoto , Kenichi Kuroda
发明人： Koichiro Ishibashi , Shuji Ikeda , Harumi Wakimoto , Kenichi Kuroda
IPC分类号： H01L2976
CPC分类号： H01L27/092
摘要： The metal layers embedded into the contact holes of various kinds in shape are used as the lines and are employed as the lines for controlling the substrate bias. The first-layer metal line layers are made thin so as to be also employed as the lines for controlling the substrate bias. Moreover, the second-layer metal line layers are employed as the copper line layers. Thereby, a semiconductor integrated circuit which allows a high-speed and low-power operation is provided with a small area and without increasing the number of the masks.

56. 发明授权

US06693001B2 Process for producing semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US06693001B2
公开(公告)日：2004-02-17
申请号：US09380735
申请日：2000-02-04
申请人： Shinji Nishihara , Shuji Ikeda , Naotaka Hashimoto , Hiroshi Momiji , Hiromi Abe , Shinichi Fukada , Masayuki Suzuki
发明人： Shinji Nishihara , Shuji Ikeda , Naotaka Hashimoto , Hiroshi Momiji , Hiromi Abe , Shinichi Fukada , Masayuki Suzuki
IPC分类号： H01L218238
CPC分类号： H01L21/28518 , H01L21/2855 , H01L23/53223 , H01L29/456 , H01L29/4933 , H01L2924/0002 , H01L2924/00
摘要： A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.
摘要翻译：通过使用高纯度Co靶通过溅射将沉积在晶片的主平面上的Co膜进行硅化，在MOSFET的栅极，源极和漏极的表面上形成具有低电阻和小的结漏电流的Co硅化物层 Co纯度至少为99.99％，Fe和Ni含量不大于10ppm，Co的纯度优选为99.999％。

57. 发明授权

US06686108B2 Fabrication method of semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US06686108B2
公开(公告)日：2004-02-03
申请号：US09964341
申请日：2001-09-28
申请人： Osamu Inoue , Norio Hasegawa , Shuji Ikeda
发明人： Osamu Inoue , Norio Hasegawa , Shuji Ikeda
IPC分类号： G03F900
CPC分类号： G03F1/32 , G03F1/36 , G03F7/70125 , Y10S430/146
摘要： On the occasion of the aligning process to transfer a predetermined pattern to a semiconductor wafer by irradiating a photoresist on the semiconductor wafer with an aligning laser beam of the modified lighting via a photomask MK, the photomask MK allocating, to provide periodicity, the main apertures to transfer the predetermined pattern as the apertures formed by removing a part of the half-tone film on the mask substrate and the auxiliary apertures not resolved on the semiconductor wafer as the apertures formed by removing a part of the half-tone film is used to improve the resolution of the pattern.
摘要翻译：在通过经由光掩模MK照射经修改的照明的定向激光束在半导体晶片上照射光致抗蚀剂以将预定图案转印到半导体晶片的对准处理的情况下，光掩模MK分配以提供周期性的主孔通过去除掩模基板上的半色调膜的一部分而形成的孔，并且通过将半色调膜的一部分形成的孔用于提高模式的分辨率。

58. 发明授权

US06677649B2 SRAM cells with two P-well structure 有权
标题翻译：具有两个P阱结构的SRAM单元
公开(公告)号：US06677649B2
公开(公告)日：2004-01-13
申请号：US09565535
申请日：2000-05-05
申请人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
发明人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
IPC分类号： H01L2976
CPC分类号： H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
摘要： Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.
摘要翻译：现有的已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底进行电接触，这将导致不对称性导致了微图案化困难的问题的发生。为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。在阵列的中间位置处，以与字线平行的方式形成用于向基板供电的区域，以每组三十二个存储单元行或六十四个单元行提供一个区域。

59. 发明授权

US06569742B1 Method of manufacturing semiconductor integrated circuit device having silicide layers 有权
标题翻译：制造具有硅化物层的半导体集成电路器件的方法
公开(公告)号：US06569742B1
公开(公告)日：2003-05-27
申请号：US09471321
申请日：1999-12-23
申请人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
发明人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
IPC分类号： H01L21336
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823835 , H01L21/823857 , H01L21/823864 , H01L27/105 , H01L27/10814 , H01L27/10894 , H01L27/11546 , H01L29/1083 , H01L29/665 , H01L29/7833 , H01L29/7835 , Y10S438/981
摘要： A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.
摘要翻译：能够进行高速运转的MISFET包括在自对准的基础上与栅极侧壁层对准的高浓度区域的金属硅化物层。可以以高电压驱动的MISFET包括具有大于侧壁层的宽度的宽度的LDD部分，与LDD部分接触的高浓度区域和高浓度区域中的金属硅化物层。

60. 发明授权

US06512245B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06512245B2
公开(公告)日：2003-01-28
申请号：US09859045
申请日：2001-05-17
申请人： Shuji Ikeda , Satoshi Meguro , Kyoichiro Asayama , Eri Fujita , Koichiro Ishibashi , Toshiro Aoto , Sadayuki Morita , Atsuyoshi Koike , Masayuki Kojima , Yasuo Kiguchi , Kazuyuki Suko , Fumiyuki Kanai , Naotaka Hashimoto , Toshiaki Yamanaka
发明人： Shuji Ikeda , Satoshi Meguro , Kyoichiro Asayama , Eri Fujita , Koichiro Ishibashi , Toshiro Aoto , Sadayuki Morita , Atsuyoshi Koike , Masayuki Kojima , Yasuo Kiguchi , Kazuyuki Suko , Fumiyuki Kanai , Naotaka Hashimoto , Toshiaki Yamanaka
IPC分类号： H01L2972
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.
摘要翻译：一种静态随机存取存储器，包括由字线控制的转移MISFET和由驱动器MISFET和负载MISFET构成的触发电路组成的存储单元。负载MISFET的顶部覆盖有电源电压线，使得层叠结构的电容器元件形成在负载MISFET的栅电极和电源电压线之间。

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