专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US4942556A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4942556A
公开(公告)日：1990-07-17
申请号：US377181
申请日：1989-07-10
申请人： Toshio Sasaki , Masakazu Aoki , Masashi Horiguchi , Yoshinobu Nakagome , Shinichi Ikenaga , Toshiaki Masuhara
发明人： Toshio Sasaki , Masakazu Aoki , Masashi Horiguchi , Yoshinobu Nakagome , Shinichi Ikenaga , Toshiaki Masuhara
IPC分类号： G11C15/04 , G11C29/00 , G11C29/44
CPC分类号： G11C29/76 , G11C15/04 , G11C15/046 , G11C29/44
摘要： In a defect relieving technology which replaces defective memory cells of a semiconductor memory device by spare memory cells, use is made of an associative memory. Address information of a defective memory cell is stored as a reference data of the associative memory, and new address information of a spare memory cell is written down as output data of the associative memory. A variety of improvements are made to the associative memory. For instance, a plurality of coincidence detection signal lines of the associative memory are divided into at least two groups, and one group among them is selected by switching means. Reference data of the associative memory comprises three values consisting of binary information of "0" and "1", and don't care value "X". The associative memory further includes a plurality of electrically programable non-volatile semiconductor memory elements.
摘要翻译：在通过备用存储器单元代替半导体存储器件的缺陷存储单元的缺陷解除技术中，使用关联存储器。存储有缺陷的存储单元的地址信息被存储为关联存储器的参考数据，并且备用存储单元的新地址信息被写入作为关联存储器的输出数据。对联想记忆进行了各种改进。例如，关联存储器的多个符合检测信号线被划分为至少两组，其中一组由切换装置选择。关联存储器的参考数据包括由“0”和“1”的二进制信息组成的三个值，并且不关心值“X”。关联存储器还包括多个可电可编程的非易失性半导体存储器元件。

52. 发明授权

US4709350A Semiconductor memory using multiple level storage structure 失效
标题翻译：半导体存储器采用多级存储结构
公开(公告)号：US4709350A
公开(公告)日：1987-11-24
申请号：US627895
申请日：1984-07-05
申请人： Yoshinobu Nakagome , Masakazu Aoki , Masashi Horiguchi , Katsuhiro Shimohigashi , Shinichi Ikenaga
发明人： Yoshinobu Nakagome , Masakazu Aoki , Masashi Horiguchi , Katsuhiro Shimohigashi , Shinichi Ikenaga
IPC分类号： G11C14/00 , G11C11/56 , G11C19/00 , G11C27/00
CPC分类号： G11C19/00 , G11C11/565 , G11C8/04
摘要： In a semiconductor memory for reading and writing of stored charge in an X-Y address system by arranging a plurality of memory cells each including a capacitance element and one MOS-FET in matrix, this invention discloses a semiconductor memory using multiple level storage structure for read and write of at least more than two multi-level data stored in the capacitance elements, by applying a multi-level step voltage to the plate electrode of the capacitance or to the gate electrode of MOS-FET so as to write and read signal charge.
摘要翻译：在通过将包括电容元件和一个MOS-FET的多个存储单元布置在矩阵中的用于在XY地址系统中读取和写入存储电荷的半导体存储器中，本发明公开了一种使用多级存储结构进行读取和通过对电容器的平板电极或MOS-FET的栅电极施加多电平阶梯电压以写入和读取信号电荷，写入存储在电容元件中的至少两个多电平数据。

53. 发明授权

US08152483B2 Variable capacity compressor 失效
标题翻译：可变容量压缩机
公开(公告)号：US08152483B2
公开(公告)日：2012-04-10
申请号：US12296206
申请日：2007-04-05
申请人： Makoto Kawamura , Masakazu Aoki
发明人： Makoto Kawamura , Masakazu Aoki
IPC分类号： F04B1/12 , F04B27/08
CPC分类号： F04B27/1072
摘要： The variable capacity compressor has a rotor 21, as a rotating member, fixed to a drive shaft 10 and rotating integrally with the drive shaft 10, a swash plate 24, as a tilting member, tiltably and slidably attached to the drive shaft 10, a linkage mechanism 40 linking the rotor 21 and the swash plate 24 at a position corresponding to an upper dead center of the swash plate 24, transferring rotation of the rotor 21 to the swash plate 24, and guiding the tilting movement of the swash plate 24, and a tilting movement guide 60 provided between the rotor 21 and the swash plate 24 and anterior to the linkage mechanism 40 in the rotating direction and guiding changes of the inclination angle of the swash plate 24 with respect to the drive shaft 10.
摘要翻译：可变容量压缩机具有作为旋转构件的转子21，其固定到驱动轴10并与驱动轴10一体旋转;作为倾斜构件的斜盘24可倾斜并可滑动地附接到驱动轴10，连接机构40将转子21和旋转斜盘24连接在与斜盘24的上止点对应的位置，将转子21的旋转传递到旋转斜盘24，以及引导斜盘24的倾斜运动，以及倾斜运动引导件60，其设置在转子21和旋转斜盘24之间并且在连动机构40的旋转方向前方，并且引导斜盘24相对于驱动轴10的倾斜角度的变化。

54. 发明申请

US20080089795A1 Water-Injected Compressor 有权
标题翻译：注水压缩机
公开(公告)号：US20080089795A1
公开(公告)日：2008-04-17
申请号：US11844053
申请日：2007-08-23
申请人： Fumio Takeda , Hitoshi Nishimura , Natsuki Kawabata , Masakazu Aoki
发明人： Fumio Takeda , Hitoshi Nishimura , Natsuki Kawabata , Masakazu Aoki
IPC分类号： F04B39/06
CPC分类号： F04B39/062 , F04C18/16 , F04C29/0014 , F04C29/021 , F04C29/026 , F04C2210/62 , F04C2280/02
摘要： A water-injected compressor, which injects the water inside the separator 3 into the compressor and discharges the water along with compressed air into the separator and then gains condensed and separated water, has the compressor stopping and then, if staying at a stop for a predetermined duration of time without activating, becoming activated and operating for a set duration of time.
摘要翻译：注水压缩机将分离器3内的水注入压缩机，并将水与压缩空气一起排放到分离器中，然后获得冷凝和分离的水，使压缩机停止，然后如果停留在预定的持续时间，而不激活，变得激活并在一定时间内运行。

55. 发明授权

US07062060B2 Outer mirror and interphone for a vehicle 有权
标题翻译：车内外镜和对讲机
公开(公告)号：US07062060B2
公开(公告)日：2006-06-13
申请号：US10356928
申请日：2003-02-04
申请人： Masami Hosono , Masakazu Aoki , Tadashi Ejiri , Takashi Ichikawa , Terumasa Suyama , Masao Ayabe
发明人： Masami Hosono , Masakazu Aoki , Tadashi Ejiri , Takashi Ichikawa , Terumasa Suyama , Masao Ayabe
IPC分类号： H04R25/00
CPC分类号： B60R11/0217 , B60R1/12 , B60R11/0247 , B60R2001/1276 , B60R2011/004 , H04R27/00
摘要： An outer mirror and a vehicle interphone are provided for transmitting a sound to the outside from a vehicle cabin and vice versa. Sound outside the vehicle cabin is transmitted to the cabin from a microphone-loudspeaker provided in a visor cover of the outer mirror. The microphone-loudspeaker is supported on a frame having higher rigidity than the visor cover, which is mounted to a vehicle body via an electric accommodating unit and a door mirror base to promote shock resistance. The visor cover includes a sound-conducting opening in its bottom portion, and the microphone-loudspeaker is made waterproof to promote weather resistance.
摘要翻译：提供外镜和车辆对讲机，用于将声音从车厢发送到外部，反之亦然。车厢外的声音从设在外镜的遮阳板盖上的麦克风扬声器传输到车厢。麦克风扬声器被支撑在具有比遮阳板盖更高的刚性的框架上，该遮阳板通过电气容纳单元和门镜座安装到车体以促进抗冲击性。遮阳板的底部包括一个导声孔，麦克风扬声器防水，以提高耐候性。

56. 发明授权

US06833725B2 Semiconductor characteristic evaluation apparatus 有权
标题翻译：半导体特性评估装置
公开(公告)号：US06833725B2
公开(公告)日：2004-12-21
申请号：US10600800
申请日：2003-06-19
申请人： Shin-ichi Ohkawa , Masakazu Aoki
发明人： Shin-ichi Ohkawa , Masakazu Aoki
IPC分类号： G01R3102
CPC分类号： G11C29/50008 , G01R31/2884 , G01R31/30 , G11C2029/5002
摘要： On a basic measurement unit arranged in a lattice shape on a chip, a resistance measurement circuit, a capacity measurement circuit, an n-type MOS transistor measurement circuit, a p-type MOS transistor measurement circuit, and a ring oscillator measurement circuit are mounted by several tens of patterns. Each measurement circuit mounted by several tens of patterns is connected to a measurement bus to constitute a measurement bus net in accordance with measured items. Switching of connection of the measurement bus net with a measurement terminal pad is electrically controlled properly by X, Y address selection signals outputted from X, Y address decoders to X, Y address selection signal lines.
摘要翻译：在芯片上布置成格子状的基本测量单元上安装有电阻测量电路，电容测量电路，n型MOS晶体管测量电路，p型MOS晶体管测量电路和环形振荡器测量电路几十种图案。安装了数十种图案的每个测量电路都连接到测量总线，以根据测量项目构成测量总线网。通过从X，Y地址解码器输出到X，Y地址选择信号线的X，Y地址选择信号，对测量总线网络与测量端子焊盘的连接进行切换。

57. 发明授权

US06787841B2 Semiconductor element and semiconductor memory device using the same 失效
标题翻译：半导体元件和使用其的半导体存储器件
公开(公告)号：US06787841B2
公开(公告)日：2004-09-07
申请号：US10650732
申请日：2003-08-29
申请人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L2976
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , G11C2216/06 , G11C2216/08 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L27/1203 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/785 , H01L29/7888
摘要： A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.
摘要翻译：一种场效应半导体元件，其具有较少数量的元件和减小的面积，并能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。

58. 发明授权

US06754114B2 Semiconductor device having redundancy circuit 失效
标题翻译：具有冗余电路的半导体器件
公开(公告)号：US06754114B2
公开(公告)日：2004-06-22
申请号：US10401975
申请日：2003-03-31
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C700
CPC分类号： G11C29/80 , G11C29/785 , G11C29/808
摘要： A semiconductor memory is provided with a defect recovery scheme featuring a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes one or more comparing circuits having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. Each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected.
摘要翻译：半导体存储器具有冗余电路的缺陷恢复方案。存储器中的存储器阵列具有多个字线，多个位线，备用位线和多个存储器单元。冗余电路包括具有可编程元件的一个或多个比较电路，其作为用于在其中存储存在于存储器阵列中的缺陷地址的存储器。冗余电路的可编程元件可以根据多种不同类型的缺陷模式中的任何一种进行编程。冗余电路的每个比较电路将在其中输入的信息（数据），例如可能在地址多路复用系统的控制下的列和行地址与在比较电路的可编程元件中编程的信息（数据）进行比较。在此比较的基础上，进行适当的缺陷恢复。

59. 发明授权

US06696865B2 Semiconductor integrated circuit device having power reduction mechanism 失效
标题翻译：具有功率降低机构的半导体集成电路装置
公开(公告)号：US06696865B2
公开(公告)日：2004-02-24
申请号：US10283280
申请日：2002-10-30
申请人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
发明人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
IPC分类号： H03K19094
CPC分类号： H01L27/0207 , G06F1/3203 , G11C5/14 , H01L27/0218 , H03K3/356113 , H03K19/0013 , H03K19/0016 , H03K19/01721
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The substrate voltages of the transistors are set so that the threshold voltage would be varied based on the operation mode. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
摘要翻译：半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。逻辑门连接到第一电势点和第二电位点。晶体管的衬底电压被设置为使得阈值电压将基于操作模式而改变。半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值逻辑门。该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。

60. 外观设计

USD478617S1 Toner cartridge 失效
公开(公告)号：USD478617S1
公开(公告)日：2003-08-19
申请号：US29171295
申请日：2002-11-20
申请人： Hironobu Kinoshita , Naoki Yamaguchi , Masakazu Aoki
设计人： Hironobu Kinoshita , Naoki Yamaguchi , Masakazu Aoki

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式