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51. 发明授权

US08069363B2 Double data rate output latch for static RAM device has edge-triggered flip-flop to output DDR signal to synchronize with a second clock signal 有权
标题翻译：用于静态RAM器件的双数据速率输出锁存器具有边沿触发触发器以输出DDR信号以与第二时钟信号同步
公开(公告)号：US08069363B2
公开(公告)日：2011-11-29
申请号：US12543839
申请日：2009-08-19
申请人： Alan Roth , Oswald Becca , Pedro Ovalle
发明人： Alan Roth , Oswald Becca , Pedro Ovalle
IPC分类号： G06F1/12 , H03L7/00
CPC分类号： G06F5/08
摘要： A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.
摘要翻译：提出了用于将数据从输入时钟重新同步到输出时钟的同步电路。第一透明锁存器接收与输入时钟同步的数据。第二透明锁存器从第一透明锁存器接收数据，并且输出取决于延迟的输出时钟的数据，延迟的输出时钟是延迟了插入延迟的输出时钟。输出锁存器从第二透明锁存器接收数据并将数据与输出时钟同步。

52. 发明授权

US08004868B2 Method and apparatus for performing variable word width searches in a content addressable memory 有权
标题翻译：用于在内容可寻址存储器中执行可变字宽搜索的方法和装置
公开(公告)号：US08004868B2
公开(公告)日：2011-08-23
申请号：US12546554
申请日：2009-08-24
申请人： Alan Roth
发明人： Alan Roth
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/00
摘要： A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR.
摘要翻译：一种用于使用可变宽度搜索数据执行搜索操作的内容可寻址存储器（CAM），所述CAM包括多个CAM单元阵列，每个阵列耦合到相应的子搜索数据总线，所述子搜索总线被限制为形成主搜索数据总线，应用搜索数据; 接收来自相应CAM阵列的匹配线信号的选择器电路，匹配线信号表示在相关联的CAM阵列中形成的搜索和比较的结果，选择器电路响应于选择一个或多个所述匹配的模式选择信号线路输出信号被切换到优先编码器和多重匹配解算器（PE-MMR），其中在第一模式中，匹配线输出信号被切换到所述PE-MMR，并且在第二模式中，来自所选择的匹配线输出信号组阵列被切换到所述PE-MMR。

53. 发明授权

US07596710B2 Synchronization circuit and method with transparent latches 有权
标题翻译：具有透明锁存器的同步电路和方法
公开(公告)号：US07596710B2
公开(公告)日：2009-09-29
申请号：US11305433
申请日：2005-12-14
申请人： Alan Roth , Oswald Becca , Pedro Ovalle
发明人： Alan Roth , Oswald Becca , Pedro Ovalle
IPC分类号： G06F1/12 , G06F1/06
CPC分类号： G06F5/08
摘要： A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.
摘要翻译：提出了用于将数据从输入时钟重新同步到输出时钟的同步电路。第一透明锁存器接收与输入时钟同步的数据。第二透明锁存器从第一透明锁存器接收数据，并输出取决于延迟的输出时钟的数据，延迟的输出时钟是延迟了插入延迟的输出时钟。输出锁存器从第二透明锁存器接收数据并将数据与输出时钟同步。

54. 发明授权

US07478193B2 Method and apparatus for interconnecting content addressable memory devices 失效
标题翻译：用于互连内容可寻址存储器件的方法和装置
公开(公告)号：US07478193B2
公开(公告)日：2009-01-13
申请号：US11419374
申请日：2006-05-19
申请人： Oswald Becca , Alan Roth , Robert McKenzie
发明人： Oswald Becca , Alan Roth , Robert McKenzie
IPC分类号： G06F12/00
CPC分类号： G06F17/30982 , G06F13/18 , G06F13/4247 , G11C15/00
摘要： A CAM system comprising a plurality of CAM devices connected in a serial cascade arrangement, the CAMs in the cascade being connected to an adjacent CAM by a respective forwarding bus, with at most a first CAM in the cascade being connected to a receive data signals from a host controller and at most a last CAM devices being coupled to forward results back to the host controller; and a send signal generation means for supplying a SEND signal to the last CAM; the SEND signal for coordinating transfer of the search result from the last CAM to the host controller, the serial cascade arrangement minimizing the number of CAMs being connected to a common forwarding bus.
摘要翻译：一种CAM系统，包括以串联级联装置连接的多个CAM装置，级联中的CAM通过相应的转发总线连接到相邻的CAM，最多具有级联中的第一CAM连接到来自主机控制器和至多最后的CAM设备被耦合以将结果转发回主机控制器; 以及发送信号发生装置，用于向最后一个CAM提供SEND信号; 用于协调将搜索结果从最后一个CAM传送到主机控制器的SEND信号，串行级联布置使得连接到公共转发总线的CAM的数量最小化。

55. 发明授权

US07136961B2 Method and apparatus for wide word deletion in content addressable memories 有权
公开(公告)号：US07136961B2
公开(公告)日：2006-11-14
申请号：US10357270
申请日：2003-01-31
申请人： Alan Roth , Robert McKenzie , Oswald Becca
发明人： Alan Roth , Robert McKenzie , Oswald Becca
IPC分类号： G06F12/00
CPC分类号： G11C15/00 , G11C15/04
摘要： A system and method for searching and deleting segmented wide word entries in a CAM array is disclosed. A normal CAM search operation is executed to find the first word segment of a wide word. Once found, a search and delete operation is executed to find all successive word segments of the wide word, with the last word segment being marked as a deleted word segment, along a first CAM array direction. Once the last word segment is deleted, the wide word is considered to have been deleted because subsequent searches for the wide word will not find its last word segment. A purge operation is then executed along the opposite CAM array direction to delete all the word segments of the deleted wide word. Match processing circuits in each row of the CAM array can pass search results to an adjacent row above or below it to ensure that only word segments belonging to the wide word are found in the search and delete operation and deleted in the purge operation.

56. 发明申请

US20060123327A1 Method and circuit for error correction in CAM cells 失效
标题翻译： CAM单元纠错方法与电路
公开(公告)号：US20060123327A1
公开(公告)日：2006-06-08
申请号：US11313661
申请日：2005-12-22
申请人： Richard Foss , Alan Roth
发明人： Richard Foss , Alan Roth
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G06F11/1064 , G11C15/00
摘要： A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching CAM cells in the array. The method includes the following steps: a row parity bit corresponding to a parity of a first plurality of bits stored along a row of CAM cells is stored; a column parity bit corresponding to the parity of a second plurality of bits stored along a column of CAM cells is stored; a parity of the first plurality of bits is read and generated and the generated parity is compared to the stored row parity bit, if the generated and stored parity bits do not match, columns of the array are cycled through; a parity of the second plurality of bits is read and generated and the generated parity is compared to the stored column parity bit until a mismatch is indicated; and, a bit located at an intersection of the mismatched row and column is inverted if the mismatch is indicated.
摘要翻译：提供了一种用于检测和校正内容可寻址存储器（CAM）单元阵列中的错误的方法和电路。阵列包括用于从阵列中读取，写入和搜索CAM单元的字线，搜索线，位线和匹配线。该方法包括以下步骤：存储对应于沿着一组CAM单元存储的第一多个比特的奇偶校验位的行奇偶校验位; 存储与沿着CAM单元的列存储的第二多个比特的奇偶校验相对应的列奇偶校验位; 读出并产生第一多个比特的奇偶校验，并且如果生成和存储的奇偶校验位不匹配，则将生成的奇偶校验与存储的行奇偶校验位进行比较，则阵列的列循环; 读取并生成第二多个比特的奇偶校验，并将生成的奇偶校验与存储的列奇偶校验位进行比较，直到指示不匹配为止; 并且如果指示不匹配，位于错配的行和列的交点处的位被反转。

57. 发明授权

US06888731B2 Method and apparatus for replacing defective rows in a semiconductor memory array 有权
标题翻译：用于替换半导体存储器阵列中的有缺陷的行的方法和装置
公开(公告)号：US06888731B2
公开(公告)日：2005-05-03
申请号：US10306734
申请日：2002-11-29
申请人： Alan Roth , Douglas Perry , Richard Foss
发明人： Alan Roth , Douglas Perry , Richard Foss
IPC分类号： G11C15/00 , G11C29/00 , G11C15/02
CPC分类号： G11C29/848 , G11C15/00
摘要： A method for replacing a defective row in a CAM array, the array having a plurality of normal rows of cells and at least one spare row of cells, each the row being enabled by a corresponding word line signal, and having corresponding match line outputs switched to corresponding ones of a plurality of match line inputs in a match line decoder, the method comprising the steps of: (a) generating a signal indicative of the location of a defective row in the array; (b) generating a set of word line select signals for selecting ones of the plurality of normal rows; (d) using the defective row signal to switch a word line select signal of the defective row to a row adjacent the defective row and switching the adjacent row word line select signals to subsequent rows upto the at least one spare row, and (e) using the defective row signal to switch the match line input of the row adjacent the defective row to the matchline input of the defective row and switching the subsequent row match line input to the adjacent row match line input, repeating the switching for subsequent matchlines upto the matchline of the at least one spare row.
摘要翻译：一种用于替换CAM阵列中的有缺陷的行的方法，所述阵列具有多个正常的单元行和至少一个备用的单元行，每一行由相应的字线信号使能，并且具有对应的匹配线输出到匹配行解码器中的多个匹配线输入中的对应的一个，该方法包括以下步骤：（a）产生指示阵列中缺陷行的位置的信号; （b）产生用于选择多个正常行中的一个的一组字线选择信号; （d）使用缺陷行信号将缺陷行的字线选择信号切换到与缺陷行相邻的行，并将相邻行字线选择信号切换到至少一个备用行的后续行，以及（e）使用有缺陷的行信号将与缺陷行相邻的行的匹配线输入切换到缺陷行的匹配线输入，并将随后的行匹配线输入切换到相邻行匹配线输入，重复对后续匹配线的切换直到至少一个备用行的匹配线。

58. 发明授权

US06768659B2 Circuit and method for reducing power usage in a content addressable memory 有权
标题翻译：用于减少内容可寻址存储器中的功率使用的电路和方法
公开(公告)号：US06768659B2
公开(公告)日：2004-07-27
申请号：US10060100
申请日：2002-01-31
申请人： Peter Gillingham , Alan Roth
发明人： Peter Gillingham , Alan Roth
IPC分类号： G11C1500
CPC分类号： G11C15/04 , G11C15/00
摘要： A content addressable memory (CAM) including a plurality of rows, each of the rows has a plurality of matchline segments having a plurality of CAM cells coupled thereto. A circuit is provided for precharging the matchline segments to a mismatch condition. For each segment a sense circuit detects a match and in response thereto enables a discharge path in a subsequent segment, to allow matches to be detected therein. This is propagated through all segments in a row to generate a search result for the row.
摘要翻译：包括多行的内容可寻址存储器（CAM）中的每一行具有多个具有与其耦合的多个CAM单元的匹配线段。提供用于将匹配线段预充电到不匹配条件的电路。对于每个段，感测电路检测到匹配，并且响应于此，能够在随后的段中执行放电路径，以允许在其中检测到匹配。这是通过行中的所有段传播的，以生成该行的搜索结果。

59. 发明授权

US06580652B2 Priority encoder circuit and method for content addressable memory 失效
标题翻译：优先级编码器电路和内容可寻址存储器的方法
公开(公告)号：US06580652B2
公开(公告)日：2003-06-17
申请号：US10291645
申请日：2002-11-12
申请人： Richard C. Foss , Alan Roth
发明人： Richard C. Foss , Alan Roth
IPC分类号： G11C700
CPC分类号： G06F7/74 , G11C15/00
摘要： A circuit selects a highest priority signal from a plurality of input signals. The circuit comprises the following components. A plurality of serially coupled input blocks, each of which are coupled to a corresponding one of a plurality of input lines for receiving respective ones of the input signals and providing corresponding output signals. A pre-charging device coupled between a first supply voltage terminal and a first one of the serially coupled input blocks. The pre-charging device couples the supply voltage to the first one of the serially coupled input blocks in response to a clock pulse signal transition. An activation device coupled between a second supply voltage terminal and a last one of the serially coupled input blocks. The activation device couples the second supply voltage to the last one of the serially coupled input blocks in response to an activation signal transition.
摘要翻译：电路从多个输入信号中选择最高优先级的信号。该电路包括以下部件。多个串联的输入块，每个输入块耦合到多个输入线中的相应一个输入线，用于接收相应的输入信号并提供对应的输出信号。耦合在第一电源电压端子和串联耦合输入块中的第一电源端子之间的预充电装置。预充电装置响应于时钟脉冲信号转换将电源电压耦合到串联耦合的输入块中的第一个。耦合在第二电源电压端子和串联耦合的输入块中的最后一个的激活装置。激活装置响应于激活信号转换将第二电源电压耦合到串行耦合输入块中的最后一个。

60. 发明授权

US06559544B1 Programmable interconnect for semiconductor devices 失效
标题翻译：用于半导体器件的可编程互连
公开(公告)号：US06559544B1
公开(公告)日：2003-05-06
申请号：US10107821
申请日：2002-03-28
申请人： Alan Roth , Curtis Richardson
发明人： Alan Roth , Curtis Richardson
IPC分类号： H01L2940
CPC分类号： H01L23/525 , H01L21/76892 , H01L2924/0002 , H01L2924/00
摘要： A structure for selectively programming interconnections between an input contact and an output contact segment in a multilayer semiconductor, comprising a first group of metal segments each being formed on successive layers of the semiconductor and being interconnected by vias, the first group including the output contact segment; a second group of metal segments each formed on successive layers of the semiconductor and being interconnected by vias, the second group including the input contact segment; and means for connecting a metal segment in the first group to a metal segment in a corresponding layer in the second group, thereby connecting the input contact to the output contact.
摘要翻译：一种用于选择性地编程在多层半导体中的输入触点和输出触点段之间的互连的结构，包括第一组金属段，每个金属段都形成在半导体的连续层上并且被通孔互连，第一组包括输出触点段 ; 第二组金属片，每个形成在所述半导体的连续层上并且通过通孔互连，所述第二组包括所述输入触点段; 以及用于将第一组中的金属段连接到第二组中相应层中的金属段的装置，由此将输入触点连接到输出触点。

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