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1. 发明授权

US06768659B2 Circuit and method for reducing power usage in a content addressable memory 有权
标题翻译：用于减少内容可寻址存储器中的功率使用的电路和方法
公开(公告)号：US06768659B2
公开(公告)日：2004-07-27
申请号：US10060100
申请日：2002-01-31
申请人： Peter Gillingham , Alan Roth
发明人： Peter Gillingham , Alan Roth
IPC分类号： G11C1500
CPC分类号： G11C15/04 , G11C15/00
摘要： A content addressable memory (CAM) including a plurality of rows, each of the rows has a plurality of matchline segments having a plurality of CAM cells coupled thereto. A circuit is provided for precharging the matchline segments to a mismatch condition. For each segment a sense circuit detects a match and in response thereto enables a discharge path in a subsequent segment, to allow matches to be detected therein. This is propagated through all segments in a row to generate a search result for the row.
摘要翻译：包括多行的内容可寻址存储器（CAM）中的每一行具有多个具有与其耦合的多个CAM单元的匹配线段。提供用于将匹配线段预充电到不匹配条件的电路。对于每个段，感测电路检测到匹配，并且响应于此，能够在随后的段中执行放电路径，以允许在其中检测到匹配。这是通过行中的所有段传播的，以生成该行的搜索结果。

2. 发明授权

US08781053B2 Clock reproducing and timing method in a system having a plurality of devices 有权
标题翻译：具有多个装置的系统中的时钟再现和定时方法
公开(公告)号：US08781053B2
公开(公告)日：2014-07-15
申请号：US12168091
申请日：2008-07-04
申请人： Hong Beom Pyeon , Peter Gillingham
发明人： Hong Beom Pyeon , Peter Gillingham
IPC分类号： H03D3/24
CPC分类号： H04L7/0331 , G06F13/1689 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2225/06562 , Y02D10/14 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A system includes a memory controller and a plurality of semiconductor devices that are series-connected. Each of the devices has memory core for storing data. The memory controller provides a clock signal for synchronizing the operations of the devices. Each device includes a phase-locked loop (PLL) that is selectively enabled or disabled by a PLL enable signal. In each group, the PLLs of a selected number of devices are enabled by PLL enable signals and the other devices are disabled. The enabled PLL provides a plurality of reproduced clock signals with a phase shift of a multiple of 90° in response to an input clock signal. The data transfer is synchronized with at least one of the reproduced clock signals. In the devices of disabled PLLs, the data transfer is synchronized with the input clock signal. The enabled PLL and disabled PLL cause the devices to be the source and the common synchronous clocking, respectively. The devices can be grouped. The devices of one group can be structured by multiple chip packages.
摘要翻译：系统包括存储器控制器和串联连接的多个半导体器件。每个设备具有用于存储数据的存储器核心。存储器控制器提供用于同步器件的操作的时钟信号。每个器件包括被PLL使能信号选择性地使能或禁止的锁相环（PLL）。在每个组中，选定数量的器件的PLL通过PLL使能信号使能，其他器件被禁止。所启用的PLL响应于输入时钟信号提供多个具有90°的倍数的相移的再现时钟信号。数据传输与再现的时钟信号中的至少一个同步。在禁用PLL的器件中，数据传输与输入时钟信号同步。使能的PLL和禁用的PLL分别使器件成为源和公共同步时钟。设备可以分组。一组的器件可以由多个芯片封装构成。

3. 发明授权

US08471591B2 Termination circuit for on-die termination 失效
标题翻译：端接终端电路
公开(公告)号：US08471591B2
公开(公告)日：2013-06-25
申请号：US13284338
申请日：2011-10-28
申请人： Peter Gillingham
发明人： Peter Gillingham
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K3/012 , H01L2924/0002 , H03K19/0005 , H03K19/00361 , H04L25/0278 , H01L2924/00
摘要： In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.
摘要翻译：在具有连接到内部部分的端子的半导体器件中，用于为器件的端子提供管芯端接的终端电路。终端电路包括多个晶体管，其包括连接在端子和电源之间的至少一个NMOS晶体管和至少一个PMOS晶体管; 以及控制电路，用于以相应的NMOS栅极电压驱动每个NMOS晶体管的栅极并且用相应的PMOS栅极电压驱动每个PMOS晶体管的栅极，所述控制电路被配置为控制NMOS和PMOS栅极电压，以便当使能片上端接时，将晶体管置于欧姆区域。电源提供小于每个所述NMOS栅极电压并大于每个所述PMOS栅极电压的电压。

4. 发明申请

US20110199820A1 NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES 有权
标题翻译：具有多个外部电源的非易失性半导体存储器
公开(公告)号：US20110199820A1
公开(公告)日：2011-08-18
申请号：US13096874
申请日：2011-04-28
申请人： Jin-Ki Kim , Peter Gillingham
发明人： Jin-Ki Kim , Peter Gillingham
IPC分类号： G11C16/30 , G11C16/06
CPC分类号： G11C16/30 , G11C5/14 , G11C5/143 , G11C5/145 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26
摘要： A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.
摘要翻译：存储器件包括诸如用于存储数据的闪存的核心存储器。存储器件包括用于接收用于为闪速存储器供电的第一电压的第一电源输入。另外，存储器件包括用于接收第二电压的第二电源输入。存储器件包括被配置为接收第二电压并导出一个或多个内部电压的电源管理电路。电源管理电路将内部电压提供或传送到闪存。由功率管理电路（例如，电压转换器电路）产生并提供给核心存储器的不同的内部电压使得诸如针对核心存储器中的单元的读取/编程/擦除的操作。

5. 发明申请

US20100110794A1 NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES 有权
标题翻译：具有多个外部电源的非易失性半导体存储器
公开(公告)号：US20100110794A1
公开(公告)日：2010-05-06
申请号：US12617459
申请日：2009-11-12
申请人： Jin-Ki Kim , Peter Gillingham
发明人： Jin-Ki Kim , Peter Gillingham
IPC分类号： G11C16/04 , G11C5/02 , G11C5/14
CPC分类号： G11C16/30 , G11C5/14 , G11C5/143 , G11C5/145 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26
摘要： A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.
摘要翻译：存储器件包括诸如用于存储数据的闪存的核心存储器。存储器件包括用于接收用于为闪速存储器供电的第一电压的第一电源输入。另外，存储器件包括用于接收第二电压的第二电源输入。存储器件包括被配置为接收第二电压并导出一个或多个内部电压的电源管理电路。电源管理电路将内部电压提供或传送到闪存。由功率管理电路（例如，电压转换器电路）产生并提供给核心存储器的不同的内部电压使得诸如针对核心存储器中的单元的读取/编程/擦除的操作。

6. 发明申请

US20090154629A1 CLOCK REPRODUCING AND TIMING METHOD IN A SYSTEM HAVING A PLURALITY OF DEVICES 有权
标题翻译：具有多种设备的系统中的时钟再现和时序方法
公开(公告)号：US20090154629A1
公开(公告)日：2009-06-18
申请号：US12168091
申请日：2008-07-04
申请人： Hong Beom PYEON , Peter Gillingham
发明人： Hong Beom PYEON , Peter Gillingham
IPC分类号： H03D3/24
CPC分类号： H04L7/0331 , G06F13/1689 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2225/06562 , Y02D10/14 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A system includes a memory controller and a plurality of semiconductor devices that are series-connected. Each of the devices has memory core for storing data. The memory controller provides a clock signal for synchronizing the operations of the devices. Each device includes a phase-locked loop (PLL) that is selectively enabled or disabled by a PLL enable signal. In each group, the PLLs of a selected number of devices are enabled by PLL enable signals and the other devices are disabled. The enabled PLL provides a plurality of reproduced clock signals with a phase shift of a multiple of 90° in response to an input clock signal. The data transfer is synchronized with at least one of the reproduced clock signals. In the devices of disabled PLLs, the data transfer is synchronized with the input clock signal. The enabled PLL and disabled PLL cause the devices to be the source and the common synchronous clocking, respectively. The devices can be grouped. The devices of one group can be structured by multiple chip packages.
摘要翻译：系统包括存储器控制器和串联连接的多个半导体器件。每个设备具有用于存储数据的存储器核心。存储器控制器提供用于同步器件的操作的时钟信号。每个器件包括被PLL使能信号选择性地使能或禁止的锁相环（PLL）。在每个组中，选定数量的器件的PLL通过PLL使能信号使能，其他器件被禁止。所启用的PLL响应于输入时钟信号提供多个具有90°的倍数的相移的再现时钟信号。数据传输与再现的时钟信号中的至少一个同步。在禁用PLL的器件中，数据传输与输入时钟信号同步。使能的PLL和禁用的PLL分别使器件成为源和公共同步时钟。设备可以分组。一组的器件可以由多个芯片封装构成。

7. 发明授权

US07120040B2 Ternary CAM cell for reduced matchline capacitance 有权
标题翻译：三元CAM单元，用于减少匹配线电容
公开(公告)号：US07120040B2
公开(公告)日：2006-10-10
申请号：US10856783
申请日：2004-06-01
申请人： Douglas Perry , Peter Gillingham
发明人： Douglas Perry , Peter Gillingham
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A ternary content addressable memory (CAM) cell is disclosed for providing reduced or minimized matchline (ML) capacitance and for increasing current between matchline and tail-line in the case of a mismatch. The speed of a CAM cell is generally inversely proportional to its ML capacitance, and proportional to the current. Conventional ternary CAM cells have many matchline transistors, each contributing to the matchline capacitance. Embodiments of the present invention have a single matchline transistor between a matchline and a ground line, or tail-line, of the CAM cell. The single matchline transistor couples the matchline to the tail-line in response to a discharge signal from a compare circuit. The compare circuit can be divided into a pull-up section for driving a gate voltage level control node and a discharge section for discharging the gate voltage level control node, the discharge signal being provided at the gate voltage level control node.
摘要翻译：公开了三元内容可寻址存储器（CAM）单元，用于在不匹配的情况下提供缩减或最小化匹配线（ML）电容并用于增加匹配线和尾线之间的电流。 CAM单元的速度通常与其ML电容成反比，并且与电流成比例。传统的三元CAM单元具有许多匹配线晶体管，每个有助于匹配线电容。本发明的实施例在CAM单元的匹配线和接地线或尾线之间具有单个匹配线晶体管。单个匹配线晶体管响应于来自比较电路的放电信号将匹配线耦合到尾线。比较电路可以分为用于驱动栅极电压电平控制节点的上拉部分和用于放电栅极电压电平控制节点的放电部分，放电信号被提供在栅极电压电平控制节点处。

8. 发明申请

US20050081012A1 High bandwidth memory interface 有权
标题翻译：高带宽存储器接口
公开(公告)号：US20050081012A1
公开(公告)日：2005-04-14
申请号：US10919491
申请日：2004-08-17
申请人： Peter Gillingham , Bruce Millar
发明人： Peter Gillingham , Bruce Millar
IPC分类号： G06F13/42 , G06F12/00
CPC分类号： G11C5/06 , G06F1/12 , G06F13/1689 , G06F13/4234 , G06F13/4243 , G11C8/18 , Y02D10/14 , Y02D10/151
摘要： This invention describes an improved high bandwidth chip-to-chip interface for memory devices, which is capable of operating at higher speeds, while maintaining error free data transmission, consuming lower power, and supporting more load. Accordingly, the invention provides a memory subsystem comprising at least two semiconductor devices; a main bus containing a plurality of bus lines for carrying substantially all data and command information needed by the devices, the semiconductor devices including at least one memory device connected in parallel to the bus; the bus lines including respective row command lines and column command lines; a clock generator for coupling to a clock line, the devices including clock inputs for coupling to the clock line; and the devices including programmable delay elements coupled to the clock inputs to delay the clock edges for setting an input data sampling time of the memory device.
摘要翻译：本发明描述了一种用于存储器件的改进的高带宽芯片到芯片接口，其能够以更高的速度运行，同时保持无错误的数据传输，消耗较低的功率并支持更多的负载。因此，本发明提供一种包括至少两个半导体器件的存储器子系统; 主总线，其包含用于承载所述设备所需的基本上所有数据和命令信息的多条总线，所述半导体器件包括与所述总线并联连接的至少一个存储器件; 总线包括各行命令行和列命令行; 用于耦合到时钟线的时钟发生器，所述器件包括用于耦合到时钟线的时钟输入; 并且所述设备包括耦合到所述时钟输入的可编程延迟元件，以延迟所述时钟边沿，以设置所述存储器件的输入数据采样时间。

9. 发明授权

US06182257B2 BIST memory test system 失效
标题翻译： BIST内存测试系统
公开(公告)号：US06182257B2
公开(公告)日：2001-01-30
申请号：US09000968
申请日：1997-12-30
申请人： Peter Gillingham
发明人： Peter Gillingham
IPC分类号： G01R3128
CPC分类号： G11C29/72 , G11C11/401 , G11C29/08 , G11C29/14 , G11C29/50 , G11C29/789 , G11C2029/5004
摘要： A semiconductor device having a self test circuit including an embedded dynamic random access memory array for storing data, a self test controller for internally generating test data patterns and expected resulting data and for comparing the expected resulting data with actual resulting data, test interface circuitry for loading the test data patterns into the memory and reading back the actual resulting data from the memory, means for selectively programming a voltage level to be applied to a selected cell plate of the memory according to predetermined test requirements and means for storing an address of a defective memory cell. In addition, the semiconductor device includes means for repairing a defective memory row or column in response to a signal received from the self test controller.
摘要翻译：一种具有自检电路的半导体器件，包括用于存储数据的嵌入式动态随机存取存储器阵列，用于内部产生测试数据模式和期望的结果数据并用于将预期结果数据与实际产生的数据进行比较的自测试控制器，用于将测试数据模式加载到存储器中并从存储器读回实际的结果数据，用于根据预定的测试要求选择性地编程要施加到存储器的所选单元板的电压电平的装置，以及用于存储有缺陷的存储单元。此外，半导体器件包括用于响应于从自测试控制器接收到的信号来修复有缺陷的存储器行或列的装置。

10. 发明授权

US4751666A Switched capacitor finite impulse response filter 失效
标题翻译：开关电容有限脉冲响应滤波器
公开(公告)号：US4751666A
公开(公告)日：1988-06-14
申请号：US783559
申请日：1985-10-03
申请人： Peter Gillingham
发明人： Peter Gillingham
IPC分类号： H03H15/00 , H03H17/06 , H03H19/00 , H03H17/02
CPC分类号： H03H17/06 , H03H19/004
摘要： A symmetric finite impulse response filter for receiving a digital input signal and generates a filtered analog output signal for application to a balanced line, such as a tip and ring lead pair. Logic levels of predetermined symmetrical bit pairs of the digital input signal are detected and in response, predetermined corresponding capacitors are selectively switched between bias and reference voltages, thereby charging predetermined voltages proportional to the capacitances of the capacitors. The predetermined voltages are summed in an operational amplifier which, in response produces a filtered analog output signal. Individual capacitors are utilized for realizing each pair of symmetrical coefficients of the filter transfer function, resulting in considerable economy of size. A switched capacitor implementation results in high speed performance, simple design and low cost.
摘要翻译：对称有限脉冲响应滤波器，用于接收数字输入信号并产生滤波的模拟输出信号，以应用于平衡线路，例如尖端和环形引线对。检测数字输入信号的预定对称比特对的逻辑电平，并且作为响应，在偏置电压和参考电压之间有选择地切换预定的对应电容器，从而对与电容器的电容成比例的预定电压进行充电。预定电压在运算放大器中相加，运算放大器响应产生经滤波的模拟输出信号。单个电容器用于实现滤波器传递函数的每对对称系数，从而导致相当大的经济性。开关电容器实现高速性能，设计简单，成本低。

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