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1. 发明申请

US20130082668A1 SINGLE-INDUCTOR MULTIPLE-OUTPUT DC TO DC CONVERTER 有权
标题翻译：单电感器多路输出直流到直流转换器
公开(公告)号：US20130082668A1
公开(公告)日：2013-04-04
申请号：US13340746
申请日：2011-12-30
申请人： Chien-Chung Tseng , Eric Soenen , Alan Roth , Justin Shi
发明人： Chien-Chung Tseng , Eric Soenen , Alan Roth , Justin Shi
IPC分类号： G05F1/577
CPC分类号： H02M3/158 , H02M2001/009
摘要： A DC to DC converter includes a switching circuit and a controller. The switching circuit includes an inductor coupled to first and second voltage supply nodes and to a plurality of output loads. The controller is configured to monitor a current through the inductor and to selectively couple the inductor to each of the plurality of output loads such that at least one of the following criteria is met: 1) an average current through the inductor is minimized for the particular output loads coupled to the switching circuit, or 2) minimize a number of times the switching circuit is switched during a charging period for the particular output loads coupled to the switching circuit.
摘要翻译： DC-DC转换器包括开关电路和控制器。开关电路包括耦合到第一和第二电压供应节点和耦合到多个输出负载的电感器。控制器被配置为监测通过电感器的电流并且选择性地将电感器耦合到多个输出负载中的每一个，使得满足以下标准中的至少一个：1）通过电感器的平均电流对于特定的耦合到开关电路的输出负载，或2）在耦合到开关电路的特定输出负载的充电周期期间最小化开关电路切换的次数。

2. 发明申请

US20110089916A1 LDO REGULATORS FOR INTEGRATED APPLICATIONS 有权
标题翻译：集成应用的LDO调节器
公开(公告)号：US20110089916A1
公开(公告)日：2011-04-21
申请号：US12857092
申请日：2010-08-16
申请人： Eric Soenen , Alan Roth , Justin Shi , Ying-Chih Hsu , Guang-Cheng Wang , Wen-Shen Chou
发明人： Eric Soenen , Alan Roth , Justin Shi , Ying-Chih Hsu , Guang-Cheng Wang , Wen-Shen Chou
IPC分类号： G05F1/10
CPC分类号： G05F1/575 , H02M3/07 , H02M2001/0045
摘要： Embodiments of the invention are related to LDO regulators. In an embodiment, an amplifier drives the gate of a master source follower and of at least one slave source follower to form an LDO regulator. In an alternative embodiment, a charge pump drives the master source follower to form the regulator. Additional slave source followers may be used in conjunction with the charge pump and the master source follower to improve the regulator performance. Other embodiments are also disclosed.
摘要翻译：本发明的实施例涉及LDO调节器。在一个实施例中，放大器驱动主源跟随器的栅极和至少一个从源极跟随器的栅极以形成LDO调节器。在替代实施例中，电荷泵驱动主源极跟随器以形成调节器。附加的从源跟随器可以与电荷泵和主源极跟随器一起使用，以改善调节器的性能。还公开了其他实施例。

3. 发明申请

US20110006844A1 Class D Amplifier Control Circuit and Method 有权
标题翻译： D类放大器控制电路及方法
公开(公告)号：US20110006844A1
公开(公告)日：2011-01-13
申请号：US12858310
申请日：2010-08-17
申请人： Eric Soenen , Alan Roth , Justin Shi , Martin Kinyua
发明人： Eric Soenen , Alan Roth , Justin Shi , Martin Kinyua
IPC分类号： H03F3/217
CPC分类号： H03F3/2173
摘要： Circuit and method for a Class D amplifier. In one exemplary embodiment, an audio amplifier is disclosed. A closed loop configuration for driving high and low side driver transistors is provided, each circuit is compatible with advanced sub micron semiconductor processes. The analog time varying input is coupled to one input of a sigma delta analog to digital converter. A feedback signal from the output is also input to the analog to digital converter. A bit stream is output by the analog to digital converter. A decimator receives this bit stream and downconverts the samples to digital values at a lower frequency. A digital filter with adaptable coefficients is used to filter that signal and a digital pulse width modulator then develops an analog differential PWM signal. A predriver inputs the PWM signal and derives the output gating signals to control the high and low side drivers of a Class D amplifier.
摘要翻译： D类放大器的电路和方法。在一个示例性实施例中，公开了一种音频放大器。提供用于驱动高侧和低侧驱动晶体管的闭环配置，每个电路与先进的亚微米半导体工艺兼容。模拟时变输入耦合到Σ-Δ模数转换器的一个输入端。来自输出的反馈信号也被输入到模数转换器。位流由模数转换器输出。抽取器接收该位流，并以较低的频率将样本下变频为数字值。使用具有适应系数的数字滤波器来对该信号进行滤波，并且数字脉宽调制器然后开发模拟差分PWM信号。预驱动器输入PWM信号并导出输出门控信号以控制D类放大器的高侧和低侧驱动器。

4. 发明授权

US07834604B2 Digital control of power converters 有权
标题翻译：电源转换器的数字控制
公开(公告)号：US07834604B2
公开(公告)日：2010-11-16
申请号：US12197790
申请日：2008-08-25
申请人： Eric Soenen , Alan Roth , Martin Kinyua , Justin Shi
发明人： Eric Soenen , Alan Roth , Martin Kinyua , Justin Shi
IPC分类号： G05F1/40
CPC分类号： H02M3/1588 , H02M2001/0012 , Y02B70/1466
摘要： A system and method for controlling a power converter is presented. An embodiment comprises an analog differential circuit connected to an analog-to-digital converter, and comparing the digital error signal to at least a first threshold value. If the digital error signal is less than the first threshold value, a pulse is generated to control the power converter. Another embodiment includes multiple thresholds that may be compared against the digital error signal.
摘要翻译：提出了一种用于控制功率转换器的系统和方法。实施例包括连接到模拟 - 数字转换器的模拟差分电路，并将数字误差信号与至少第一阈值进行比较。如果数字误差信号小于第一阈值，则产生脉冲以控制功率转换器。另一实施例包括可与数字误差信号进行比较的多个阈值。

5. 发明申请

US20100045376A1 CLASS D AMPLIFIER CONTROL CIRCUIT AND METHOD 审中-公开
标题翻译：等级放大器控制电路和方法
公开(公告)号：US20100045376A1
公开(公告)日：2010-02-25
申请号：US12197967
申请日：2008-08-25
申请人： Eric Soenen , Alan Roth , Justin Shi
发明人： Eric Soenen , Alan Roth , Justin Shi
IPC分类号： H03F3/217
CPC分类号： H03F3/2173
摘要： Circuit and method for a Class D amplifier. In one exemplary embodiment, an audio amplifier is disclosed. A closed loop configuration for driving high and low side driver transistors is provided, each circuit is compatible with advanced sub micron semiconductor processes. The analog time varying input is coupled to one input of a sigma delta analog to digital converter. A feedback signal from the output is also input to the analog to digital converter. A bit stream is output by the analog to digital converter. A decimator receives this bit stream and downconverts the samples to digital values at a lower frequency. A digital filter with adaptable coefficients is used to filter that signal and a digital pulse width modulator then develops an analog differential PWM signal. A predriver inputs the PWM signal and derives the output gating signals to control the high and low side drivers of a Class D amplifier.
摘要翻译： D类放大器的电路和方法。在一个示例性实施例中，公开了一种音频放大器。提供用于驱动高侧和低侧驱动晶体管的闭环配置，每个电路与先进的亚微米半导体工艺兼容。模拟时变输入耦合到Σ-Δ模数转换器的一个输入端。来自输出的反馈信号也被输入到模数转换器。位流由模数转换器输出。抽取器接收该位流，并以较低的频率将样本下变频为数字值。使用具有适应系数的数字滤波器来对该信号进行滤波，并且数字脉宽调制器然后开发模拟差分PWM信号。预驱动器输入PWM信号并导出输出门控信号以控制D类放大器的高侧和低侧驱动器。

6. 发明申请

US20100033216A1 SYNCHRONIZATION CIRCUIT AND METHOD WITH TRANSPARENT LATCHES 有权
标题翻译：同步电路的同步电路和方法
公开(公告)号：US20100033216A1
公开(公告)日：2010-02-11
申请号：US12543839
申请日：2009-08-19
申请人： Alan Roth , Oswald Becca , Pedro Ovalle
发明人： Alan Roth , Oswald Becca , Pedro Ovalle
IPC分类号： H03L7/00
CPC分类号： G06F5/08
摘要： A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.
摘要翻译：提出了用于将数据从输入时钟重新同步到输出时钟的同步电路。第一透明锁存器接收与输入时钟同步的数据。第二透明锁存器从第一透明锁存器接收数据，并输出取决于延迟的输出时钟的数据，延迟的输出时钟是延迟了插入延迟的输出时钟。输出锁存器从第二透明锁存器接收数据并将数据与输出时钟同步。

7. 发明授权

US07558909B2 Method and apparatus for wide word deletion in content addressable memories 有权
标题翻译：内容可寻址存储器中用于宽字删除的方法和装置
公开(公告)号：US07558909B2
公开(公告)日：2009-07-07
申请号：US11548766
申请日：2006-10-12
申请人： Alan Roth , Robert McKenzie , Oswald Becca
发明人： Alan Roth , Robert McKenzie , Oswald Becca
IPC分类号： G06F12/00
CPC分类号： G11C15/00 , G11C15/04
摘要： A system and method for searching and deleting segmented wide word entries in a CAM array is disclosed. A normal CAM search operation is executed to find the first word segment of a wide word. Once found, a search and delete operation is executed to find all successive word segments of the wide word, with the last word segment being marked as a deleted word segment, along a first CAM array direction. Once the last word segment is deleted, the wide word is considered to have been deleted because subsequent searches for the wide word will not find its last word segment. A purge operation is then executed along the opposite CAM array direction to delete all the word segments of the deleted wide word. Match processing circuits in each row of the CAM array can pass search results to an adjacent row above or below it to ensure that only word segments belonging to the wide word are found in the search and delete operation and deleted in the purge operation.
摘要翻译：公开了一种用于搜索和删除CAM阵列中的分段宽字条目的系统和方法。执行正常的CAM搜索操作以找到宽字的第一字段。一旦找到，执行搜索和删除操作，以沿着第一CAM阵列方向找到宽字的所有连续字段，其中最后一个字段被标记为删除的字段。一旦最后一个字段被删除，宽字被认为已被删除，因为后续搜索宽字不会找到其最后一个字段。然后沿着相反的CAM阵列方向执行清除操作，以删除所删除的宽字的所有字段。 CAM阵列的每一行中的匹配处理电路可以将搜索结果传递到其上方或下方的相邻行，以确保在搜索和删除操作中仅找到属于宽字的字段，并在清除操作中删除。

8. 发明申请

US20070008759A1 METHOD AND APPARATUS FOR INTERCONNECTING CONTENT ADDRESSABLE MEMORY DEVICES 失效
标题翻译：用于互连内部可寻址存储器件的方法和装置
公开(公告)号：US20070008759A1
公开(公告)日：2007-01-11
申请号：US11419374
申请日：2006-05-19
申请人： Oswald Becca , Alan Roth , Robert McKenzie
发明人： Oswald Becca , Alan Roth , Robert McKenzie
IPC分类号： G11C15/00
CPC分类号： G06F17/30982 , G06F13/18 , G06F13/4247 , G11C15/00
摘要： A CAM system comprising a plurality of CAM devices connected in a serial cascade arrangement, the CAMs in the cascade being connected to an adjacent CAM by a respective forwarding bus, with at most a first CAM in the cascade being connected to a receive data signals from a host controller and at most a last CAM devices being coupled to forward results back to the host controller; and a send signal generation means for supplying a SEND signal to the last CAM; the SEND signal for coordinating transfer of the search result from the last CAM to the host controller, the serial cascade arrangement minimizing the number of CAMs being connected to a common forwarding bus.
摘要翻译：一种CAM系统，包括以串联级联装置连接的多个CAM装置，级联中的CAM通过相应的转发总线连接到相邻的CAM，最多具有级联中的第一CAM连接到来自主机控制器和至多最后的CAM设备被耦合以将结果转发回主机控制器; 以及发送信号发生装置，用于向最后一个CAM提供SEND信号; 用于协调将搜索结果从最后一个CAM传送到主机控制器的SEND信号，串行级联布置使得连接到公共转发总线的CAM的数量最小化。

9. 发明申请

US20060103439A1 Synchronization circuit and method with transparent latches 有权
公开(公告)号：US20060103439A1
公开(公告)日：2006-05-18
申请号：US11305433
申请日：2005-12-14
申请人： Alan Roth , Oswald Becca , Pedro Ovalle
发明人： Alan Roth , Oswald Becca , Pedro Ovalle
IPC分类号： H03L7/06
CPC分类号： G06F5/08
摘要： A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

10. 发明授权

US09530761B2 Package systems including passive electrical components 有权
标题翻译：封装系统包括无源电器元件
公开(公告)号：US09530761B2
公开(公告)日：2016-12-27
申请号：US13597973
申请日：2012-08-29
申请人： Alan Roth , Eric Soenen , Chaohao Wang
发明人： Alan Roth , Eric Soenen , Chaohao Wang
IPC分类号： H05K7/00 , H01L25/16 , H05K1/18 , H01L23/00
CPC分类号： H02M3/158 , H01L23/5226 , H01L24/05 , H01L24/29 , H01L24/45 , H01L24/48 , H01L25/16 , H01L28/10 , H01L28/40 , H01L2224/05025 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/29025 , H01L2224/2919 , H01L2224/32265 , H01L2224/4502 , H01L2224/45111 , H01L2224/45116 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48265 , H01L2924/00014 , H01L2924/01047 , H01L2924/0479 , H01L2924/048 , H01L2924/04941 , H01L2924/04953 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/10329 , H01L2924/10331 , H01L2924/10332 , H01L2924/10333 , H01L2924/10335 , H01L2924/10337 , H01L2924/10339 , H01L2924/10342 , H01L2924/10351 , H01L2924/1205 , H01L2924/1206 , H01L2924/1207 , H01L2924/14252 , H01L2924/1427 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H05K1/111 , H05K1/181 , H05K1/185 , H05K2201/10015 , H05K2201/10022 , H05K2201/1003 , H05K2201/10166 , Y02P70/611 , H01L2224/45099 , H01L2924/00
摘要： A package system includes at least one active circuitry disposed over a substrate. A passivation structure is disposed over the at least one active circuitry. The passivation structure has at least one opening that is configured to expose at least one first electrical pad. At least one passive electrical component is disposed over the passivation structure. The at least one passive electrical component is electrically coupled with the at least one first electrical pad.
摘要翻译：封装系统包括设置在衬底上的至少一个有源电路。钝化结构设置在至少一个有源电路上。钝化结构具有至少一个开口，其被配置为暴露至少一个第一电垫。在钝化结构上方设置至少一个无源电组件。所述至少一个无源电部件与所述至少一个第一电焊盘电耦合。

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