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1. 发明授权

US06888731B2 Method and apparatus for replacing defective rows in a semiconductor memory array 有权
标题翻译：用于替换半导体存储器阵列中的有缺陷的行的方法和装置
公开(公告)号：US06888731B2
公开(公告)日：2005-05-03
申请号：US10306734
申请日：2002-11-29
申请人： Alan Roth , Douglas Perry , Richard Foss
发明人： Alan Roth , Douglas Perry , Richard Foss
IPC分类号： G11C15/00 , G11C29/00 , G11C15/02
CPC分类号： G11C29/848 , G11C15/00
摘要： A method for replacing a defective row in a CAM array, the array having a plurality of normal rows of cells and at least one spare row of cells, each the row being enabled by a corresponding word line signal, and having corresponding match line outputs switched to corresponding ones of a plurality of match line inputs in a match line decoder, the method comprising the steps of: (a) generating a signal indicative of the location of a defective row in the array; (b) generating a set of word line select signals for selecting ones of the plurality of normal rows; (d) using the defective row signal to switch a word line select signal of the defective row to a row adjacent the defective row and switching the adjacent row word line select signals to subsequent rows upto the at least one spare row, and (e) using the defective row signal to switch the match line input of the row adjacent the defective row to the matchline input of the defective row and switching the subsequent row match line input to the adjacent row match line input, repeating the switching for subsequent matchlines upto the matchline of the at least one spare row.
摘要翻译：一种用于替换CAM阵列中的有缺陷的行的方法，所述阵列具有多个正常的单元行和至少一个备用的单元行，每一行由相应的字线信号使能，并且具有对应的匹配线输出到匹配行解码器中的多个匹配线输入中的对应的一个，该方法包括以下步骤：（a）产生指示阵列中缺陷行的位置的信号; （b）产生用于选择多个正常行中的一个的一组字线选择信号; （d）使用缺陷行信号将缺陷行的字线选择信号切换到与缺陷行相邻的行，并将相邻行字线选择信号切换到至少一个备用行的后续行，以及（e）使用有缺陷的行信号将与缺陷行相邻的行的匹配线输入切换到缺陷行的匹配线输入，并将随后的行匹配线输入切换到相邻行匹配线输入，重复对后续匹配线的切换直到至少一个备用行的匹配线。

2. 发明授权

US07350137B2 Method and circuit for error correction in CAM cells 失效
标题翻译： CAM单元纠错方法与电路
公开(公告)号：US07350137B2
公开(公告)日：2008-03-25
申请号：US11313661
申请日：2005-12-22
申请人： Richard Foss , Alan Roth
发明人： Richard Foss , Alan Roth
IPC分类号： G11C29/00
CPC分类号： G06F11/1064 , G11C15/00
摘要： A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching CAM cells in the array. The method includes the following steps: a row parity bit corresponding to a parity of a first plurality of bits stored along a row of CAM cells is stored; a column parity bit corresponding to the parity of a second plurality of bits stored along a column of CAM cells is stored; a parity of the first plurality of bits is read and generated and the generated parity is compared to the stored row parity bit, if the generated and stored parity bits do not match, columns of the array are cycled through; a parity of the second plurality of bits is read and generated and the generated parity is compared to the stored column parity bit until a mismatch is indicated; and, a bit located at an intersection of the mismatched row and column is inverted if the mismatch is indicated.
摘要翻译：提供了一种用于检测和校正内容可寻址存储器（CAM）单元阵列中的错误的方法和电路。阵列包括用于从阵列中读取，写入和搜索CAM单元的字线，搜索线，位线和匹配线。该方法包括以下步骤：存储对应于沿着一组CAM单元存储的第一多个比特的奇偶校验位的行奇偶校验位; 存储与沿着CAM单元的列存储的第二多个比特的奇偶校验相对应的列奇偶校验位; 读出并产生第一多个比特的奇偶校验，并且如果生成和存储的奇偶校验位不匹配，则将生成的奇偶校验与存储的行奇偶校验位进行比较，则阵列的列循环; 读取并生成第二多个比特的奇偶校验，并将生成的奇偶校验与存储的列奇偶校验位进行比较，直到指示不匹配为止; 并且如果指示不匹配，位于错配的行和列的交点处的位被反转。

3. 发明授权

US07010741B2 Method and circuit for error correction in CAM cells 有权
标题翻译： CAM单元纠错方法与电路
公开(公告)号：US07010741B2
公开(公告)日：2006-03-07
申请号：US10306732
申请日：2002-11-29
申请人： Richard Foss , Alan Roth
发明人： Richard Foss , Alan Roth
IPC分类号： G11C29/00
CPC分类号： G06F11/1064 , G11C15/00
摘要： A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching CAM cells in the array. The method includes the following steps: a row parity bit corresponding to a parity of a first plurality of bits stored along a row of CAM cells is stored; a column parity bit corresponding to the parity of a second plurality of bits stored along a column of CAM cells is stored; a parity of the first plurality of bits is read and generated and the generated parity is compared to the stored row parity bit; if the generated and stored parity bits do not match, columns of the array are cycled through; a parity of the second plurality of bits is read and generated and the generated parity is compared to the stored column parity bit until a mismatch is indicated; and, a bit located at an intersection of the mismatched row and column is inverted if the mismatch is indicated.
摘要翻译：提供了一种用于检测和校正内容可寻址存储器（CAM）单元阵列中的错误的方法和电路。阵列包括用于从阵列中读取，写入和搜索CAM单元的字线，搜索线，位线和匹配线。该方法包括以下步骤：存储对应于沿着一组CAM单元存储的第一多个比特的奇偶校验位的行奇偶校验位; 存储与沿着CAM单元的列存储的第二多个比特的奇偶校验相对应的列奇偶校验位; 读取并生成第一多个比特的奇偶校验，并将所生成的奇偶校验与存储的行奇偶校验位进行比较; 如果生成和存储的奇偶校验位不匹配，则阵列的列循环; 读取并生成第二多个比特的奇偶校验，并将生成的奇偶校验与存储的列奇偶校验位进行比较，直到指示不匹配为止; 并且如果指示不匹配，位于错配的行和列的交点处的位被反转。

4. 发明申请

US20060123327A1 Method and circuit for error correction in CAM cells 失效
标题翻译： CAM单元纠错方法与电路
公开(公告)号：US20060123327A1
公开(公告)日：2006-06-08
申请号：US11313661
申请日：2005-12-22
申请人： Richard Foss , Alan Roth
发明人： Richard Foss , Alan Roth
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G06F11/1064 , G11C15/00
摘要： A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching CAM cells in the array. The method includes the following steps: a row parity bit corresponding to a parity of a first plurality of bits stored along a row of CAM cells is stored; a column parity bit corresponding to the parity of a second plurality of bits stored along a column of CAM cells is stored; a parity of the first plurality of bits is read and generated and the generated parity is compared to the stored row parity bit, if the generated and stored parity bits do not match, columns of the array are cycled through; a parity of the second plurality of bits is read and generated and the generated parity is compared to the stored column parity bit until a mismatch is indicated; and, a bit located at an intersection of the mismatched row and column is inverted if the mismatch is indicated.
摘要翻译：提供了一种用于检测和校正内容可寻址存储器（CAM）单元阵列中的错误的方法和电路。阵列包括用于从阵列中读取，写入和搜索CAM单元的字线，搜索线，位线和匹配线。该方法包括以下步骤：存储对应于沿着一组CAM单元存储的第一多个比特的奇偶校验位的行奇偶校验位; 存储与沿着CAM单元的列存储的第二多个比特的奇偶校验相对应的列奇偶校验位; 读出并产生第一多个比特的奇偶校验，并且如果生成和存储的奇偶校验位不匹配，则将生成的奇偶校验与存储的行奇偶校验位进行比较，则阵列的列循环; 读取并生成第二多个比特的奇偶校验，并将生成的奇偶校验与存储的列奇偶校验位进行比较，直到指示不匹配为止; 并且如果指示不匹配，位于错配的行和列的交点处的位被反转。

5. 发明申请

US20130082668A1 SINGLE-INDUCTOR MULTIPLE-OUTPUT DC TO DC CONVERTER 有权
标题翻译：单电感器多路输出直流到直流转换器
公开(公告)号：US20130082668A1
公开(公告)日：2013-04-04
申请号：US13340746
申请日：2011-12-30
申请人： Chien-Chung Tseng , Eric Soenen , Alan Roth , Justin Shi
发明人： Chien-Chung Tseng , Eric Soenen , Alan Roth , Justin Shi
IPC分类号： G05F1/577
CPC分类号： H02M3/158 , H02M2001/009
摘要： A DC to DC converter includes a switching circuit and a controller. The switching circuit includes an inductor coupled to first and second voltage supply nodes and to a plurality of output loads. The controller is configured to monitor a current through the inductor and to selectively couple the inductor to each of the plurality of output loads such that at least one of the following criteria is met: 1) an average current through the inductor is minimized for the particular output loads coupled to the switching circuit, or 2) minimize a number of times the switching circuit is switched during a charging period for the particular output loads coupled to the switching circuit.
摘要翻译： DC-DC转换器包括开关电路和控制器。开关电路包括耦合到第一和第二电压供应节点和耦合到多个输出负载的电感器。控制器被配置为监测通过电感器的电流并且选择性地将电感器耦合到多个输出负载中的每一个，使得满足以下标准中的至少一个：1）通过电感器的平均电流对于特定的耦合到开关电路的输出负载，或2）在耦合到开关电路的特定输出负载的充电周期期间最小化开关电路切换的次数。

6. 发明申请

US20110089916A1 LDO REGULATORS FOR INTEGRATED APPLICATIONS 有权
标题翻译：集成应用的LDO调节器
公开(公告)号：US20110089916A1
公开(公告)日：2011-04-21
申请号：US12857092
申请日：2010-08-16
申请人： Eric Soenen , Alan Roth , Justin Shi , Ying-Chih Hsu , Guang-Cheng Wang , Wen-Shen Chou
发明人： Eric Soenen , Alan Roth , Justin Shi , Ying-Chih Hsu , Guang-Cheng Wang , Wen-Shen Chou
IPC分类号： G05F1/10
CPC分类号： G05F1/575 , H02M3/07 , H02M2001/0045
摘要： Embodiments of the invention are related to LDO regulators. In an embodiment, an amplifier drives the gate of a master source follower and of at least one slave source follower to form an LDO regulator. In an alternative embodiment, a charge pump drives the master source follower to form the regulator. Additional slave source followers may be used in conjunction with the charge pump and the master source follower to improve the regulator performance. Other embodiments are also disclosed.
摘要翻译：本发明的实施例涉及LDO调节器。在一个实施例中，放大器驱动主源跟随器的栅极和至少一个从源极跟随器的栅极以形成LDO调节器。在替代实施例中，电荷泵驱动主源极跟随器以形成调节器。附加的从源跟随器可以与电荷泵和主源极跟随器一起使用，以改善调节器的性能。还公开了其他实施例。

7. 发明申请

US20110006844A1 Class D Amplifier Control Circuit and Method 有权
标题翻译： D类放大器控制电路及方法
公开(公告)号：US20110006844A1
公开(公告)日：2011-01-13
申请号：US12858310
申请日：2010-08-17
申请人： Eric Soenen , Alan Roth , Justin Shi , Martin Kinyua
发明人： Eric Soenen , Alan Roth , Justin Shi , Martin Kinyua
IPC分类号： H03F3/217
CPC分类号： H03F3/2173
摘要： Circuit and method for a Class D amplifier. In one exemplary embodiment, an audio amplifier is disclosed. A closed loop configuration for driving high and low side driver transistors is provided, each circuit is compatible with advanced sub micron semiconductor processes. The analog time varying input is coupled to one input of a sigma delta analog to digital converter. A feedback signal from the output is also input to the analog to digital converter. A bit stream is output by the analog to digital converter. A decimator receives this bit stream and downconverts the samples to digital values at a lower frequency. A digital filter with adaptable coefficients is used to filter that signal and a digital pulse width modulator then develops an analog differential PWM signal. A predriver inputs the PWM signal and derives the output gating signals to control the high and low side drivers of a Class D amplifier.
摘要翻译： D类放大器的电路和方法。在一个示例性实施例中，公开了一种音频放大器。提供用于驱动高侧和低侧驱动晶体管的闭环配置，每个电路与先进的亚微米半导体工艺兼容。模拟时变输入耦合到Σ-Δ模数转换器的一个输入端。来自输出的反馈信号也被输入到模数转换器。位流由模数转换器输出。抽取器接收该位流，并以较低的频率将样本下变频为数字值。使用具有适应系数的数字滤波器来对该信号进行滤波，并且数字脉宽调制器然后开发模拟差分PWM信号。预驱动器输入PWM信号并导出输出门控信号以控制D类放大器的高侧和低侧驱动器。

8. 发明授权

US07834604B2 Digital control of power converters 有权
标题翻译：电源转换器的数字控制
公开(公告)号：US07834604B2
公开(公告)日：2010-11-16
申请号：US12197790
申请日：2008-08-25
申请人： Eric Soenen , Alan Roth , Martin Kinyua , Justin Shi
发明人： Eric Soenen , Alan Roth , Martin Kinyua , Justin Shi
IPC分类号： G05F1/40
CPC分类号： H02M3/1588 , H02M2001/0012 , Y02B70/1466
摘要： A system and method for controlling a power converter is presented. An embodiment comprises an analog differential circuit connected to an analog-to-digital converter, and comparing the digital error signal to at least a first threshold value. If the digital error signal is less than the first threshold value, a pulse is generated to control the power converter. Another embodiment includes multiple thresholds that may be compared against the digital error signal.
摘要翻译：提出了一种用于控制功率转换器的系统和方法。实施例包括连接到模拟 - 数字转换器的模拟差分电路，并将数字误差信号与至少第一阈值进行比较。如果数字误差信号小于第一阈值，则产生脉冲以控制功率转换器。另一实施例包括可与数字误差信号进行比较的多个阈值。

9. 发明申请

US20100045376A1 CLASS D AMPLIFIER CONTROL CIRCUIT AND METHOD 审中-公开
标题翻译：等级放大器控制电路和方法
公开(公告)号：US20100045376A1
公开(公告)日：2010-02-25
申请号：US12197967
申请日：2008-08-25
申请人： Eric Soenen , Alan Roth , Justin Shi
发明人： Eric Soenen , Alan Roth , Justin Shi
IPC分类号： H03F3/217
CPC分类号： H03F3/2173
摘要： Circuit and method for a Class D amplifier. In one exemplary embodiment, an audio amplifier is disclosed. A closed loop configuration for driving high and low side driver transistors is provided, each circuit is compatible with advanced sub micron semiconductor processes. The analog time varying input is coupled to one input of a sigma delta analog to digital converter. A feedback signal from the output is also input to the analog to digital converter. A bit stream is output by the analog to digital converter. A decimator receives this bit stream and downconverts the samples to digital values at a lower frequency. A digital filter with adaptable coefficients is used to filter that signal and a digital pulse width modulator then develops an analog differential PWM signal. A predriver inputs the PWM signal and derives the output gating signals to control the high and low side drivers of a Class D amplifier.
摘要翻译： D类放大器的电路和方法。在一个示例性实施例中，公开了一种音频放大器。提供用于驱动高侧和低侧驱动晶体管的闭环配置，每个电路与先进的亚微米半导体工艺兼容。模拟时变输入耦合到Σ-Δ模数转换器的一个输入端。来自输出的反馈信号也被输入到模数转换器。位流由模数转换器输出。抽取器接收该位流，并以较低的频率将样本下变频为数字值。使用具有适应系数的数字滤波器来对该信号进行滤波，并且数字脉宽调制器然后开发模拟差分PWM信号。预驱动器输入PWM信号并导出输出门控信号以控制D类放大器的高侧和低侧驱动器。

10. 发明申请

US20100033216A1 SYNCHRONIZATION CIRCUIT AND METHOD WITH TRANSPARENT LATCHES 有权
标题翻译：同步电路的同步电路和方法
公开(公告)号：US20100033216A1
公开(公告)日：2010-02-11
申请号：US12543839
申请日：2009-08-19
申请人： Alan Roth , Oswald Becca , Pedro Ovalle
发明人： Alan Roth , Oswald Becca , Pedro Ovalle
IPC分类号： H03L7/00
CPC分类号： G06F5/08
摘要： A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.
摘要翻译：提出了用于将数据从输入时钟重新同步到输出时钟的同步电路。第一透明锁存器接收与输入时钟同步的数据。第二透明锁存器从第一透明锁存器接收数据，并输出取决于延迟的输出时钟的数据，延迟的输出时钟是延迟了插入延迟的输出时钟。输出锁存器从第二透明锁存器接收数据并将数据与输出时钟同步。

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