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51. 发明申请

US20070117347A1 Semiconductor constructions 审中-公开
标题翻译：半导体结构
公开(公告)号：US20070117347A1
公开(公告)日：2007-05-24
申请号：US11655386
申请日：2007-01-17
申请人： Hongmei Wang , Fred Fishburn , Janos Fucsko , T. Allen , Richard Lane , Robert Hanson , Kevin Shea
发明人： Hongmei Wang , Fred Fishburn , Janos Fucsko , T. Allen , Richard Lane , Robert Hanson , Kevin Shea
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： The invention includes methods of forming isolation regions. An opening can be formed to extend into a semiconductor material, and an upper periphery of the opening can be protected with a liner while a lower periphery is unlined. The unlined portion can then be etched to form a widened region of the opening. Subsequently, the opening can be filled with insulative material to form an isolation region. Transistor devices can then be formed on opposing sides of the isolation region, and electrically isolated from one another with the isolation region. The invention also includes semiconductor constructions containing an electrically insulative isolation structure extending into a semiconductor material, with the structure having a bulbous bottom region and a stem region extending upwardly from the bottom region to a surface of the semiconductor material.
摘要翻译：本发明包括形成隔离区域的方法。可以形成开口以延伸到半导体材料中，并且可以用衬垫保护开口的上周边，而下边缘是无衬里的。然后可以对无衬里部分进行蚀刻以形成开口的加宽区域。随后，开口可以用绝缘材料填充以形成隔离区域。晶体管器件然后可以形成在隔离区域的相对侧上，并且与隔离区域彼此电隔离。本发明还包括包含延伸到半导体材料中的电绝缘隔离结构的半导体结构，其结构具有球形底部区域和从底部区域向上延伸到半导体材料表面的杆区域。

52. 发明授权

US07205245B2 Method of forming trench isolation within a semiconductor substrate 有权
标题翻译：在半导体衬底内形成沟槽隔离的方法
公开(公告)号：US07205245B2
公开(公告)日：2007-04-17
申请号：US11200632
申请日：2005-08-10
申请人： Janos Fucsko , Grady S. Waldo , Kevin J. Torek , Li Li
发明人： Janos Fucsko , Grady S. Waldo , Kevin J. Torek , Li Li
IPC分类号： H01L21/461 , H01L21/302 , H01L21/8283
CPC分类号： H01L21/31111 , C09K13/08 , H01L21/76224
摘要： A method of etching silicon nitride substantially selectively relative to an oxide of aluminum includes providing a substrate comprising silicon nitride and an oxide of aluminum. The silicon nitride and the oxide is exposed to an etching solution comprising HF and an organic HF solvent under conditions effective to etch the silicon nitride substantially selectively relative to the oxide. Other aspects and implementations are contemplated.
摘要翻译：相对于铝的氧化物基本上选择性地蚀刻氮化硅的方法包括提供包括氮化硅和铝的氧化物的衬底。在有效地相对于氧化物基本上选择性地蚀刻氮化硅的条件下，氮化硅和氧化物暴露于包含HF和有机HF溶剂的蚀刻溶液。考虑了其他方面和实现。

53. 发明申请

US20070042608A1 Method of substantially uniformly etching non-homogeneous substrates 有权
标题翻译：基本均匀地蚀刻非均质基板的方法
公开(公告)号：US20070042608A1
公开(公告)日：2007-02-22
申请号：US11209059
申请日：2005-08-22
申请人： Janos Fucsko , Grady Waldo , Bob Carstensen , Satish Bedge
发明人： Janos Fucsko , Grady Waldo , Bob Carstensen , Satish Bedge
IPC分类号： C03C25/68 , H01L21/302
CPC分类号： C03C15/00 , H01L21/31111 , H01L21/31133 , Y10S134/902 , Y10S438/906
摘要： A method of substantially uniformly etching oxides from non-homogeneous substrates is provided. The method utilizes a substantially non-aqueous etchant including an organic solvent and a fluorine-containing compound. The fluorine containing compound may include HF, HF:NH4F, (NH4)HF2, or TMAF:HF and mixtures thereof. The etchant may be applied to chemically non-homogeneous layers such as shallow trench isolation fill oxide layers, or to layers having a non-homogeneous composition or density at different depths within the layers, such as spin-on-glass or spin-on-dielectric films.
摘要翻译：提供了从非均匀基底基本均匀地蚀刻氧化物的方法。该方法利用包括有机溶剂和含氟化合物的基本非水性蚀刻剂。含氟化合物可以包括HF，HF：NH 4 F，（NH 4）HF 2 H或TMAF：HF及其混合物。蚀刻剂可以应用于化学不均匀的层，例如浅沟槽隔离填充氧化物层，或者在层内的不同深度处具有非均匀组成或密度的层，例如旋涂玻璃或旋转 - 电介质膜。

54. 发明授权

US07166539B2 Wet etching method of removing silicon from a substrate 有权
标题翻译：从基板去除硅的湿蚀刻方法
公开(公告)号：US07166539B2
公开(公告)日：2007-01-23
申请号：US10625166
申请日：2003-07-22
申请人： Janos Fucsko , Grady S. Waldo
发明人： Janos Fucsko , Grady S. Waldo
IPC分类号： H01L21/465
CPC分类号： H01L21/30604 , H01L21/32134 , H01L21/76224 , H01L21/763
摘要： A wet etching method of removing silicon from a substrate includes depositing a layer comprising silicon in elemental form over a substrate. The layer is exposed to an aqueous liquid etching solution comprising a hydroxide and a fluoride, and having a pH of at least 10, under conditions and for a period of time effective to etch the elemental silicon from the substrate. Wet etching can be employed in methods of forming trench isolation, and in other methods. Other aspects and implementations are contemplated.
摘要翻译：从衬底去除硅的湿蚀刻方法包括在衬底上沉积包含元素形式的硅的层。将该层暴露于包含氢氧化物和氟化物的水性液体蚀刻溶液中，并且在有效地从衬底上蚀刻元素硅的条件和时间段内具有至少10的pH。可以在形成沟槽隔离的方法中采用湿式蚀刻，也可以采用其它方法。考虑了其他方面和实现。

55. 发明申请

US20060024914A1 Wet etching method of removing silicon from a substrate and method of forming trench isolation 有权
标题翻译：从基板去除硅的湿式蚀刻方法和形成沟槽隔离的方法
公开(公告)号：US20060024914A1
公开(公告)日：2006-02-02
申请号：US11207115
申请日：2005-08-18
申请人： Janos Fucsko , Grady Waldo
发明人： Janos Fucsko , Grady Waldo
IPC分类号： H01L21/76
CPC分类号： H01L21/30604 , H01L21/32134 , H01L21/76224 , H01L21/763
摘要： A wet etching method of removing silicon from a substrate includes depositing a layer comprising silicon in elemental form over a substrate. The layer is exposed to an aqueous liquid etching solution comprising a hydroxide and a fluoride, and having a pH of at least 10, under conditions and for a period of time effective to etch the elemental silicon from the substrate. Wet etching can be employed in methods of forming trench isolation, and in other methods. Other aspects and implementations are contemplated.
摘要翻译：从衬底去除硅的湿蚀刻方法包括在衬底上沉积包含元素形式的硅的层。将该层暴露于包含氢氧化物和氟化物的水性液体蚀刻溶液中，并且在有效地从衬底上蚀刻元素硅的条件和时间段内具有至少10的pH。可以在形成沟槽隔离的方法中采用湿式蚀刻，也可以采用其它方法。考虑了其他方面和实现。

56. 发明申请

US20060009004A1 Method of forming trench isolation within a semiconductor substrate 有权
标题翻译：在半导体衬底内形成沟槽隔离的方法
公开(公告)号：US20060009004A1
公开(公告)日：2006-01-12
申请号：US11200632
申请日：2005-08-10
申请人： Janos Fucsko , Grady Waldo , Kevin Torek , Li Li
发明人： Janos Fucsko , Grady Waldo , Kevin Torek , Li Li
IPC分类号： H01L21/76
CPC分类号： H01L21/31111 , C09K13/08 , H01L21/76224
摘要： A method of etching silicon nitride substantially selectively relative to an oxide of aluminum includes providing a substrate comprising silicon nitride and an oxide of aluminum. The silicon nitride and the oxide is exposed to an etching solution comprising HF and an organic HF solvent under conditions effective to etch the silicon nitride substantially selectively relative to the oxide. Other aspects and implementations are contemplated.
摘要翻译：相对于铝的氧化物基本上选择性地蚀刻氮化硅的方法包括提供包括氮化硅和铝的氧化物的衬底。在有效地相对于氧化物基本上选择性地蚀刻氮化硅的条件下，氮化硅和氧化物暴露于包含HF和有机HF溶剂的蚀刻溶液。考虑了其他方面和实现。

57. 发明申请

US20050020091A1 Wet etching method of removing silicon from a substrate and method of forming trench isolation 有权
标题翻译：从基板去除硅的湿式蚀刻方法和形成沟槽隔离的方法
公开(公告)号：US20050020091A1
公开(公告)日：2005-01-27
申请号：US10625166
申请日：2003-07-22
申请人： Janos Fucsko , Grady Waldo
发明人： Janos Fucsko , Grady Waldo
IPC分类号： H01L21/302 , H01L21/3213 , H01L21/762
CPC分类号： H01L21/30604 , H01L21/32134 , H01L21/76224 , H01L21/763
摘要： A wet etching method of removing silicon from a substrate includes depositing a layer comprising silicon in elemental form over a substrate. The layer is exposed to an aqueous liquid etching solution comprising a hydroxide and a fluoride, and having a pH of at least 10, under conditions and for a period of time effective to etch the elemental silicon from the substrate. Wet etching can be employed in methods of forming trench isolation, and in other methods. Other aspects and implementations are contemplated.
摘要翻译：从衬底去除硅的湿蚀刻方法包括在衬底上沉积包含元素形式的硅的层。将该层暴露于包含氢氧化物和氟化物的水性液体蚀刻溶液中，并且在有效地从衬底上蚀刻元素硅的条件和时间段内具有至少10的pH。可以在形成沟槽隔离的方法中采用湿式蚀刻，也可以采用其它方法。考虑了其他方面和实现。

58. 发明授权

US08829643B2 Memory arrays 有权
标题翻译：内存阵列
公开(公告)号：US08829643B2
公开(公告)日：2014-09-09
申请号：US12835042
申请日：2010-07-13
申请人： Zailong Bian , Janos Fucsko
发明人： Zailong Bian , Janos Fucsko
IPC分类号： H01L29/00 , H01L27/115 , H01L29/78
CPC分类号： H01L29/0649 , H01L21/762 , H01L21/764 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L29/0642 , H01L29/0653 , H01L29/78
摘要： The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.
摘要翻译：本发明包括具有沟槽隔离区域的半导体结构。沟槽隔离区域的沟槽可以包括底部的窄底部部分和上部宽部分。电绝缘材料可以填充上部宽部分，同时留下狭窄底部内的空隙。沟槽隔离区域可以并入存储器阵列中，和/或可并入到电子系统中。本发明还包括形成半导体结构的方法。

59. 发明申请

US20120178221A1 Methods Of Forming Memory Arrays 有权
标题翻译：形成记忆阵列的方法
公开(公告)号：US20120178221A1
公开(公告)日：2012-07-12
申请号：US13418767
申请日：2012-03-13
申请人： Sanh D. Tang , Janos Fucsko
发明人： Sanh D. Tang , Janos Fucsko
IPC分类号： H01L21/8229
CPC分类号： H01L21/768 , H01L27/112 , H01L27/11206 , H01L27/228 , H01L27/24
摘要： Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.
摘要翻译：一些实施例包括形成存储器阵列的方法。一叠半导体材料板可以被图案化以将该板细分成多个。导电层可以沿着片的侧壁边缘形成。然后将这些片材图案化成线阵列，阵列具有垂直列和水平行。单独的线可以具有连接到导电层的第一端，可以具有与第一端相对的第二端，并且可以在第一端和第二端之间具有中间区域。栅极材料可以沿着中间区域形成。存储单元结构可以形成在电线的第二端。多个垂直延伸的电互连可以通过存储单元结构连接到导线，其中各个垂直延伸的电互连沿阵列的各个列。一些实施例包括并入到集成电路中的存储器阵列。

60. 发明申请

US20110121255A1 Integrated Memory Arrays, And Methods Of Forming Memory Arrays 有权
标题翻译：集成内存数组和形成内存数组的方法
公开(公告)号：US20110121255A1
公开(公告)日：2011-05-26
申请号：US12624312
申请日：2009-11-23
申请人： Sanh D. Tang , Janos Fucsko
发明人： Sanh D. Tang , Janos Fucsko
IPC分类号： H01L45/00 , H01L21/8239
CPC分类号： H01L21/768 , H01L27/112 , H01L27/11206 , H01L27/228 , H01L27/24
摘要： Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.
摘要翻译：一些实施例包括形成存储器阵列的方法。一叠半导体材料板可以被图案化以将该板细分成多个。导电层可以沿着片的侧壁边缘形成。然后将这些片材图案化成线阵列，阵列具有垂直列和水平行。单独的线可以具有连接到导电层的第一端，可以具有与第一端相对的第二端，并且可以在第一端和第二端之间具有中间区域。栅极材料可以沿着中间区域形成。存储单元结构可以形成在电线的第二端。多个垂直延伸的电互连可以通过存储单元结构连接到导线，其中各个垂直延伸的电互连沿阵列的各个列。一些实施例包括并入到集成电路中的存储器阵列。

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