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1. 发明授权

US08513064B2 Methods of forming memory arrays 有权
标题翻译：形成记忆阵列的方法
公开(公告)号：US08513064B2
公开(公告)日：2013-08-20
申请号：US13607339
申请日：2012-09-07
申请人： Sanh D. Tang , Janos Fucsko
发明人： Sanh D. Tang , Janos Fucsko
IPC分类号： H01L21/82
CPC分类号： H01L21/768 , H01L27/112 , H01L27/11206 , H01L27/228 , H01L27/24
摘要： Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.
摘要翻译：一些实施例包括形成存储器阵列的方法。一叠半导体材料板可以被图案化以将该板细分成多个。导电层可以沿着片的侧壁边缘形成。然后将这些片材图案化成线阵列，阵列具有垂直列和水平行。单独的线可以具有连接到导电层的第一端，可以具有与第一端相对的第二端，并且可以在第一端和第二端之间具有中间区域。栅极材料可以沿着中间区域形成。存储单元结构可以形成在电线的第二端。多个垂直延伸的电互连可以通过存储单元结构连接到导线，其中各个垂直延伸的电互连沿阵列的各个列。一些实施例包括并入到集成电路中的存储器阵列。

2. 发明申请

US20120329215A1 Methods of Forming Memory Arrays 有权
标题翻译：形成记忆阵列的方法
公开(公告)号：US20120329215A1
公开(公告)日：2012-12-27
申请号：US13607339
申请日：2012-09-07
申请人： Sanh D. Tang , Janos Fucsko
发明人： Sanh D. Tang , Janos Fucsko
IPC分类号： H01L21/8229
CPC分类号： H01L21/768 , H01L27/112 , H01L27/11206 , H01L27/228 , H01L27/24
摘要： Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.
摘要翻译：一些实施例包括形成存储器阵列的方法。一叠半导体材料板可以被图案化以将该板细分成多个。导电层可以沿着片的侧壁边缘形成。然后将这些片材图案化成线阵列，阵列具有垂直列和水平行。单独的线可以具有连接到导电层的第一端，可以具有与第一端相对的第二端，并且可以在第一端和第二端之间具有中间区域。栅极材料可以沿着中间区域形成。存储单元结构可以形成在电线的第二端。多个垂直延伸的电互连可以通过存储单元结构连接到导线，其中各个垂直延伸的电互连沿阵列的各个列。一些实施例包括并入到集成电路中的存储器阵列。

3. 发明授权

US08288213B2 Methods of forming memory arrays 有权
标题翻译：形成记忆阵列的方法
公开(公告)号：US08288213B2
公开(公告)日：2012-10-16
申请号：US13418767
申请日：2012-03-13
申请人： Sanh D. Tang , Janos Fucsko
发明人： Sanh D. Tang , Janos Fucsko
IPC分类号： H01L21/82
CPC分类号： H01L21/768 , H01L27/112 , H01L27/11206 , H01L27/228 , H01L27/24
摘要： Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.
摘要翻译：一些实施例包括形成存储器阵列的方法。一叠半导体材料板可以被图案化以将该板细分成多个。导电层可以沿着片的侧壁边缘形成。然后将这些片材图案化成线阵列，阵列具有垂直列和水平行。单独的线可以具有连接到导电层的第一端，可以具有与第一端相对的第二端，并且可以在第一端和第二端之间具有中间区域。栅极材料可以沿着中间区域形成。存储单元结构可以形成在电线的第二端。多个垂直延伸的电互连可以通过存储单元结构连接到导线，其中各个垂直延伸的电互连沿阵列的各个列。一些实施例包括并入到集成电路中的存储器阵列。

4. 发明授权

US08158967B2 Integrated memory arrays 有权
标题翻译：集成存储器阵列
公开(公告)号：US08158967B2
公开(公告)日：2012-04-17
申请号：US12624312
申请日：2009-11-23
申请人： Sanh D. Tang , Janos Fucsko
发明人： Sanh D. Tang , Janos Fucsko
IPC分类号： H01L47/00
CPC分类号： H01L21/768 , H01L27/112 , H01L27/11206 , H01L27/228 , H01L27/24
摘要： Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.
摘要翻译：一些实施例包括形成存储器阵列的方法。一叠半导体材料板可以被图案化以将该板细分成多个。导电层可以沿着片的侧壁边缘形成。然后将这些片材图案化成线阵列，阵列具有垂直列和水平行。单独的线可以具有连接到导电层的第一端，可以具有与第一端相对的第二端，并且可以在第一端和第二端之间具有中间区域。栅极材料可以沿着中间区域形成。存储单元结构可以形成在电线的第二端。多个垂直延伸的电互连可以通过存储单元结构连接到导线，其中各个垂直延伸的电互连沿阵列的各个列。一些实施例包括并入到集成电路中的存储器阵列。

5. 发明申请

US20120178221A1 Methods Of Forming Memory Arrays 有权
标题翻译：形成记忆阵列的方法
公开(公告)号：US20120178221A1
公开(公告)日：2012-07-12
申请号：US13418767
申请日：2012-03-13
申请人： Sanh D. Tang , Janos Fucsko
发明人： Sanh D. Tang , Janos Fucsko
IPC分类号： H01L21/8229
CPC分类号： H01L21/768 , H01L27/112 , H01L27/11206 , H01L27/228 , H01L27/24
摘要： Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.
摘要翻译：一些实施例包括形成存储器阵列的方法。一叠半导体材料板可以被图案化以将该板细分成多个。导电层可以沿着片的侧壁边缘形成。然后将这些片材图案化成线阵列，阵列具有垂直列和水平行。单独的线可以具有连接到导电层的第一端，可以具有与第一端相对的第二端，并且可以在第一端和第二端之间具有中间区域。栅极材料可以沿着中间区域形成。存储单元结构可以形成在电线的第二端。多个垂直延伸的电互连可以通过存储单元结构连接到导线，其中各个垂直延伸的电互连沿阵列的各个列。一些实施例包括并入到集成电路中的存储器阵列。

6. 发明申请

US20110121255A1 Integrated Memory Arrays, And Methods Of Forming Memory Arrays 有权
标题翻译：集成内存数组和形成内存数组的方法
公开(公告)号：US20110121255A1
公开(公告)日：2011-05-26
申请号：US12624312
申请日：2009-11-23
申请人： Sanh D. Tang , Janos Fucsko
发明人： Sanh D. Tang , Janos Fucsko
IPC分类号： H01L45/00 , H01L21/8239
CPC分类号： H01L21/768 , H01L27/112 , H01L27/11206 , H01L27/228 , H01L27/24
摘要： Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.
摘要翻译：一些实施例包括形成存储器阵列的方法。一叠半导体材料板可以被图案化以将该板细分成多个。导电层可以沿着片的侧壁边缘形成。然后将这些片材图案化成线阵列，阵列具有垂直列和水平行。单独的线可以具有连接到导电层的第一端，可以具有与第一端相对的第二端，并且可以在第一端和第二端之间具有中间区域。栅极材料可以沿着中间区域形成。存储单元结构可以形成在电线的第二端。多个垂直延伸的电互连可以通过存储单元结构连接到导线，其中各个垂直延伸的电互连沿阵列的各个列。一些实施例包括并入到集成电路中的存储器阵列。

7. 发明申请

US20190067028A1 VAPOR-ETCH CYCLIC PROCESS 审中-公开
公开(公告)号：US20190067028A1
公开(公告)日：2019-02-28
申请号：US15686526
申请日：2017-08-25
申请人： Andrew L. Li , Prashant Raghu , Sanjeev Sapra , Rita J. Klein , Sanh D. Tang , Sourabh Dhir
发明人： Andrew L. Li , Prashant Raghu , Sanjeev Sapra , Rita J. Klein , Sanh D. Tang , Sourabh Dhir
IPC分类号： H01L21/311 , H01L21/02 , H01L27/108 , H01L21/66 , H01L21/67
摘要： Various embodiments comprise methods of selectively etching oxides over nitrides in a vapor-etch cyclic process. In one embodiment, the method includes, in a first portion of the vapor-etch cyclic process, exposing a substrate having oxide features and nitride features formed thereon to selected etchants in a vapor-phase chamber; transferring the substrate to a post-etch heat treatment chamber; and heating the substrate to remove etchant reaction products from the substrate. In a second portion of the vapor-etch cyclic process, the method continues with transferring the substrate from the post-etch heat treatment chamber to the vapor-phase chamber; exposing the substrate to the selected etchants in the vapor-phase chamber; transferring the substrate to the post-etch heat treatment chamber; and heating the substrate to remove additional etchant reaction products from the substrate. Apparatuses for performing the method and additional methods are also disclosed.

8. 发明授权

US08574954B2 Phase change memory structures and methods 有权
标题翻译：相变记忆结构和方法
公开(公告)号：US08574954B2
公开(公告)日：2013-11-05
申请号：US12872945
申请日：2010-08-31
申请人： Sanh D. Tang
发明人： Sanh D. Tang
IPC分类号： H01L21/62
CPC分类号： H01L45/1253 , G11C13/0004 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/14 , H01L45/144 , H01L45/148 , H01L45/1675 , H01L45/1683
摘要： Methods, devices, and systems associated with phase change material memory are described herein. In one or more embodiments, a method of forming a phase change material memory cell includes forming a number of memory structure regions, wherein the memory structure regions include a bottom electrode material and a sacrificial material, forming a number of insulator regions between the number of memory structure regions, forming a number of openings between the number of insulator regions and forming a contoured surface on the number of insulator regions by removing the sacrificial material and a portion of the number of insulator regions, forming a number of dielectric spacers on the number of insulator regions, forming a contoured opening between the number of insulator regions and exposing the bottom electrode material by removing a portion of the number of dielectric spacers, and forming a phase change material in the opening between the number of insulator regions.
摘要翻译：本文描述了与相变材料存储器相关联的方法，装置和系统。在一个或多个实施例中，形成相变材料存储单元的方法包括形成多个存储器结构区域，其中存储器结构区域包括底部电极材料和牺牲材料，在多个绝缘体区域之间形成多个绝缘体区域存储器结构区域，在多个绝缘体区域之间形成多个开口，并通过去除牺牲材料和绝缘体区域的数量的一部分在绝缘体区域的数量上形成轮廓表面，在数量上形成多个电介质间隔物的绝缘体区域之间，在多个绝缘体区域之间形成轮廓的开口，并通过去除一部分电介质间隔物而露出底部电极材料，并且在绝缘体区域之间的开口中形成相变材料。

9. 发明授权

US08535992B2 Thyristor random access memory device and method 有权
标题翻译：晶闸管随机存取存储器件及方法
公开(公告)号：US08535992B2
公开(公告)日：2013-09-17
申请号：US12826323
申请日：2010-06-29
申请人： Sanh D. Tang , John K. Zahurak , Michael P. Violette
发明人： Sanh D. Tang , John K. Zahurak , Michael P. Violette
IPC分类号： H01L21/322
CPC分类号： H01L29/66363 , H01L27/1027 , H01L29/42308 , H01L29/74 , H01L2924/1301
摘要： Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.
摘要翻译：显示存储器件和制造存储器件的方法。所示的方法和配置提供用于增加存储器密度的折叠和垂直存储器件。提供的方法减少了对诸如深掺杂剂植入物的制造方法的需要。

10. 发明授权

US08513722B2 Floating body cell structures, devices including same, and methods for forming same 有权
标题翻译：浮体细胞结构，包括其的装置及其形成方法
公开(公告)号：US08513722B2
公开(公告)日：2013-08-20
申请号：US12715843
申请日：2010-03-02
申请人： Sanh D. Tang , John K. Zahurak , Werner Juengling
发明人： Sanh D. Tang , John K. Zahurak , Werner Juengling
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10802 , H01L21/845 , H01L27/10826 , H01L27/10879 , H01L27/1211 , H01L29/4236 , H01L29/7841
摘要： Floating body cell structures including an array of floating body cells disposed on a back gate and source regions and drain regions of the floating body cells spaced apart from the back gate. The floating body cells may each include a volume of semiconductive material having a channel region extending between pillars, which may be separated by a void, such as a U-shaped trench. The floating body cells of the array may be electrically coupled to another gate, which may be disposed on sidewalls of the volume of semiconductive material or within the void therein. Methods of forming the floating body cell devices are also disclosed.
摘要翻译：包括浮置体细胞结构，其包括布置在背栅上的浮体阵列阵列和与后门间隔开的浮体细胞的源区和漏区。浮体细胞可以各自包括体积的半导体材料，其具有在柱之间延伸的通道区域，其可以通过诸如U形沟槽的空隙分开。阵列的浮体电池可以电耦合到另一个栅极，另一个栅极可以设置在半导体材料的体积的侧壁上或其内的空隙中。还公开了形成浮体电池器件的方法。

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