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51. 发明申请

US20090036556A1 Acidic Zirconia Sol and Production Method of the Same 有权
标题翻译：酸性氧化锆溶胶及其制备方法
公开(公告)号：US20090036556A1
公开(公告)日：2009-02-05
申请号：US11918134
申请日：2006-04-11
申请人： Yutaka Ohmori , Hirokazu Kato , Kenji Yamaguchi
发明人： Yutaka Ohmori , Hirokazu Kato , Kenji Yamaguchi
IPC分类号： B01F3/12
CPC分类号： C01G25/02 , B82Y30/00 , C01P2004/64
摘要： There is provided an acidic zirconia sol having compatibility of particle properties and binding properties, and a production method of the same.The present invention relates to a production method of an acidic zirconia sol containing zirconia particles having a particle diameter of less than 20 nm in a content of 10 to 50% by mass, based on the mass of all zirconia particles including: a first process in which an alkaline zirconia sol (A) and a zirconium salt (B) are mixed in a mass ratio (Bs/As) ranging from 0.2 to 5.0 of a mass of a solid content (Bs) which is converted into an amount of ZrO2 in the zirconium salt (B) to a mass of a solid content (As) which is converted into an amount of ZrO2 in the alkaline zirconia sol (A); and a second process in which the resultant mixture is reacted at 80 to 250°C. to produce an acidic zirconia sol.
摘要翻译：提供了具有颗粒性质和结合性质的相容性的酸性氧化锆溶胶及其制备方法。本发明涉及以氧化锆粒子的质量计，含有10〜50质量％的粒径小于20nm的氧化锆粒子的酸性氧化锆溶胶的制造方法，其特征在于，包括：将碱土金属氧化锆溶胶（A）和锆盐（B）以质量比（Bs / As）为0.2〜5.0，以固体成分（Bs）的质量比转化成ZrO 2的量在碱性氧化锆溶胶（A）中将锆盐（B）转化为一定量的ZrO 2的固体成分（As）的质量; 和其中所得混合物在80-250℃下反应的第二种方法。以产生酸性氧化锆溶胶。

52. 发明申请

US20090032994A1 Method for Manufacturing Slurry and Mold for Precision Casting 有权
标题翻译：制造精密铸造用浆料和模具的方法
公开(公告)号：US20090032994A1
公开(公告)日：2009-02-05
申请号：US11922777
申请日：2006-06-21
申请人： Kiyomi Ema , Yutaka Ohmori , Hirokazu Kato , Kenji Yamaguchi
发明人： Kiyomi Ema , Yutaka Ohmori , Hirokazu Kato , Kenji Yamaguchi
IPC分类号： B29C33/38 , C04B35/48
CPC分类号： B22C1/08 , B82Y30/00 , C04B35/481 , C04B35/486 , C04B35/624 , C04B35/6263 , C04B35/6303 , C04B35/634 , C04B2235/3208 , C04B2235/3217 , C04B2235/3244 , C04B2235/3246 , C04B2235/3248 , C04B2235/3463 , C04B2235/442 , C04B2235/5427 , C04B2235/5454 , C04B2235/6028 , C04B2235/606 , C04B2235/6567
摘要： A manufacturing method for a slurry for the production of a precision casting mold that includes a zirconia sol and a refractory powder, and a manufacturing method for a precision casting mold that uses the slurry is provided. The present invention relates to a manufacturing method for a slurry for the production of a precision casting mold for a metal that includes a step in which an alkaline zirconia sol (A1) and a refractory powder (D) are mixed, the alkaline zirconia sol (A1) being obtained by a manufacturing method that includes a step (i), in which a zirconium salt (B1) is heated at 60 to 110° C. in an aqueous medium that includes a carbonate of quaternary ammonium, and a step (ii), in which a hydrothermal treatment is carried out at 100 to 250° C. In addition, the present invention relates to a manufacturing method for a slurry for the production of a precision casting mold for a metal that includes a step in which an acidic zirconia sol (C3) and a refractory powder (D) are mixed, the acidic zirconia sol (C3) being obtained by a manufacturing method that includes a step (I), in which an alkaline zirconia sol (A3) and a zirconium salt (B3) are mixed, and a step II, in which the obtained liquid mixture is caused to react at 80 to 250° C.
摘要翻译：提供了一种用于生产包括氧化锆溶胶和耐火材料粉末的精密铸造模具的浆料的制造方法，以及使用该浆料的精密铸造模具的制造方法。本发明涉及一种用于生产金属精密铸造模具的浆料的制造方法，其包括将碱性氧化锆溶胶（A1）和耐火材料粉末（D）混合的步骤，所述碱性氧化锆溶胶（ A1）通过包括步骤（i）的制备方法获得，其中锆盐（B1）在包含季铵盐的碳酸盐的水性介质中在60至110℃下加热，和步骤（ii）），其中在100〜250℃下进行水热处理。此外，本发明涉及一种用于制造金属精密铸造模具的浆料的制造方法，其包括以下步骤：将酸性氧化锆溶胶（C3）和耐火粉末（D）混合，所述酸性氧化锆溶胶（C3）通过包括步骤（I）的制备方法获得，其中碱性氧化锆溶胶（A3）和锆盐（ B3）混合，和步骤II，其中所获得的液体混合 e在80〜250℃下反应

53. 发明授权

US07480598B2 Characteristic evaluation apparatus for insulated gate type transistors 失效
公开(公告)号：US07480598B2
公开(公告)日：2009-01-20
申请号：US10702455
申请日：2003-11-07
申请人： Kenji Yamaguchi
发明人： Kenji Yamaguchi
IPC分类号： G06F17/10 , G01R31/26
CPC分类号： H01L22/14 , G01R31/2621 , G01R31/2837
摘要： The accuracy of effective channel width extraction in drain current method is improved. There are prepared a transistor with a wide channel width serving as a reference, and a transistor with a narrow channel width that becomes a candidate for extraction (step ST1.1). From the characteristic curve of a plane formed by mask channel width and source-drain conductance, there is extracted a virtual point at which the change of source-drain conductance is estimated to be approximately zero even if the gate overdrive is finely changed. Then, the value of function F is calculated which is defined by the difference between the change of the conductance at the coordinate of the virtual point and the product obtained by multiplying the conductance per unit width by the change of the mask channel width (step ST1.6). From a shift amount (δ) which minimizes the standard deviation of the function F to be obtained (step ST1.7), the true threshold voltage of the transistor with the narrow channel width is determined (step ST1.10).

54. 发明申请

US20050008741A1 Liquid foods and process for producing the same 审中-公开
标题翻译：液体食品及其制造方法
公开(公告)号：US20050008741A1
公开(公告)日：2005-01-13
申请号：US10481894
申请日：2002-07-03
申请人： Takashi Inoue , Wakako Kato , Kenji Yamaguchi
发明人： Takashi Inoue , Wakako Kato , Kenji Yamaguchi
IPC分类号： A23C3/00 , A23F3/16 , A23F5/18 , A23F5/24 , A23L2/44 , A23L2/50 , A23L3/32 , A23L23/00 , C12H1/00
CPC分类号： A23C3/00 , A23F3/163 , A23F5/18 , A23F5/243 , A23L2/44 , A23L2/50 , A23L3/325
摘要： The invention is to provide a process for producing a liquid food, characterized by subjecting at least one of coffee, a milk composition, a food material (liquid) containing a component(s) having an antioxidation ability (radical-scavenging activity) and mixed liquids containing one(s) of them to an electrolysis treatment and/or a current passage treatment. Since the invention can prevent quality deterioration of coffee or milk composition over a long period of time without using additives and also improve safety, it is appropriate for producing canned coffee, milk-containing coffee or milk-containing tea drink to be sold in vending machines or can warmers. Further, since the invention can improve the antioxidation ability of foods, the resulting foods can suppress the in-vivo increase of active oxygen and free radicals, it greatly contributes to health.
摘要翻译：本发明提供一种制备液体食品的方法，其特征在于，将至少一种咖啡，乳组合物，含有抗氧化能力（自由基清除活性）的成分的食品（液体）和混合的含有它们的液体进行电解处理和/或电流通道处理。由于本发明可以在不使用添加剂的情况下长时间防止咖啡或牛奶组合物的质量劣化并且还提高安全性，所以适合于生产在自动售货机中出售的罐装咖啡，含牛奶的咖啡或含牛奶的茶饮料或者可以加热。此外，由于本发明能够提高食品的抗氧化能力，因此能够抑制活性氧和自由基的体内增加，从而极大地有助于健康。

55. 发明授权

US06735558B1 Characteristic extraction device, characteristic evaluation device, characteristic extraction method, characteristic evaluation method, recording medium and semiconductor device 失效
标题翻译：特征提取装置，特征评估装置，特征提取方法，特征评估方法，记录介质和半导体装置
公开(公告)号：US06735558B1
公开(公告)日：2004-05-11
申请号：US09487826
申请日：2000-01-20
申请人： Kenji Yamaguchi
发明人： Kenji Yamaguchi
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： As to at least two transistors different only in channel lengths from each other, Ids−Vgs characteristics in a linear region are measured under two drain-to-source voltages Vds. Consequently, a graph of Rtot=Vds/Ids vs. channel lengths is obtained for two Vds, whereby an effective channel length Leff for each Vds is extracted. A velocity saturation coefficient U1 is obtained by expressing the relation between two effective channel lengths Le1 and Le2 corresponding to the two Vds on the graph and dividing the value of Le2 at Le1=0 by the difference &Dgr;Vds between the two Vds. Thus, parameters related to mobility and a velocity saturation effect are extracted with consistency in a form matching with remaining E-T data.
摘要翻译：至少两个晶体管的沟道长度彼此不同，线性区域中的Ids-Vgs特性在两个漏极 - 源极电压Vds之间被测量。因此，对于两个Vds获得Rtot = Vds / Ids与通道长度的曲线图，由此提取每个Vds的有效通道长度Leff。通过表示与曲线图上的两个Vds相对应的两个有效通道长度Le1和Le2之间的关系来获得速度饱和系数U1，并且将Le1 = 0处的Le2值除以两个Vds之间的差ΔVd。因此，以与剩余E-T数据匹配的形式的一致性来提取与移动性和速度饱和效应相关的参数。

56. 发明授权

US06569534B2 Optical material and optical element using the same 有权
标题翻译：光学材料和光学元件使用相同
公开(公告)号：US06569534B2
公开(公告)日：2003-05-27
申请号：US09797881
申请日：2001-03-05
申请人： Kenji Yamaguchi , Kazuki Mizushima
发明人： Kenji Yamaguchi , Kazuki Mizushima
IPC分类号： B32B700
CPC分类号： H01L33/08 , H01L31/032 , H01L33/34 , Y02E10/547 , Y10S428/917 , Y10T428/256
摘要： An optical material including a crystalline silicon and FexSi2 in the form of dots, islands, or a film is provided. The FexSi2 has a symmetrical monoclinic crystalline structure belonging to the P21/c space group and is synthesized at the surface or in the interior of the crystalline silicon. The monoclinic structure corresponds to a deformed structure of &bgr;-FeSi2 generated by heteroepitaxial stress between the {110} plane of the FexSi2 and the {111} plane of the crystalline silicon. The value of x is 0.85≦x≦1.1. An optical element using the optical material is also provided.
摘要翻译：提供了包括晶体硅和FexSi2的光学材料，其形式为点，岛或膜。 FexSi2具有属于P21 / C空间群的对称单斜晶体结构，并在晶体硅的表面或内部合成。单晶结构对应于由FexSi2的{110}平面和晶体硅的{111}面之间的异质外延应力产生的β-FeSi2的变形结构。 x的值为0.85 <= x <= 1.1。还提供了使用光学材料的光学元件。

57. 发明授权

US06559672B2 Characteristic evaluation apparatus for insulated gate type transistors 失效
公开(公告)号：US06559672B2
公开(公告)日：2003-05-06
申请号：US10093936
申请日：2002-03-11
申请人： Kenji Yamaguchi
发明人： Kenji Yamaguchi
IPC分类号： G01R3126
CPC分类号： H01L22/14 , G01R31/2621 , G01R31/2837
摘要： The accuracy of effective channel width extraction in drain current method is improved. There are prepared a transistor with a wide channel width serving as a reference, and a transistor with a narrow channel width that becomes a candidate for extraction (step ST1.1). From the characteristic curve of a plane formed by mask channel width and source-drain conductance, there is extracted a virtual point at which the change of source-drain conductance is estimated to be approximately zero even if the gate overdrive is finely changed. Then, the value of function F is calculated which is defined by the difference between the change of the conductance at the coordinate of the virtual point and the product obtained by multiplying the conductance per unit width by the change of the mask channel width (step ST1.6). From a shift amount (&dgr;) which minimizes the standard deviation of the function F to be obtained (step ST1.7), the true threshold voltage of the transistor with the narrow channel width is determined (step ST1.10).

58. 发明授权

US06525338B2 Semiconductor substrate, field effect transistor, method of forming SiGe layer and method of forming strained Si layer using same, and method of manufacturing field effect transistor 有权
公开(公告)号：US06525338B2
公开(公告)日：2003-02-25
申请号：US09917923
申请日：2001-07-31
申请人： Kazuki Mizushima , Ichiro Shiono , Kenji Yamaguchi
发明人： Kazuki Mizushima , Ichiro Shiono , Kenji Yamaguchi
IPC分类号： H01L2906
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/0251 , H01L21/02532 , H01L29/66916
摘要： A semiconductor substrate, a field effect transistor, a method of forming a SiGe layer and a method of forming a strained Si layer using the same, and a method of manufacturing a field effect transistor are provided, which enable the threading dislocation density of the SiGe layer to be reduced and the surface roughness to be minimized. On top of a Si substrate 1 is provided a SiGe buffer layer 2, 12 constructed of a plurality of laminated layers comprising alternating layers of a SiGe gradient composition layer 2a, 12a in which the Ge composition ratio increases gradually from the Ge composition ratio of the base material, and a SiGe constant composition layer 2b, 12b which is provided on top of the gradient composition layer and in which the Ge composition ratio is equal to that of the upper surface of the gradient composition layer.

59. 发明授权

US5589668A Multi-metal layer wiring tab tape carrier and process for fabricating the same 失效
标题翻译：多金属层接线片带载体及其制造方法
公开(公告)号：US5589668A
公开(公告)日：1996-12-31
申请号：US149795
申请日：1993-11-10
申请人： Kenji Yamaguchi , Shoji Takagi , Sadahiko Mitsugi , Mamoru Mita , Tomio Murakami
发明人： Kenji Yamaguchi , Shoji Takagi , Sadahiko Mitsugi , Mamoru Mita , Tomio Murakami
IPC分类号： H01L23/498 , H05K3/40 , H05K1/14
CPC分类号： H01L23/4985 , H05K3/4076 , H01L2924/0002 , H01L2924/3011
摘要： A multi-metal layer wiring TAB tape carrier capable of forming a fine pattern without affecting the thicknesses of conductive metal layers, and a process for fabricating the multi-metal layer wiring TAB tape carrier. This TAB tape carrier is constructed such that respective dielectric film layers are interposed between adjacent ones of plurality of conductive metal layers having a predetermined wiring pattern, such that the dielectric film layer is formed with interfacial connection holes, and such that a conductive via layer is formed in the interfacial connection holes to electrically connect adjacent conductive metal layers. The conductive via layer is formed by a vapor deposition method such as evaporation, ion plating or sputtering. Alternatively, a portion of the conductive metal layers and the conductive via layer are simultaneously formed. Especially according to the latter method of forming a portion of the conductive metal layers and the conductive via layer simultaneously, the conductive via layer need not be formed after the conductive metal layers so that the fabrication steps are simplified. Moreover, the thicknesses of the conductive metal layers are not adversely affected later, and the conductive metal layers and the conductive via layer can be positioned highly precisely to form a fine wiring pattern.
摘要翻译：能够形成精细图案而不影响导电金属层的厚度的多金属层布线TAB带载体，以及制造多金属层布线TAB带载体的工艺。该TAB带载体被构造成使得各个电介质膜层插入具有预定布线图案的多个导电金属层的相邻的导电金属层之间，使得电介质膜层形成有界面连接孔，并且导电通孔层为形成在界面连接孔中以电连接相邻的导电金属层。导电通孔层通过蒸发，离子镀或溅射等气相沉积法形成。或者，同时形成一部分导电金属层和导电通孔层。特别地，根据后一种形成导电金属层和导电通路层的一部分的方法，导电通孔层不需要在导电金属层之后形成，从而简化制造步骤。此外，导电性金属层的厚度以后不会受到不利影响，并且可以高精度地定位导电金属层和导电通孔层以形成精细的布线图案。

60. 发明授权

US5442229A Metal lead-film carrier assembly having a plurality of film carriers, and film carrier-semiconductor chip assembly and semiconductor device containing such metal lead-film carrier assembly 失效
标题翻译：具有多个膜载体的金属铅膜载体组件和包含这种金属引线膜载体组件的膜载体 - 半导体芯片组件和半导体装置
公开(公告)号：US5442229A
公开(公告)日：1995-08-15
申请号：US118646
申请日：1993-09-10
申请人： Takao Mori , Satoshi Yoshida , Tadahiko Nishimukai , Kenji Yamaguchi
发明人： Takao Mori , Satoshi Yoshida , Tadahiko Nishimukai , Kenji Yamaguchi
IPC分类号： H01L21/60 , H01L23/495 , H01L23/50 , H01L25/04 , H01L25/18 , H01L23/48 , H01L29/44 , H01L29/52 , H01L29/60
CPC分类号： H01L24/81 , H01L23/49572 , H01L2224/13111 , H01L2224/13144 , H01L2224/16145 , H01L2224/73253 , H01L2224/81801 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15312 , H01L2924/16195 , H01L2924/30105 , H01L2924/30107
摘要： A method of assembling a semiconductor chip on a tape carrier has the steps of stacking, on a film carrier having a first group of metal leads, another film carrier having a second group of metal leads and bonding the two film carriers together by adhesive to form a laminated structure. The first and second groups of metal leads are so disposed that they do not contact and do not cross one another. The tips of the metal leads of the two groups are bonded to the electrodes on the semiconductor chip. The metal leads are formed in advance on the corresponding film carriers by etching. By stacking the plurality of film carriers, the connection pitch can be reduced while eliminating a necessity for reducing the thickness of each lead.
摘要翻译：将半导体芯片组装在带载体上的方法具有以下步骤：在具有第一组金属引线的薄膜载体上堆叠具有第二组金属引线的另一薄膜载体，并通过粘合剂将两个薄膜载体粘合在一起形成层压结构。金属引线的第一组和第二组被布置成使它们不接触并且不互相交叉。两组的金属引线的尖端接合到半导体芯片上的电极。金属引线通过蚀刻预先形成在相应的载体上。通过堆叠多个薄膜载体，可以减少连接间距，而不需要减少每个导线的厚度。

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