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51. 发明申请

US20070294471A1 DRAM ACCESS COMMAND QUEUING METHOD 有权
标题翻译： DRAM访问命令队列方法
公开(公告)号：US20070294471A1
公开(公告)日：2007-12-20
申请号：US11832220
申请日：2007-08-01
申请人： Jean Calvignac , Chih-jen Chang , Gordon Davis , Fabrice Verplanken
发明人： Jean Calvignac , Chih-jen Chang , Gordon Davis , Fabrice Verplanken
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.
摘要翻译：访问仲裁器被用于将对DRAM存储器件，特别是快速循环DRAM中的各个存储体的读取和写入访问请求进行优先级排序。这用于通过避免对同一存储体的连续访问并且通过最小化死循环来优化用于读取和写入操作的存储器带宽。仲裁器首先将DRAM访问划分为写访问和读访问。访问请求被划分为每个存储体的访问，并且对每个存储体的访问次数施加了阈值限制。基于写入队列状态，写入接收数据包在存储体之间旋转。每个存储体的写入队列的状态也可以用于系统流控制。仲裁器还通常包括基于命令队列的状态来确定访问窗口的能力，并且在每个访问窗口上执行仲裁。

52. 发明申请

US20060285551A1 STM-1 TO STM-64 SDH/SONET FRAMER WITH DATA MULTIPLEXING FROM A SERIES OF CONFIGURABLE I/O PORTS 有权
标题翻译： STM-1到STM-64 SDH / SONET框架，具有从一系列可配置I / O端口进行数据多路复用
公开(公告)号：US20060285551A1
公开(公告)日：2006-12-21
申请号：US11467848
申请日：2006-08-28
申请人： Kenneth Barker , Rolf Clauberg , Jean Calvignac , Andreas Herkersdorf , Fabrice Verplanken , David Webb
发明人： Kenneth Barker , Rolf Clauberg , Jean Calvignac , Andreas Herkersdorf , Fabrice Verplanken , David Webb
IPC分类号： H04J3/22
CPC分类号： H04J3/1611 , H04J3/0685 , H04J3/22 , H04J2203/0089
摘要： The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port snning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.
摘要翻译：本发明涉及一种用于将具有输入数据速率的至少两个数据信号组合成具有高于用于在共享介质上传输的输入数据速率的输出数据速率的单个数据流的装置，反之亦然，特别涉及一种单个SDH / SONET成帧器能够处理从STM-i到STM-j的大范围的SDH / SONET帧，具有对应于STM-j帧的聚合总容量，其中i和j是从1到64的整数或根据SDH / SONET标准的STM-N定义更高。更进一步地，本发明也可以扩展到使用STS-1作为最低范围。 STS-1仅存在于SONET中而不是SDH，对应于156Mb / s的STM-1的三分之一的51.5Mb / s的数据速率。根据本发明的装置包括用于接收和/或发送所述至少两个数据信号的至少两个端口，用于从由所述端口接收的数据信号中提取数据和/或合成要通过所述端口发送的数据的端口捕捉单元其中所述端口扫描单元被配置为从提供具有至少两个不同输入数据速率的数据流的端口提取数据和/或合成要通过端口发送的数据，该数据流具有至少两个不同数据速率的数据流。

53. 发明申请

US20060221953A1 Method and apparatus for blind checksum and correction for network transmissions 审中-公开
标题翻译：用于网络传输的盲校验和校正的方法和装置
公开(公告)号：US20060221953A1
公开(公告)日：2006-10-05
申请号：US11097055
申请日：2005-04-01
申请人： Claude Basso , Jean Calvignac , Chih-Jen Chang , Philippe Damon , Ronald Fuhs , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli , Scott Willenborg
发明人： Claude Basso , Jean Calvignac , Chih-Jen Chang , Philippe Damon , Ronald Fuhs , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli , Scott Willenborg
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L69/16 , H04L1/0041 , H04L1/0061 , H04L1/0072 , H04L69/161
摘要： Method and apparatus for providing a checksum in a network transmission. In one aspect of the invention, a checksum for a packet to be transmitted on a network is determined by retrieving packet information from a storage device, the packet information to be included in the packet to be transmitted. A blind checksum value is determined based on the retrieved packet information, and the blind checksum value is adjusted to a protocol checksum based on descriptor information describing the structure of the packet. The protocol checksum is inserted in the packet before the packet is transmitted.
摘要翻译：用于在网络传输中提供校验和的方法和装置。在本发明的一个方面，通过从存储设备检索分组信息来确定要在网络上发送的分组的校验和，所述分组信息将包括在要发送的分组中。基于检索的分组信息确定盲校验和值，并且基于描述分组的结构的描述符信息将盲校验和值调整为协议校验和。在分组发送之前，协议校验和被插入到分组中。

54. 发明申请

US20060209827A1 Systems and methods for implementing counters in a network processor with cost effective memory 失效
标题翻译：在具有成本效益的存储器的网络处理器中实现计数器的系统和方法
公开(公告)号：US20060209827A1
公开(公告)日：2006-09-21
申请号：US11070060
申请日：2005-03-02
申请人： Jean Calvignac , Chih-jen Chang , Joseph Logan , Fabrice Verplanken
发明人： Jean Calvignac , Chih-jen Chang , Joseph Logan , Fabrice Verplanken
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L49/901 , H04L49/90
摘要： Systems and methods for implementing counters in a network processor with cost effective memory are disclosed. Embodiments include systems and methods for implementing counters in a network processor using less expensive memory such as DRAM. A network processor receives packets and implements accounting functions including counting packets in each of a plurality of flow queues. Embodiments include a counter controller that may increment counter values more than once during a R-M-W cycle. Each time a counter controller receives a request to update a counter during a R-M-W cycle that has been initiated for the counter, the counter controller increments the counter value received from memory. The incremented value is written to memory during the write cycle of the R-M-W cycle. A write disable unit disables writes that would otherwise occur during R-M-W cycles initiated for the counter during the earlier initiated R-M-W cycle.
摘要翻译：公开了在具有成本效益的存储器的网络处理器中实现计数器的系统和方法。实施例包括用于在使用诸如DRAM的廉价存储器的网络处理器中实现计数器的系统和方法。网络处理器接收分组并实现计费功能，包括在多个流队列中的每一个中计数分组。实施例包括可以在R-M-W周期期间多次增加计数器值的计数器控制器。每当计数器控制器在已经为计数器启动的R-M-W周期期间接收到更新计数器的请求时，计数器控制器增加从存储器接收的计数器值。在R-M-W周期的写周期期间，递增的值被写入存储器。写禁止单元禁用在较早启动的R-M-W周期期间为计数器启动的R-M-W周期期间将发生的写入。

55. 发明申请

US20060187963A1 Method for sharing single data buffer by several packets 审中-公开
标题翻译：通过多个数据包共享单个数据缓冲区的方法
公开(公告)号：US20060187963A1
公开(公告)日：2006-08-24
申请号：US11062036
申请日：2005-02-18
申请人： Claude Basso , Jean Calvignac , Chih-jen Chang , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Chih-jen Chang , Fabrice Verplanken
IPC分类号： H04J3/24
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9021
摘要： Methods, computer readable programs and network processor systems appropriate for IP fragmentation and reassembly on network processors comprising a plurality of buffers and buffer control blocks, the buffer control blocks comprising a buffer usage field, the buffer usage field having a value set responsive to a quantity of frame data fragments, wherein the network processor system associates a buffer control block with each buffer and frees a first buffer after reading a frame data fragment responsive to the first buffer control block buffer usage field value indicating only one frame data fragment is present in the first buffer.
摘要翻译：方法，适用于包括多个缓冲器和缓冲器控制块的网络处理器上的IP分段和重组的计算机可读程序和网络处理器系统，所述缓冲器控制块包括缓冲器使用场，所述缓冲器使用场具有响应于数量的值其中所述网络处理器系统将缓冲器控制块与每个缓冲器相关联，并且在读取帧数据片段之后释放第一缓冲器，所述第一缓冲器响应于所述第一缓冲器控制块缓冲器使用字段值指示仅存在一个帧数据片段第一缓冲区。

56. 发明申请

US20050232205A1 Network switch and components and method of operation 失效
标题翻译：网络交换机及组件及操作方法
公开(公告)号：US20050232205A1
公开(公告)日：2005-10-20
申请号：US11152419
申请日：2005-06-14
申请人： Brian Bass , Jean Calvignac , Anthony Gallo , Marco Heddes , Sridhar Rao , Michael Siegel , Brian Youngman , Fabrice Verplanken
发明人： Brian Bass , Jean Calvignac , Anthony Gallo , Marco Heddes , Sridhar Rao , Michael Siegel , Brian Youngman , Fabrice Verplanken
IPC分类号： G06F15/16 , G06F13/40 , G06F15/177 , H04L12/56 , H04B7/216
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.
摘要翻译：一种网络交换装置，这种装置的组件，以及操作这样的装置的方法，其中通过控制点和形成在半导体衬底上的多个接口处理器的协作来增强数据流处理和灵活性。控制点和接口处理器一起形成一个网络处理器，能够在执行指导网络中的数据流的指令的情况下与包括可选交换结构设备在内的其他元件协作。

57. 发明申请

US20050232204A1 Network switch and components and method of operation 失效
公开(公告)号：US20050232204A1
公开(公告)日：2005-10-20
申请号：US11152119
申请日：2005-06-14
申请人： Brian Bass , Jean Calvignac , Anthony Gallo , Marco Heddes , Sridhar Rao , Michael Siegel , Brian Youngman , Fabrice Verplanken
发明人： Brian Bass , Jean Calvignac , Anthony Gallo , Marco Heddes , Sridhar Rao , Michael Siegel , Brian Youngman , Fabrice Verplanken
IPC分类号： G06F15/16 , G06F13/40 , G06F15/177 , H04L12/56 , H04B7/216
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

58. 发明申请

US20050177552A1 Full match (FM) search algorithm implementation for a network processor 失效
标题翻译：网络处理器的完全匹配（FM）搜索算法实现
公开(公告)号：US20050177552A1
公开(公告)日：2005-08-11
申请号：US10650397
申请日：2003-08-28
申请人： Brian Bass , Jean Calvignac , Marco Heddes , Antonios Maragkos , Piyush Patel , Michael Siegel , Fabrice Verplanken
发明人： Brian Bass , Jean Calvignac , Marco Heddes , Antonios Maragkos , Piyush Patel , Michael Siegel , Fabrice Verplanken
IPC分类号： G06F17/30 , H04L12/46 , H04L12/56 , G06F7/00
CPC分类号： H04L45/742 , H04L45/7453 , Y10S707/99933 , Y10S707/99934 , Y10S707/99935 , Y10S707/99936 , Y10S707/99937 , Y10S707/99943 , Y10S707/99945
摘要： Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBs) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n->n mapping of the bits of the key to the bits of the hash key.
摘要翻译：用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。键输入，对密钥执行哈希函数，访问直接表（DT），并通过模式搜索控制块（PSCB），树直到达到叶。搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。检索所需的两个密钥和相应的信息都存储在Patricia树结构中。散列函数提供密钥的比特到散列密钥的比特的n> n映射。

59. 发明授权

US06789234B2 Method and system for a timing based logic entry 失效
标题翻译：基于定时的逻辑输入的方法和系统
公开(公告)号：US06789234B2
公开(公告)日：2004-09-07
申请号：US10328355
申请日：2002-12-23
申请人： Jean-Paul Aldebert , Jean Calvignac , Fabrice Verplanken
发明人： Jean-Paul Aldebert , Jean Calvignac , Fabrice Verplanken
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： A method and system for creating on a computer a timing based representation of an integrated circuit using a graphical editor operating on the computer. The method includes first in creating timing diagrams identifying the elements of the circuit and their time based interconnections. The method further comprises a translation of the timing based diagram editor files into HDL statement. The preferred embodiment is described, it comprises the use of an ASCII editor and a translation program to VHDL statements. A system is also described implementing the steps of the method in a computer. In order to avoid having different tools to translate timing based diagram editor files into HDL statements, a first step translating graphical editor output file into a PostScript file is performed by executing the “print to file” command of the printing driver of the computer. The PostScript file is then translated into a bitmap file using a RIP. The translation is then performed from the bitmap file into the HDL statements. This translation is “universal” as it can be used for any type of initial graphical file containing the timing diagram.
摘要翻译：一种用于在计算机上创建使用在计算机上操作的图形编辑器的基于时序的集成电路表示的方法和系统。该方法首先在创建识别电路的元件及其基于时间的互连的时序图。该方法还包括将基于时序的编辑器文件转换为HDL语句。描述了优选实施例，它包括使用ASCII编辑器和对VHDL语句的翻译程序。还描述了在计算机中实现该方法的步骤的系统。为了避免使用不同的工具将基于时序的图编辑器文件转换为HDL语句，将图形编辑器输出文件转换为PostScript文件的第一步是通过执行计算机打印驱动程序的“打印到文件”命令执行的。然后使用RIP将PostScript文件转换为位图文件。然后，转换从位图文件执行到HDL语句。这个翻译是“通用的”，因为它可以用于包含时序图的任何类型的初始图形文件。

60. 发明授权

US06195335B1 Data switch 失效
标题翻译：数据开关
公开(公告)号：US06195335B1
公开(公告)日：2001-02-27
申请号：US09110917
申请日：1998-07-06
申请人： Jean Calvignac , Daniel Orsatti , Gilles Toubol , Fabrice Verplanken , Claude Basso
发明人： Jean Calvignac , Daniel Orsatti , Gilles Toubol , Fabrice Verplanken , Claude Basso
IPC分类号： H04L1256
CPC分类号： H04L12/5601 , H04L49/1576 , H04L2012/5679 , H04L2012/5681
摘要： A packet data switch is described comprising a crossbar switch fabric including a set of crosspoint buffers for storing at least one data packet, one for each input/output pair. An input queue is provided for each input-output pair and means are provided for storing incoming data packets in one of the queues corresponding to an input-output routing for the data packet. An input scheduler repeatedly selects one queue from the plurality of queues at each input and a data packet is transferred from the queue selected by the input scheduler from the input queue means to the crosspoint buffer corresponding to the input-output routing for the data packet. A back pressure mechanism is arranged to inhibit selection by the first selector of queues corresponding to input/output pairs for which the respective crosspoint buffer is full. Finally, an output scheduler repeatedly selects for each output one of the crosspoint buffers corresponding to the output and the switch is responsive to the output scheduler to complete the transmission through the switch fabric of the data packet stored in the crosspoint buffer selected by the output scheduler.
摘要翻译：描述包数据交换机，其包括交叉开关结构，其包括用于存储至少一个数据分组的一组交叉点缓冲器，每个数据分组一个用于每个输入/输出对。为每个输入 - 输出对提供输入队列，并且提供装置用于在对应于数据分组的输入 - 输出路由的一个队列中存储输入数据分组。输入调度器在每个输入处重复从多个队列中选择一个队列，并且将数据分组从输入调度器选择的队列从输入队列装置传送到对应于数据分组的输入 - 输出路由的交叉点缓冲区。背压机构被布置为禁止第一选择器对应于相应交叉点缓冲器已满的输入/输出对的队列的选择。最后，输出调度器针对每个输出重复选择对应于输出的交叉点缓冲器之一，并且交换机响应于输出调度器来完成通过存储在由输出调度器选择的交叉点缓冲器中的数据分组的交换结构的传输。

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