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1. 发明申请

US20070067478A1 Data aligner in reconfigurable computing environment technical field 失效
标题翻译：数据对准器在可重构计算环境技术领域
公开(公告)号：US20070067478A1
公开(公告)日：2007-03-22
申请号：US11230956
申请日：2005-09-20
申请人： Fabrice Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Calvignac
发明人： Fabrice Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Calvignac
IPC分类号： G06F15/16
CPC分类号： H04L69/16 , H04L49/45 , H04L69/161
摘要： A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
摘要翻译：公开了可重构计算环境中的数据对准器。实施例使用现场可配置门阵列（FPGA）中的硬件宏来最小化移动数据字节所需的可配置逻辑块（CLB）的数量。与专用集成电路相比，对准机制允许灵活性，可扩展性，可配置性和降低的成本。

2. 发明授权

US06789234B2 Method and system for a timing based logic entry 失效
标题翻译：基于定时的逻辑输入的方法和系统
公开(公告)号：US06789234B2
公开(公告)日：2004-09-07
申请号：US10328355
申请日：2002-12-23
申请人： Jean-Paul Aldebert , Jean Calvignac , Fabrice Verplanken
发明人： Jean-Paul Aldebert , Jean Calvignac , Fabrice Verplanken
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： A method and system for creating on a computer a timing based representation of an integrated circuit using a graphical editor operating on the computer. The method includes first in creating timing diagrams identifying the elements of the circuit and their time based interconnections. The method further comprises a translation of the timing based diagram editor files into HDL statement. The preferred embodiment is described, it comprises the use of an ASCII editor and a translation program to VHDL statements. A system is also described implementing the steps of the method in a computer. In order to avoid having different tools to translate timing based diagram editor files into HDL statements, a first step translating graphical editor output file into a PostScript file is performed by executing the “print to file” command of the printing driver of the computer. The PostScript file is then translated into a bitmap file using a RIP. The translation is then performed from the bitmap file into the HDL statements. This translation is “universal” as it can be used for any type of initial graphical file containing the timing diagram.
摘要翻译：一种用于在计算机上创建使用在计算机上操作的图形编辑器的基于时序的集成电路表示的方法和系统。该方法首先在创建识别电路的元件及其基于时间的互连的时序图。该方法还包括将基于时序的编辑器文件转换为HDL语句。描述了优选实施例，它包括使用ASCII编辑器和对VHDL语句的翻译程序。还描述了在计算机中实现该方法的步骤的系统。为了避免使用不同的工具将基于时序的图编辑器文件转换为HDL语句，将图形编辑器输出文件转换为PostScript文件的第一步是通过执行计算机打印驱动程序的“打印到文件”命令执行的。然后使用RIP将PostScript文件转换为位图文件。然后，转换从位图文件执行到HDL语句。这个翻译是“通用的”，因为它可以用于包含时序图的任何类型的初始图形文件。

3. 发明授权

US5923664A Method and apparatus providing a multiport physical interface to high speed packet networks 失效
标题翻译：向高速分组网络提供多端口物理接口的方法和装置
公开(公告)号：US5923664A
公开(公告)日：1999-07-13
申请号：US824941
申请日：1997-03-27
申请人： Jean-Paul Aldebert , Jean Calvignac , Daniel Orsatti , Fabrice Verplanken , Jean-Claude Zunino
发明人： Jean-Paul Aldebert , Jean Calvignac , Daniel Orsatti , Fabrice Verplanken , Jean-Claude Zunino
IPC分类号： H04L12/70 , H04Q11/04 , H04J3/16 , H04J3/22 , H04J3/24
CPC分类号： H04Q11/0478 , H04L2012/5615
摘要： The invention discloses a method and an apparatus for implementing the physical interface in a network element connected to a packet network such as Asynchronous Transfer Mode (ATM) network. With the solution of the invention, the physical interface functions can be integrated on one chip for more than one network port. The physical interface is provided between port bit streams at media speed and word data flow transferred onto/from a bus which is under the control of the network equipment. The solution of the invention includes grouping logics and storage elements by islands of more than one port. Furthermore, the logics and storage elements for statistical counting operations can be grouped for a processing generalized to all ports. Finally, the solution of the present invention takes into account two characteristics of the physical interface which are the different rates between network link media speed and bus access rate and the technology of the high density static imbedded RAMs used for hardware integration. The Flip/Flop pointer RAMs of Flip/Flop data RAMs are duplicated and some interface RAMs are created to transfer control data between the islands and the generalized processing logical blocks.
摘要翻译：本发明公开了一种在连接到诸如异步传输模式（ATM）网络的分组网络的网络元件中实现物理接口的方法和装置。通过本发明的解决方案，物理接口功能可以集成在多个网络端口的一个芯片上。在媒体速度的端口比特流之间提供物理接口，并且传输到/经由网络设备控制的总线上的字数据流。本发明的解决方案包括通过多于一个端口的岛分组逻辑和存储元件。此外，用于统计计数操作的逻辑和存储元件可以被分组用于对所有端口进行泛化。最后，本发明的解决方案考虑了物理接口的两个特征，它们是网络链路媒体速度和总线访问速率之间的不同速率以及用于硬件集成的高密度静态嵌入RAM的技术。翻转/翻转数据RAM的翻转/翻转指针RAM被复制，并且创建一些接口RAM以在岛和广义处理逻辑块之间传送控制数据。

4. 发明授权

US07921396B2 Data aligner in reconfigurable computing environment 失效
公开(公告)号：US07921396B2
公开(公告)日：2011-04-05
申请号：US12126951
申请日：2008-05-26
申请人： Fabrice Jean Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Louis Calvignac
发明人： Fabrice Jean Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Louis Calvignac
IPC分类号： G06F17/50
CPC分类号： H04L69/16 , H04L49/45 , H04L69/161
摘要： A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.

5. 发明授权

US08037439B2 Data aligner in reconfigurable computing environment 失效
标题翻译：可重构计算环境中的数据对齐器
公开(公告)号：US08037439B2
公开(公告)日：2011-10-11
申请号：US12126953
申请日：2008-05-26
申请人： Fabrice Jean Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Louis Calvignac
发明人： Fabrice Jean Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Louis Calvignac
IPC分类号： G06F17/50
CPC分类号： H04L69/16 , H04L49/45 , H04L69/161
摘要： A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
摘要翻译：公开了可重构计算环境中的数据对准器。实施例使用现场可配置门阵列（FPGA）中的硬件宏来最小化移动数据字节所需的可配置逻辑块（CLB）的数量。与专用集成电路相比，对准机制允许灵活性，可扩展性，可配置性和降低的成本。

6. 发明申请

US20080229271A1 DATA ALIGNER IN RECONFIGURABLE COMPUTING ENVIRONMENT 失效
标题翻译：数据对齐器在可重构计算环境中
公开(公告)号：US20080229271A1
公开(公告)日：2008-09-18
申请号：US12126951
申请日：2008-05-26
申请人： Fabrice Jean Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Louis Calvignac
发明人： Fabrice Jean Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Louis Calvignac
IPC分类号： G06F17/50 , G06F15/16
CPC分类号： H04L69/16 , H04L49/45 , H04L69/161
摘要： A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
摘要翻译：公开了可重构计算环境中的数据对准器。实施例使用现场可配置门阵列（FPGA）中的硬件宏来最小化移动数据字节所需的可配置逻辑块（CLB）的数量。与专用集成电路相比，对准机制允许灵活性，可扩展性，可配置性和降低的成本。

7. 发明授权

US07395517B2 Data aligner in reconfigurable computing environment 失效
标题翻译：可重构计算环境中的数据对齐器
公开(公告)号：US07395517B2
公开(公告)日：2008-07-01
申请号：US11230956
申请日：2005-09-20
申请人： Fabrice Jean Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Louis Calvignac
发明人： Fabrice Jean Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Louis Calvignac
IPC分类号： G06F17/50
CPC分类号： H04L69/16 , H04L49/45 , H04L69/161
摘要： A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
摘要翻译：公开了可重构计算环境中的数据对准器。实施例使用现场可配置门阵列（FPGA）中的硬件宏来最小化移动数据字节所需的可配置逻辑块（CLB）的数量。与专用集成电路相比，对准机制允许灵活性，可扩展性，可配置性和降低的成本。

8. 发明申请

US20080229272A1 DATA ALIGNER IN RECONFIGURABLE COMPUTING ENVIRONMENT 失效
公开(公告)号：US20080229272A1
公开(公告)日：2008-09-18
申请号：US12126953
申请日：2008-05-26
申请人： Fabrice Jean Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Louis Calvignac
发明人： Fabrice Jean Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Louis Calvignac
IPC分类号： G06F17/50 , G06F15/16
CPC分类号： H04L69/16 , H04L49/45 , H04L69/161
摘要： A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.

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